coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: soc/intel: Add definition of D0 stepping for TigerLake Halo
by Felix Singer (Code Review) 05 Mar '24

05 Mar '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80849?usp=email ) Change subject: soc/intel: Add definition of D0 stepping for TigerLake Halo ...................................................................... soc/intel: Add definition of D0 stepping for TigerLake Halo Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80849 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/include/cpu/intel/cpu_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/tigerlake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index d74cf1e..ddb4e54 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -46,6 +46,7 @@ #define CPUID_COMETLAKE_H_S_10_2_Q0 0xa0655 #define CPUID_TIGERLAKE_A0 0x806c0 #define CPUID_TIGERLAKE_B0 0x806c1 +#define CPUID_TIGERLAKE_P0 0x806d0 #define CPUID_TIGERLAKE_R0 0x806d1 #define CPUID_SAPPHIRERAPIDS_SP_A 0x806f0 #define CPUID_SAPPHIRERAPIDS_SP_B 0x806f1 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index bd43545..3cff621 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -71,6 +71,7 @@ { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_B0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_TIGERLAKE_P0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_R0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_B0, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 1ecaf77..8f90b3c 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -25,6 +25,7 @@ } cpu_table[] = { { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, { CPUID_TIGERLAKE_B0, "Tigerlake B0" }, + { CPUID_TIGERLAKE_P0, "Tigerlake P0" }, { CPUID_TIGERLAKE_R0, "Tigerlake R0" }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/80849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Gerrit-Change-Number: 80849 Gerrit-PatchSet: 3 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports
by Felix Singer (Code Review) 05 Mar '24

05 Mar '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80848?usp=email ) Change subject: soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports ...................................................................... soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports ACPI _PRT method was missing from PEG (SoC PCI-E) links, resulting in OS complaining about interrupt routing. 'pcieport 0000:00:06.0: can't derive routing for PCI INT A' 'nvme 0000:04:00.0: PCI INT A: not connected' 'Interrupt: pin A routed to IRQ -2147483648' TEST=Boot Linux and Windows 10 on TGL-H platform with PEG0/PEG1 populated with PCI-E devices - Radeon RX 7800XT and Kingston KC3000 NVME SSD. Check logs and stability while running 3D application and disk benchmark at the same time. Change-Id: If102522efa1a67b362b14d859d9e27a37bad85a4 Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80848 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/soc/intel/tigerlake/acpi/pcie.asl 1 file changed, 48 insertions(+), 0 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl index a25335c..86d53fe 100644 --- a/src/soc/intel/tigerlake/acpi/pcie.asl +++ b/src/soc/intel/tigerlake/acpi/pcie.asl @@ -115,22 +115,70 @@ Device (PEG0) { Name (_ADR, 0x00060000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } } #if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H) Device (PEG1) { Name (_ADR, 0x00010000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } } Device (PEG2) { Name (_ADR, 0x00010001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } } Device (PEG3) { Name (_ADR, 0x00010002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/80848?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If102522efa1a67b362b14d859d9e27a37bad85a4 Gerrit-Change-Number: 80848 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports
by Felix Singer (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Alicja Michalska, Arthur Heymans, Martin L Roth, Nick Vaccaro. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80848?usp=email ) Change subject: soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80848/comment/a09ad7f3_1e5a9429 : PS1, Line 16: Boot Linux > Yes, pci=nomsi breaks NVME altogether. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80848?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If102522efa1a67b362b14d859d9e27a37bad85a4 Gerrit-Change-Number: 80848 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 05 Mar 2024 23:28:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel: Add definition of D0 stepping for TigerLake Halo
by Felix Singer (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Alicja Michalska, Nick Vaccaro, Subrata Banik. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80849?usp=email ) Change subject: soc/intel: Add definition of D0 stepping for TigerLake Halo ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Gerrit-Change-Number: 80849 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Mar 2024 23:19:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel: Add definition of D0 stepping for TigerLake Halo
by Alicja Michalska (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Felix Singer, Nick Vaccaro, Subrata Banik. Alicja Michalska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80849?usp=email ) Change subject: soc/intel: Add definition of D0 stepping for TigerLake Halo ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/tigerlake/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/80849/comment/e70606de_4c3782d3 : PS1, Line 28: B0 > should be P0 Thanks for heads-up! -- To view, visit https://review.coreboot.org/c/coreboot/+/80849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Gerrit-Change-Number: 80849 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Mar 2024 23:16:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel: Add definition of D0 stepping for TigerLake Halo
by Alicja Michalska (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Alicja Michalska, Felix Singer, Nick Vaccaro, Subrata Banik. Hello Felix Singer, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80849?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Felix Singer, Verified+1 by build bot (Jenkins) Change subject: soc/intel: Add definition of D0 stepping for TigerLake Halo ...................................................................... soc/intel: Add definition of D0 stepping for TigerLake Halo Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- M src/include/cpu/intel/cpu_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/tigerlake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/80849/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Gerrit-Change-Number: 80849 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel: Add definition of D0 stepping for TigerLake Halo
by Felix Singer (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Alicja Michalska, Nick Vaccaro, Subrata Banik. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80849?usp=email ) Change subject: soc/intel: Add definition of D0 stepping for TigerLake Halo ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Gerrit-Change-Number: 80849 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Mar 2024 23:04:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel: Add definition of D0 stepping for TigerLake Halo
by Felix Singer (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Alicja Michalska, Nick Vaccaro, Subrata Banik. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80849?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel: Add definition of D0 stepping for TigerLake Halo ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/tigerlake/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/80849/comment/9e7bcd9b_f798aafb : PS1, Line 28: B0 should be P0 -- To view, visit https://review.coreboot.org/c/coreboot/+/80849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Gerrit-Change-Number: 80849 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Mar 2024 23:04:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[NoOp] Change in blobs[main]: mb/erying/tgl: Add blobs necessary for platform bring-up
by Felix Singer (Code Review) 05 Mar '24

05 Mar '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/blobs/+/80852?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/erying/tgl: Add blobs necessary for platform bring-up ...................................................................... mb/erying/tgl: Add blobs necessary for platform bring-up Flash Descriptor and Management Engine blobs extracted from stock. Microcodes from public GitHub repository, as Intel doesn't carry microcode for D0 stepping in their tree. Change-Id: I9ee9e031969b477d2d9f63f7e49a113bd4380f91 Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- A mainboard/erying/tgl/cpu806D0_platC2_ver00000054_2021-05-07_PRD_B0F9E245.bin A mainboard/erying/tgl/cpu806D1_platC2_ver00000046_2023-02-27_PRD_08E6188A.bin A mainboard/erying/tgl/fd.bin A mainboard/erying/tgl/me.bin 4 files changed, 0 insertions(+), 0 deletions(-) Approvals: Felix Singer: Verified; Looks good to me, approved diff --git a/mainboard/erying/tgl/cpu806D0_platC2_ver00000054_2021-05-07_PRD_B0F9E245.bin b/mainboard/erying/tgl/cpu806D0_platC2_ver00000054_2021-05-07_PRD_B0F9E245.bin new file mode 100644 index 0000000..a5182ce --- /dev/null +++ b/mainboard/erying/tgl/cpu806D0_platC2_ver00000054_2021-05-07_PRD_B0F9E245.bin Binary files differ diff --git a/mainboard/erying/tgl/cpu806D1_platC2_ver00000046_2023-02-27_PRD_08E6188A.bin b/mainboard/erying/tgl/cpu806D1_platC2_ver00000046_2023-02-27_PRD_08E6188A.bin new file mode 100644 index 0000000..e1b6851 --- /dev/null +++ b/mainboard/erying/tgl/cpu806D1_platC2_ver00000046_2023-02-27_PRD_08E6188A.bin Binary files differ diff --git a/mainboard/erying/tgl/fd.bin b/mainboard/erying/tgl/fd.bin new file mode 100644 index 0000000..0ba6d5e --- /dev/null +++ b/mainboard/erying/tgl/fd.bin Binary files differ diff --git a/mainboard/erying/tgl/me.bin b/mainboard/erying/tgl/me.bin new file mode 100644 index 0000000..05b2555 --- /dev/null +++ b/mainboard/erying/tgl/me.bin Binary files differ -- To view, visit https://review.coreboot.org/c/blobs/+/80852?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I9ee9e031969b477d2d9f63f7e49a113bd4380f91 Gerrit-Change-Number: 80852 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel: Add definition of D0 stepping for TigerLake Halo
by Felix Singer (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Alicja Michalska, Nick Vaccaro, Subrata Banik. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80849?usp=email ) Change subject: soc/intel: Add definition of D0 stepping for TigerLake Halo ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Gerrit-Change-Number: 80849 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Mar 2024 22:50:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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