coreboot-gerrit March 2024

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
by Jérémy Compostella (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Andrey Petrov, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, Wonkyu Kim. Hello Andrey Petrov, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Tarun, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80275?usp=email to look at the new patch set (#20). Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support ...................................................................... drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support Intel Firmware Support Package 2.4 specification (document 736809) brings some significant changes compared to version 2.3 (document 644852): 1. It supports FSP-M multi-phase init. Some fields have been added to the FSP header data structure for this purpose. 2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively. 3. It support 64-bits FSP but 64-bits support will be provided by subsequent patch. Note that similarly to what is done for silicon initialization, timestamps and post-codes are used during the memory initialization multi-phase. [736809] https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf [644852] https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-… TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/commonlib/include/commonlib/console/post_codes.h M src/commonlib/include/commonlib/timestamp_serialized.h M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/upd_display.c M util/cbfstool/eventlog.c 10 files changed, 124 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/80275/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/80275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Gerrit-Change-Number: 80275 Gerrit-PatchSet: 20 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
by Jérémy Compostella (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Andrey Petrov, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, Wonkyu Kim. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80275?usp=email ) Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support ...................................................................... Patch Set 19: (2 comments) File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/80275/comment/e3b1f3d9_7a1fedfb : PS16, Line 25: platform_fsp_silicon_multi_phase_init_cb > keep platform_fsp_silicon_multi_phase_init_cb and associated SoC file changes in a separate CL as ba […] Done File util/cbfstool/eventlog.c: https://review.coreboot.org/c/coreboot/+/80275/comment/96096398_e28985d9 : PS17, Line 410: {POSTCODE_FSP_MULTI_PHASE_INIT_ENTRY, "FSP-M/S Multi Phase Init Enter"}, > I still need to take care of this. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Gerrit-Change-Number: 80275 Gerrit-PatchSet: 19 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 19:26:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Add "silicon" to the multiphase callback name
by Jérémy Compostella (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Andrey Petrov, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik, Tarun. Hello Andrey Petrov, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81094?usp=email to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0: Add "silicon" to the multiphase callback name ...................................................................... drivers/intel/fsp2_0: Add "silicon" to the multiphase callback name The `platform_fsp_multi_phase_init_cb' callback is specific to the FSP-S, let's rename it 'platform_fsp_silicon_multi_phase_init_cb' to avoid any confusion. Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/silicon_init.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/tigerlake/fsp_params.c 5 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/81094/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81094?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee Gerrit-Change-Number: 81094 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Add "silicon" to the multiphase callback
by Jérémy Compostella (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Andrey Petrov, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik, Tarun. Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81094?usp=email ) Change subject: drivers/intel/fsp2_0: Add "silicon" to the multiphase callback ...................................................................... drivers/intel/fsp2_0: Add "silicon" to the multiphase callback The `platform_fsp_multi_phase_init_cb' callback is specific to the FSP-S, let's rename it 'platform_fsp_silicon_multi_phase_init_cb' to avoid any confusion. Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/silicon_init.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/tigerlake/fsp_params.c 5 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/81094/1 diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index c035452..40a64e6 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -48,7 +48,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); /* Callbacks for SoC/Mainboard specific overrides */ -void platform_fsp_multi_phase_init_cb(uint32_t phase_index); +void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index); /* Check if MultiPhase Si Init is enabled */ bool fsp_is_multi_phase_init_enabled(void); /* diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index e543628..4be4b61 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -27,7 +27,7 @@ }; /* Callbacks for SoC/Mainboard specific overrides */ -void __weak platform_fsp_multi_phase_init_cb(uint32_t phase_index) +void __weak platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index) { /* Leave for the SoC/Mainboard to implement if necessary. */ } @@ -190,7 +190,7 @@ * Give SoC/mainboard a chance to perform any operation before * Multi Phase Execution */ - platform_fsp_multi_phase_init_cb(i); + platform_fsp_silicon_multi_phase_init_cb(i); multi_phase_params.multi_phase_action = EXECUTE_PHASE; multi_phase_params.phase_index = i; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index b432030..46555b0 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -1342,7 +1342,7 @@ * 1 | After TCSS initialization completed | for TCSS specific init * 2 | Before BIOS Reset CPL is set by FSP-S | for CPU specific init */ -void platform_fsp_multi_phase_init_cb(uint32_t phase_index) +void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index) { switch (phase_index) { case 1: diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 971fa33..a02d4b9 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -838,7 +838,7 @@ * 1 | After TCSS initialization completed | for TCSS specific init * 2 | Before BIOS Reset CPL is set by FSP-S | for CPU specific init */ -void platform_fsp_multi_phase_init_cb(uint32_t phase_index) +void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index) { switch (phase_index) { case 1: diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 358536e..3326935 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -659,7 +659,7 @@ * ------- + ------------------------------------------------ + ------------------------------- * 1 | After TCSS initialization completed | for TCSS specific init */ -void platform_fsp_multi_phase_init_cb(uint32_t phase_index) +void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index) { switch (phase_index) { case 1: -- To view, visit https://review.coreboot.org/c/coreboot/+/81094?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee Gerrit-Change-Number: 81094 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
by Jérémy Compostella (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Andrey Petrov, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Tarun, Wonkyu Kim. Hello Andrey Petrov, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Tarun, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80275?usp=email to look at the new patch set (#18). Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support ...................................................................... drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support Intel Firmware Support Package 2.4 specification (document 736809) brings some significant changes compared to version 2.3 (document 644852): 1. It supports FSP-M multi-phase init. Some fields have been added to the FSP header data structure for this purpose. 2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively. 3. It support 64-bits FSP but 64-bits support will be provided by subsequent patch. Note that similarly to what is done for silicon initialization, timestamps and post-codes are used during the memory initialization multi-phase. [736809] https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf [644852] https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-… TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/commonlib/include/commonlib/console/post_codes.h M src/commonlib/include/commonlib/timestamp_serialized.h M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/upd_display.c M util/cbfstool/eventlog.c 10 files changed, 125 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/80275/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/80275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Gerrit-Change-Number: 80275 Gerrit-PatchSet: 18 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/emulation/qemu-riscv: Change to -bios option
by ron minnich (Code Review) 05 Mar '24

05 Mar '24

ron minnich has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80746?usp=email ) Change subject: mb/emulation/qemu-riscv: Change to -bios option ...................................................................... mb/emulation/qemu-riscv: Change to -bios option This changes the virt target so that it can be run with the -bios option and a pflash backend for the flash. QEMU can now be run as follows: qemu -M virt -m 1G -nographic -bios build/coreboot.rom \ -drive if=pflash,file=./build/coreboot.rom,format=raw coreboot will start in DRAM, but still have a flash to put CBFS onto and to load subsequent stages and payload from. Tested bootflow: coreboot -> OpenSBI -> Linux -> u-root Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80746 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: ron minnich <rminnich(a)gmail.com> Reviewed-by: Philipp Hug <philipp(a)hug.cx> --- M Documentation/mainboard/emulation/qemu-riscv.md M src/mainboard/emulation/Kconfig M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Makefile.mk A src/mainboard/emulation/qemu-riscv/cbmem.c A src/mainboard/emulation/qemu-riscv/chip.c M src/mainboard/emulation/qemu-riscv/devicetree.cb M src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h M src/mainboard/emulation/qemu-riscv/mainboard.c M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/qemu-riscv/rom_media.c M src/mainboard/emulation/qemu-riscv/romstage.c M util/qemu/Makefile.mk 13 files changed, 98 insertions(+), 55 deletions(-) Approvals: Philipp Hug: Looks good to me, approved build bot (Jenkins): Verified ron minnich: Looks good to me, approved diff --git a/Documentation/mainboard/emulation/qemu-riscv.md b/Documentation/mainboard/emulation/qemu-riscv.md index ed2c6d5..9ccc1b7 100644 --- a/Documentation/mainboard/emulation/qemu-riscv.md +++ b/Documentation/mainboard/emulation/qemu-riscv.md @@ -3,6 +3,9 @@ ## Building coreboot and running it in QEMU - Configure coreboot and run `make` as usual -- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to - convert coreboot to an ELF that QEMU can load -- Run `qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf` + +Run QEMU +``` +qemu-system-riscv64 -M virt -m 1G -nographic -bios build/coreboot.rom \ + -drive if=pflash,file=./build/coreboot.rom,format=raw +``` diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index f00b1fb..5f596b8 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -1,5 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only +# ugly to put it in here, but unavoidable +config SEPARATE_ROMSTAGE + default n if BOARD_EMULATION_QEMU_RISCV + if VENDOR_EMULATION choice diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index af4416d..94f9e56 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -1,8 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only # To execute, do: -# qemu-system-riscv64 -M virt -m 1024M -nographic -bios build/coreboot.rom - +# qemu-system-riscv64 -M virt -m 1024M -nographic -bios build/coreboot.rom \ +# -drive if=pflash,file=build/coreboot.rom,format=raw if BOARD_EMULATION_QEMU_RISCV_RV64 @@ -22,12 +22,18 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SOC_UCB_RISCV - select BOARD_ROMSIZE_KB_16384 - select BOOT_DEVICE_NOT_SPI_FLASH + select BOARD_ROMSIZE_KB_32768 select MISSING_BOARD_RESET select DRIVERS_UART_8250MEM select RISCV_HAS_OPENSBI + select ARCH_RISCV_S + select ARCH_RISCV_U + select ARCH_RISCV_PMP + select ARCH_BOOTBLOCK_RISCV + select ARCH_VERSTAGE_RISCV + select ARCH_ROMSTAGE_RISCV + select ARCH_RAMSTAGE_RISCV + select RISCV_USE_ARCH_TIMER config MEMLAYOUT_LD_FILE string @@ -43,6 +49,25 @@ int default 1 +config RISCV_ARCH + string + default "rv64imafd" if ARCH_RISCV_RV64 + default "rv32im" if ARCH_RISCV_RV32 + +config RISCV_ABI + string + default "lp64d" if ARCH_RISCV_RV64 + default "ilp32" if ARCH_RISCV_RV32 + +config RISCV_CODEMODEL + string + default "medany" if ARCH_RISCV_RV64 + default "medany" if ARCH_RISCV_RV32 + +config RISCV_WORKING_HARTID + int + default 0 + config DRAM_SIZE_MB int default 16383 @@ -54,20 +79,8 @@ string default "generic" -# ugly, but CBFS is placed in DRAM... config OPENSBI_TEXT_START hex - default 0x80040000 if COREBOOT_ROMSIZE_KB_256 - default 0x80080000 if COREBOOT_ROMSIZE_KB_512 - default 0x80100000 if COREBOOT_ROMSIZE_KB_1024 - default 0x80200000 if COREBOOT_ROMSIZE_KB_2048 - default 0x80400000 if COREBOOT_ROMSIZE_KB_4096 - default 0x80600000 if COREBOOT_ROMSIZE_KB_6144 - default 0x80800000 if COREBOOT_ROMSIZE_KB_8192 - default 0x80a00000 if COREBOOT_ROMSIZE_KB_10240 - default 0x80c00000 if COREBOOT_ROMSIZE_KB_12288 - default 0x81000000 if COREBOOT_ROMSIZE_KB_16384 - default 0x82000000 if COREBOOT_ROMSIZE_KB_32768 - default 0x84000000 if COREBOOT_ROMSIZE_KB_65536 + default 0x80020000 endif # BOARD_EMULATION_QEMU_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.mk b/src/mainboard/emulation/qemu-riscv/Makefile.mk index 1a8342d..bed0f80 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.mk +++ b/src/mainboard/emulation/qemu-riscv/Makefile.mk @@ -1,16 +1,21 @@ ## SPDX-License-Identifier: GPL-2.0-only +bootblock-y += mainboard.c bootblock-y += uart.c bootblock-y += rom_media.c bootblock-y += clint.c +romstage-y += cbmem.c romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c romstage-y += clint.c +ramstage-y += mainboard.c ramstage-y += uart.c ramstage-y += rom_media.c ramstage-y += clint.c +ramstage-y += cbmem.c +ramstage-y += chip.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/emulation/qemu-riscv/cbmem.c b/src/mainboard/emulation/qemu-riscv/cbmem.c new file mode 100644 index 0000000..10ca2cd --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/cbmem.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <symbols.h> +#include <ramdetect.h> +#include <console/console.h> + +uintptr_t cbmem_top_chipset(void) +{ + //TODO get memory range from QEMUs FDT + size_t dram_mb_detected = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB); + return (uintptr_t)_dram + dram_mb_detected * MiB; +} diff --git a/src/mainboard/emulation/qemu-riscv/chip.c b/src/mainboard/emulation/qemu-riscv/chip.c new file mode 100644 index 0000000..5cec284 --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/chip.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +struct chip_operations mainboard_emulation_qemu_riscv_ops = { + .name = "QEMU RISC-V", +}; diff --git a/src/mainboard/emulation/qemu-riscv/devicetree.cb b/src/mainboard/emulation/qemu-riscv/devicetree.cb index 120af99..9de1b75 100644 --- a/src/mainboard/emulation/qemu-riscv/devicetree.cb +++ b/src/mainboard/emulation/qemu-riscv/devicetree.cb @@ -1,5 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -chip soc/ucb/riscv +chip mainboard/emulation/qemu-riscv device cpu_cluster 0 on end end diff --git a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h index 27baeb7..542e395 100644 --- a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h +++ b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h @@ -4,4 +4,5 @@ #define QEMU_VIRT_PLIC 0x0c000000 #define QEMU_VIRT_UART0 0x10000000 #define QEMU_VIRT_VIRTIO 0x10001000 +#define QEMU_VIRT_FLASH 0x20000000 #define QEMU_VIRT_DRAM 0x80000000 diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index f0f0740..e17ce13 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -3,18 +3,15 @@ #include <console/console.h> #include <device/device.h> #include <symbols.h> -#include <ramdetect.h> +#include <cbmem.h> static void mainboard_enable(struct device *dev) { - size_t dram_mb_detected; - if (!dev) { die("No dev0; die\n"); } - dram_mb_detected = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB); - ram_range(dev, 0, (uintptr_t)_dram, dram_mb_detected * MiB); + ram_from_to(dev, 0, (uintptr_t)_dram, (uintptr_t)cbmem_top()); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 4fdeb9dc..9c16496 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -4,28 +4,17 @@ #include <arch/header.ld> #include <mainboard/addressmap.h> -// Stages start after CBFS in DRAM -#define STAGES_START (QEMU_VIRT_DRAM + CONFIG_ROM_SIZE) - SECTIONS { - // the virt target doesn't emulate flash and just puts the CBFS into DRAM. - // fake SRAM where CBFS resides. It's only done for better integration. - SRAM_START(QEMU_VIRT_DRAM) - BOOTBLOCK(QEMU_VIRT_DRAM, 64K) - // CBFS goes here - SRAM_END(STAGES_START) - DRAM_START(STAGES_START) + REGION(flash, QEMU_VIRT_FLASH, CONFIG_ROM_SIZE, 0) \ -#if ENV_SEPARATE_ROMSTAGE - ROMSTAGE(STAGES_START, 128K) -#endif -#if ENV_RAMSTAGE - REGION(opensbi, STAGES_START, 128K, 4K) -#endif - PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) - FMAP_CACHE(STAGES_START + 136K, 2K) - CBFS_MCACHE(STAGES_START + 138K, 8K) - RAMSTAGE(STAGES_START + 200K, 16M) - STACK(STAGES_START + 200K + 16M, 4K) + DRAM_START(QEMU_VIRT_DRAM) + BOOTBLOCK(QEMU_VIRT_DRAM, 128K) + OPENSBI(QEMU_VIRT_DRAM + 128K, 256K) + ROMSTAGE(QEMU_VIRT_DRAM + 128K + 256K, 256K) + RAMSTAGE(QEMU_VIRT_DRAM + 128K + 256K + 256K, 2M) + PRERAM_CBMEM_CONSOLE(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M, 8K) + FMAP_CACHE(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K, 2K) + CBFS_MCACHE(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K + 2K, 10K) + STACK(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K + 2K + 10K, 4M) } diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index 15989f2..3c636ce 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -1,11 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot_device.h> #include <symbols.h> +#include <mainboard/addressmap.h> -/* This assumes that the CBFS resides at start of dram, which is true for the - * default configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(_sram, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(QEMU_VIRT_FLASH, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { diff --git a/src/mainboard/emulation/qemu-riscv/romstage.c b/src/mainboard/emulation/qemu-riscv/romstage.c index 4a3ed83..39df9ad 100644 --- a/src/mainboard/emulation/qemu-riscv/romstage.c +++ b/src/mainboard/emulation/qemu-riscv/romstage.c @@ -3,10 +3,20 @@ #include <cbmem.h> #include <console/console.h> #include <program_loading.h> +#include <romstage_common.h> + +void __noreturn romstage_main(void) +{ + cbmem_initialize_empty(); + run_ramstage(); +} + +#if CONFIG(SEPARATE_ROMSTAGE) void main(void) { console_init(); - cbmem_initialize_empty(); - run_ramstage(); + romstage_main(); } + +#endif diff --git a/util/qemu/Makefile.mk b/util/qemu/Makefile.mk index 42441df..7b9b636 100644 --- a/util/qemu/Makefile.mk +++ b/util/qemu/Makefile.mk @@ -29,9 +29,11 @@ QEMU-$(CONFIG_BOARD_EMULATION_QEMU_AARCH64) ?= qemu-system-aarch64 \ -M virt,secure=on,virtualization=on -cpu cortex-a53 -m 1G -QEMU-$(CONFIG_BOARD_EMULATION_QEMU_RISCV_RV64) ?= qemu-system-riscv64 -M virt +QEMU-$(CONFIG_BOARD_EMULATION_QEMU_RISCV_RV64) ?= qemu-system-riscv64 -M virt -m 1G -drive \ + if=pflash,file=build/coreboot.rom,format=raw -QEMU-$(CONFIG_BOARD_EMULATION_QEMU_RISCV_RV32) ?= qemu-system-riscv32 -M virt +QEMU-$(CONFIG_BOARD_EMULATION_QEMU_RISCV_RV32) ?= qemu-system-riscv32 -M virt -m 1G -drive \ + if=pflash,file=build/coreboot.rom,format=raw QEMU-$(CONFIG_BOARD_EMULATION_QEMU_X86_I440FX) ?= qemu-system-x86_64 -M pc -- To view, visit https://review.coreboot.org/c/coreboot/+/80746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Gerrit-Change-Number: 80746 Gerrit-PatchSet: 9 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: vc/amd/opensil/genoa_poc/memmap: use GiB define
by Felix Held (Code Review) 05 Mar '24

05 Mar '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81093?usp=email ) Change subject: vc/amd/opensil/genoa_poc/memmap: use GiB define ...................................................................... vc/amd/opensil/genoa_poc/memmap: use GiB define Use the GiB define to make the 4 GiB boundary used in some places in the code a bit easier to read. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I81877a5d293c883d2e31bdb18ae3b22b8a44e62f --- M src/vendorcode/amd/opensil/genoa_poc/memmap.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/81093/1 diff --git a/src/vendorcode/amd/opensil/genoa_poc/memmap.c b/src/vendorcode/amd/opensil/genoa_poc/memmap.c index 31e6f04..b1d4b93 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/memmap.c +++ b/src/vendorcode/amd/opensil/genoa_poc/memmap.c @@ -115,7 +115,7 @@ reserved_ram_from_to(dev, (*idx)++, mem_usable, top_mem); // Check if we're done - if (top_of_mem <= 0x100000000) + if (top_of_mem <= 4ULL * GiB) return; // Holes in upper DRAM @@ -124,11 +124,11 @@ if (hole_info == NULL) return; uint64_t lowest_upper_hole_base = top_of_mem; - uint64_t highest_upper_hole_end = 0x100000000; + uint64_t highest_upper_hole_end = 4ULL * GiB; for (int hole = 0; hole < n_holes; hole++) { if (hole_info[hole].Type == MMIO) continue; - if (hole_info[hole].Base < 0x100000000) + if (hole_info[hole].Base < 4ULL * GiB) continue; lowest_upper_hole_base = MIN(lowest_upper_hole_base, hole_info[hole].Base); highest_upper_hole_end = MAX(highest_upper_hole_end, hole_info[hole].Base + hole_info[hole].Size); @@ -138,7 +138,7 @@ reserved_ram_range(dev, (*idx)++, hole_info[hole].Base, hole_info[hole].Size); } - ram_from_to(dev, (*idx)++, 0x100000000, lowest_upper_hole_base); + ram_from_to(dev, (*idx)++, 4ULL * GiB, lowest_upper_hole_base); // Do we need this? if (top_of_mem > highest_upper_hole_end) -- To view, visit https://review.coreboot.org/c/coreboot/+/81093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I81877a5d293c883d2e31bdb18ae3b22b8a44e62f Gerrit-Change-Number: 81093 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: vc/amd/opensil/genoa_poc/memmap: use get_top_of_mem_below_4gb
by Felix Held (Code Review) 05 Mar '24

05 Mar '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81092?usp=email ) Change subject: vc/amd/opensil/genoa_poc/memmap: use get_top_of_mem_below_4gb ...................................................................... vc/amd/opensil/genoa_poc/memmap: use get_top_of_mem_below_4gb Use get_top_of_mem_below_4gb instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5885e9ad89ed9f0aa657c56804e98c352267267f --- M src/vendorcode/amd/opensil/genoa_poc/memmap.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/81092/1 diff --git a/src/vendorcode/amd/opensil/genoa_poc/memmap.c b/src/vendorcode/amd/opensil/genoa_poc/memmap.c index 39b27ec..31e6f04 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/memmap.c +++ b/src/vendorcode/amd/opensil/genoa_poc/memmap.c @@ -110,7 +110,7 @@ mem_usable); // Account for UMA and TSEG - const uint32_t top_mem = ALIGN_DOWN(rdmsr(TOP_MEM).lo, 1 * MiB); + const uint32_t top_mem = ALIGN_DOWN(get_top_of_mem_below_4gb(), 1 * MiB); if (mem_usable != top_mem) reserved_ram_from_to(dev, (*idx)++, mem_usable, top_mem); -- To view, visit https://review.coreboot.org/c/coreboot/+/81092?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5885e9ad89ed9f0aa657c56804e98c352267267f Gerrit-Change-Number: 81092 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
by Jérémy Compostella (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Andrey Petrov, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Tarun, Wonkyu Kim. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80275?usp=email ) Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support ...................................................................... Patch Set 17: (1 comment) File util/cbfstool/eventlog.c: https://review.coreboot.org/c/coreboot/+/80275/comment/f88a1e1a_1eabf2df : PS17, Line 410: {POSTCODE_FSP_MULTI_PHASE_INIT_ENTRY, "FSP-M/S Multi Phase Init Enter"}, I still need to take care of this. -- To view, visit https://review.coreboot.org/c/coreboot/+/80275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Gerrit-Change-Number: 80275 Gerrit-PatchSet: 17 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 17:58:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/emulation/riscv: Limit DRAM size
by Philipp Hug (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Alper Nebi Yasak, Arthur Heymans, Christian Walter, Maximilian Brune, Nico Huber. Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68843?usp=email ) Change subject: mb/emulation/riscv: Limit DRAM size ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: superseeded by 36486 -- To view, visit https://review.coreboot.org/c/coreboot/+/68843?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib8555de361d1129d3d1995f056518c576f055515 Gerrit-Change-Number: 68843 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 17:58:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2024