coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

1 participants
3668 discussions

[M] Change in libgfxinit[main]: gma: Update DP training with new fields
by Nico Huber (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Angel Pons, Arthur Heymans, Jérémy Compostella, Nick Vaccaro, Shelley Chen, Subrata Banik, Tarun Tuli, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/67490?usp=email ) Change subject: gma: Update DP training with new fields ...................................................................... Patch Set 24: (1 comment) Patchset: PS23: > @Nico/Arthur: can you please help to mark V+1 … [View More]which might help us to land this CL? See other comments. Basically this change can be abandoned and a better solution can be integrated into CB:67499. I'm working on that now. I have TGL hardware at hand and everything up to CB:67500 pieced together on a local branch. I'll push it when I have it working (hopefully next week). Some of the ADL work has already been integrated into the TGL patches. I suggest that we rebase and retest what is left once CB:67500 has landed. I'll leave this comment open so it's not overlooked. -- To view, visit https://review.coreboot.org/c/libgfxinit/+/67490?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: main Gerrit-Change-Id: I3f7f8a93408a74cfa29d1493a48c88ce73dc690c Gerrit-Change-Number: 67490 Gerrit-PatchSet: 24 Gerrit-Owner: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 07 Mar 2024 21:37:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment [View Less]

1 0

[M] Change in coreboot[main]: arch/riscv: use PMP
by ron minnich (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81090?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/riscv: use PMP ..............................................................… [View More]........ arch/riscv: use PMP With this change, a simple S-mode payload works: 1: li a7, 1 li a0, 48 ecall j 1b Without this change, it will not work. Linux also boots with this on the command line: clk_ignore_unused Resolving that problem will require a separate patch. Getting this to build on RV32 required changes to the API, as it was incorrect. In RV32, PMP entries are 34 bits. Hence, the setup_pmp needed to accept u64. So, uinptr_t can not be used, as on 32 bits they are only 32 bit numbers. The internal API uses uintptr_t, but the exported API uses u64, so external code does not have to think about right shifts on base and size. Errors are detected: an error in base and size will result in a BIOS_EMERG print, but not a panic. Boots not bricks if possible. There are small changes to the internal API to reduce stack pressure: there's no need to have two pmpcfg_t on the stack when one will do. Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/include/arch/pmp.h M src/arch/riscv/payload.c M src/arch/riscv/pmp.c 3 files changed, 112 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/81090/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/81090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Gerrit-Change-Number: 81090 Gerrit-PatchSet: 14 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset [View Less]

1 0

[XS] Change in coreboot[main]: soc/intel/alderlake: Drop superfluous default for ADL-N FSP headers
by Subrata Banik (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Dinesh Gehlot, Felix Singer, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81116?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/alderlake: Drop superfluous default for ADL-N FSP headers ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: can you … [View More]

1 0

[XS] Change in coreboot[main]: Add a new config variable, RISCV_PRIV_VERSION
by ron minnich (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Arthur Heymans, Philipp Hug. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81088?usp=email ) Change subject: Add a new config variable, RISCV_PRIV_VERSION ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I don't actually like this any more, prob should test it in a register? Asssuming that works at all. -- To view, visit https://review.… [View More]

1 0

[XS] Change in coreboot[main]: soc/intel/alderlake: Drop superfluous default for ADL-N FSP headers
by ron minnich (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Dinesh Gehlot, Felix Singer, Kapil Porwal, Nick Vaccaro, Subrata Banik. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81116?usp=email ) Change subject: soc/intel/alderlake: Drop superfluous default for ADL-N FSP headers ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81116?usp=email To unsubscribe, … [View More]

1 0

[M] Change in coreboot[main]: arch/riscv: use PMP
by ron minnich (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81090?usp=email to look at the new patch set (#13). Change subject: arch/riscv: use PMP ...................................................................... arch/riscv: use PMP With this change, a simple S-mode payload works: 1: li a7, … [View More]1 li a0, 48 ecall j 1b Without this change, it will not work. Linux also boots with this on the command line: clk_ignore_unused Resolving that problem will require a separate patch. Getting this to build on RV32 required changes to the API, as it was incorrect. In RV32, PMP entries are 34 bits. Hence, the setup_pmp needed to accept u64. So, uinptr_t can not be used, as on 32 bits they are only 32 bit numbers. The internal API uses uintptr_t, but the exported API uses u64, so external code does not have to think about right shifts on base and size. Errors are detected: an error in base and size will result in a BIOS_EMERG print, but not a panic. Boots not bricks if possible. There are small changes to the internal API to reduce stack pressure: there's no need to have two pmpcfg_t on the stack when one will do. Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/include/arch/pmp.h M src/arch/riscv/payload.c M src/arch/riscv/pmp.c 3 files changed, 111 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/81090/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/81090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Gerrit-Change-Number: 81090 Gerrit-PatchSet: 13 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset [View Less]

1 0

[XL] Change in coreboot[main]: vc/intel/fsp/mtl: Update header files from 3471_85 to 3471_91
by Subrata Banik (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Kapil Porwal, Krishna P Bhat D, Ronak Kanabar, Vikrant L Jadeja, srinivas.kulkarni(a)intel.com. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80782?usp=email ) Change subject: vc/intel/fsp/mtl: Update header files from 3471_85 to 3471_91 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80782?usp=… [View More]

1 0

[S] Change in coreboot[main]: soc/intel/cmn/cse: Simplify logic to get CSE RW version
by Paul Menzel (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Arthur Heymans, Kapil Porwal, Nick Vaccaro. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81051?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/cmn/cse: Simplify logic to get CSE RW version ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: By the way `src/sbom/Makefile.mk` … [View More]

1 0

[S] Change in coreboot[main]: soc/intel/cmn/cse: Simplify logic to get CSE RW version
by Paul Menzel (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Arthur Heymans, Kapil Porwal, Nick Vaccaro. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81051?usp=email ) Change subject: soc/intel/cmn/cse: Simplify logic to get CSE RW version ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81051?usp=email To unsubscribe, or for help writing mail filters, visit … [View More]

1 0

[M] Change in coreboot[main]: arch/riscv: use PMP
by ron minnich (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81090?usp=email to look at the new patch set (#12). Change subject: arch/riscv: use PMP ...................................................................... arch/riscv: use PMP With this change, a simple S-mode payload works: 1: li a7, … [View More]1 li a0, 48 ecall j 1b Without this change, it will not work. Linux also boots with this on the command line: clk_ignore_unused Resolving that problem will require a separate patch. Getting this to build on RV32 required changes to the API, as it was incorrect. In RV32, PMP entries are 34 bits. Hence, the setup_pmp needed to accept u64. So, uinptr_t can not be used, as on 32 bits they are only 32 bit numbers. The internal API uses uintptr_t, but the exported API uses u64, so external code does not have to think about right shifts on base and size. Errors are detected: an error in base and size will result in a BIOS_EMERG print, but not a panic. Boots not bricks if possible. There are small changes to the internal API to reduce stack pressure: there's no need to have two pmpcfg_t on the stack when one will do. Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/include/arch/pmp.h M src/arch/riscv/payload.c M src/arch/riscv/pmp.c 3 files changed, 110 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/81090/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/81090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Gerrit-Change-Number: 81090 Gerrit-PatchSet: 12 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset [View Less]

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2024