coreboot-gerrit March 2024

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[S] Change in coreboot[main]: brox: ish: Add Kconfigs for ISH
by Karthik Ramasubramanian (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Martin L Roth, Shelley Chen, Yuval Peress. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81050?usp=email ) Change subject: brox: ish: Add Kconfigs for ISH ...................................................................... Patch Set 4: (2 comments) File src/mainboard/google/brox/Kconfig: https://review.coreboot.org/c/coreboot/+/81050/comment/8aee2957_ca1c8ab2 : PS4, Line 92: BOARD_GOOGLE_BROX It should be BOARD_GOOGLE_BASEBOARD_BROX https://review.coreboot.org/c/coreboot/+/81050/comment/2a6c5b73_d16e3267 : PS4, Line 120: BOARD_GOOGLE_BASEBOARD_BROX It should be BOARD_GOOGLE_BROX || BOARD_GOOGLE_BROX_EC_ISH -- To view, visit https://review.coreboot.org/c/coreboot/+/81050?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic670d550a9aaad64e52489d895b8aac2aee4b5ed Gerrit-Change-Number: 81050 Gerrit-PatchSet: 4 Gerrit-Owner: Yuval Peress <peress(a)google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Yuval Peress <peress(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Mar 2024 23:57:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/xol: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NO...
by SH Kim (Code Review) 07 Mar '24

07 Mar '24

SH Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81107?usp=email ) Change subject: mb/google/brya/var/xol: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS ...................................................................... mb/google/brya/var/xol: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS BUG=b:326481458 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I85c3c1c7ccaae9d46b66d3e7a2efea6dc9056188 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/81107/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index b85aa5a..ee33267 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -486,6 +486,7 @@ select DRIVERS_I2C_DA7219 select DRIVERS_INTEL_ISH select SOC_INTEL_RAPTORLAKE + select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS config BOARD_GOOGLE_YAVIKS select BOARD_GOOGLE_BASEBOARD_NISSA -- To view, visit https://review.coreboot.org/c/coreboot/+/81107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85c3c1c7ccaae9d46b66d3e7a2efea6dc9056188 Gerrit-Change-Number: 81107 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/brya/var/xol: Disable unused controllers
by SH Kim (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81105?usp=email ) Change subject: mb/google/brya/var/xol: Disable unused controllers ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81105/comment/dff0725c_1822f6be : PS1, Line 14: - PCIE RP8 : - PCIE RP9 > remember to disable those using softstrap as well. Does softstrap mean mfit config? There is no option to disable PCIE RP in mfit config and we verified the PCIE RPs are disabled properly with only this CL as described in the bug. -- To view, visit https://review.coreboot.org/c/coreboot/+/81105?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1be7caf8234c32406aa2cff8fc7fe9fa39b16d89 Gerrit-Change-Number: 81105 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Mar 2024 23:16:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/spi: Add GD25LR256E support
by Martin L Roth (Code Review) 07 Mar '24

07 Mar '24

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81125?usp=email ) Change subject: drivers/spi: Add GD25LR256E support ...................................................................... drivers/spi: Add GD25LR256E support Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Id405ed990101a1ceda5e09c6db835f8302047f5c --- M src/drivers/spi/gigadevice.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/81125/1 diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 94b85e7..16ba27f 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -117,6 +117,13 @@ .fast_read_dual_output_support = 1, .fast_read_dual_io_support = 1, }, + { + /* GD25LR256E */ + .id[0] = 0x6719, + .nr_sectors_shift = 13, + .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, + }, }; const struct spi_flash_vendor_info spi_flash_gigadevice_vi = { -- To view, visit https://review.coreboot.org/c/coreboot/+/81125?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id405ed990101a1ceda5e09c6db835f8302047f5c Gerrit-Change-Number: 81125 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: arch/riscv: Remove typedefs
by Felix Singer (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Martin L Roth, Maximilian Brune, Philipp Hug, ron minnich. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81124?usp=email ) Change subject: arch/riscv: Remove typedefs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id51eda53b6b53ed2cc66c0339c03c855c12c1bd8 Gerrit-Change-Number: 81124 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Mar 2024 22:59:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/riscv: Remove typedefs
by Maximilian Brune (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Felix Singer, Martin L Roth, Philipp Hug, ron minnich. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81124?usp=email ) Change subject: arch/riscv: Remove typedefs ...................................................................... Patch Set 2: (1 comment) File src/arch/riscv/include/mcall.h: https://review.coreboot.org/c/coreboot/+/81124/comment/8726a530_05ba9a87 : PS1, Line 64: #define OTHER_HLS(id) ((struct hls*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id))) > > `"(foo*)" should be "(foo *)"` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id51eda53b6b53ed2cc66c0339c03c855c12c1bd8 Gerrit-Change-Number: 81124 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Mar 2024 22:56:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/riscv: Remove typedefs
by Maximilian Brune (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Felix Singer, Martin L Roth, Maximilian Brune, Philipp Hug, ron minnich. Hello Felix Singer, Martin L Roth, Philipp Hug, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81124?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Felix Singer, Verified+1 by build bot (Jenkins) Change subject: arch/riscv: Remove typedefs ...................................................................... arch/riscv: Remove typedefs typedefs violate our coding-style Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Id51eda53b6b53ed2cc66c0339c03c855c12c1bd8 --- M src/arch/riscv/include/arch/exception.h M src/arch/riscv/include/mcall.h M src/arch/riscv/include/sbi.h M src/arch/riscv/misaligned.c M src/arch/riscv/pmp.c M src/arch/riscv/ramdetect.c M src/arch/riscv/sbi.c M src/arch/riscv/trap_handler.c 8 files changed, 36 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/81124/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id51eda53b6b53ed2cc66c0339c03c855c12c1bd8 Gerrit-Change-Number: 81124 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: arch/riscv: Remove typedefs
by Felix Singer (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Martin L Roth, Maximilian Brune, Philipp Hug, ron minnich. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81124?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: arch/riscv: Remove typedefs ...................................................................... Patch Set 1: (1 comment) File src/arch/riscv/include/mcall.h: https://review.coreboot.org/c/coreboot/+/81124/comment/487b3a27_dd40582f : PS1, Line 64: #define OTHER_HLS(id) ((struct hls*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id))) > `"(foo*)" should be "(foo *)"` While on it, please fix these spacing issues. -- To view, visit https://review.coreboot.org/c/coreboot/+/81124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id51eda53b6b53ed2cc66c0339c03c855c12c1bd8 Gerrit-Change-Number: 81124 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Mar 2024 22:21:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/riscv: Remove typedefs
by Felix Singer (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Martin L Roth, Maximilian Brune, Philipp Hug, ron minnich. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81124?usp=email ) Change subject: arch/riscv: Remove typedefs ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: nice -- To view, visit https://review.coreboot.org/c/coreboot/+/81124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id51eda53b6b53ed2cc66c0339c03c855c12c1bd8 Gerrit-Change-Number: 81124 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Mar 2024 22:03:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/riscv: Remove typedefs
by Maximilian Brune (Code Review) 07 Mar '24

07 Mar '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81124?usp=email ) Change subject: arch/riscv: Remove typedefs ...................................................................... arch/riscv: Remove typedefs typedefs violate our coding-style Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Id51eda53b6b53ed2cc66c0339c03c855c12c1bd8 --- M src/arch/riscv/include/arch/exception.h M src/arch/riscv/include/mcall.h M src/arch/riscv/include/sbi.h M src/arch/riscv/misaligned.c M src/arch/riscv/pmp.c M src/arch/riscv/ramdetect.c M src/arch/riscv/sbi.c M src/arch/riscv/trap_handler.c 8 files changed, 36 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/81124/1 diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h index 9339437..e807a3f 100644 --- a/src/arch/riscv/include/arch/exception.h +++ b/src/arch/riscv/include/arch/exception.h @@ -5,29 +5,29 @@ #include <stdint.h> -typedef struct { +struct trapframe { uintptr_t gpr[32]; uintptr_t status; uintptr_t epc; uintptr_t badvaddr; uintptr_t cause; uintptr_t insn; -} trapframe; +}; typedef uint32_t insn_t; -typedef struct { +struct insn_fetch { uintptr_t error; insn_t insn; -} insn_fetch_t; +}; static inline void exception_init(void) { } void redirect_trap(void); -void default_trap_handler(trapframe *tf); -void handle_supervisor_call(trapframe *tf); -void handle_misaligned(trapframe *tf); +void default_trap_handler(struct trapframe *tf); +void handle_supervisor_call(struct trapframe *tf); +void handle_misaligned(struct trapframe *tf); #endif diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index b0b4bc7..70dc7c6 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -3,7 +3,7 @@ #ifndef _MCALL_H #define _MCALL_H -// NOTE: this is the size of hls_t below. A static_assert would be +// NOTE: this is the size of struct hls below. A static_assert would be // nice to have. #if __riscv_xlen == 64 #define HLS_SIZE 88 @@ -22,12 +22,12 @@ #include <arch/smp/atomic.h> #include <stdint.h> -typedef struct { +struct sbi_device_message { unsigned long dev; unsigned long cmd; unsigned long data; unsigned long sbi_private_data; -} sbi_device_message; +}; struct blocker { void *arg; @@ -36,11 +36,11 @@ atomic_t sync_b; }; -typedef struct { - sbi_device_message *device_request_queue_head; +struct hls { + struct sbi_device_message *device_request_queue_head; unsigned long device_request_queue_size; - sbi_device_message *device_response_queue_head; - sbi_device_message *device_response_queue_tail; + struct sbi_device_message *device_response_queue_head; + struct sbi_device_message *device_response_queue_tail; int hart_id; int ipi_pending; @@ -48,11 +48,11 @@ uint64_t *time; void *fdt; struct blocker entry; -} hls_t; +}; _Static_assert( - sizeof(hls_t) == HLS_SIZE, - "HLS_SIZE must equal to sizeof(hls_t)"); + sizeof(struct hls) == HLS_SIZE, + "HLS_SIZE must equal to sizeof(struct hls)"); register uintptr_t current_stack_pointer asm("sp"); @@ -60,8 +60,8 @@ (void *)((current_stack_pointer + RISCV_PGSIZE) & -RISCV_PGSIZE); }) // hart-local storage, at top of stack -#define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE)) -#define OTHER_HLS(id) ((hls_t*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id))) +#define HLS() ((struct hls*)(MACHINE_STACK_TOP() - HLS_SIZE)) +#define OTHER_HLS(id) ((struct hls*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id))) #define MACHINE_STACK_SIZE RISCV_PGSIZE diff --git a/src/arch/riscv/include/sbi.h b/src/arch/riscv/include/sbi.h index 04b0ac7..8c526fc 100644 --- a/src/arch/riscv/include/sbi.h +++ b/src/arch/riscv/include/sbi.h @@ -21,6 +21,6 @@ #define IPI_SFENCE_VMA_ASID 8 #define IPI_SHUTDOWN 16 -void handle_sbi(trapframe *tf); +void handle_sbi(struct trapframe *tf); #endif /* RISCV_SBI_H */ diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c index 9f144b8..151ed99 100644 --- a/src/arch/riscv/misaligned.c +++ b/src/arch/riscv/misaligned.c @@ -156,7 +156,7 @@ return CB_ERR; } -void handle_misaligned(trapframe *tf) +void handle_misaligned(struct trapframe *tf) { uintptr_t insn = 0; union endian_buf buff; diff --git a/src/arch/riscv/pmp.c b/src/arch/riscv/pmp.c index ee39ac4..85af408 100644 --- a/src/arch/riscv/pmp.c +++ b/src/arch/riscv/pmp.c @@ -12,7 +12,7 @@ * This structure is used to temporarily record PMP * configuration information. */ -typedef struct { +struct pmpcfg { /* used to record the value of pmpcfg[i] */ uintptr_t cfg; /* @@ -23,7 +23,7 @@ uintptr_t previous_address; /* used to record the value of pmpaddr[i] */ uintptr_t address; -} pmpcfg_t; +}; /* This variable is used to record which entries have been used. */ static uintptr_t pmp_entry_used_mask; @@ -207,10 +207,10 @@ } /* Generate a PMP configuration of type NA4/NAPOT */ -static pmpcfg_t generate_pmp_napot( +static struct pmpcfg generate_pmp_napot( uintptr_t base, uintptr_t size, uintptr_t flags) { - pmpcfg_t p; + struct pmpcfg p; flags = flags & (PMP_R | PMP_W | PMP_X | PMP_L); p.cfg = flags | (size > GRANULE ? PMP_NAPOT : PMP_NA4); p.previous_address = 0; @@ -219,10 +219,10 @@ } /* Generate a PMP configuration of type TOR */ -static pmpcfg_t generate_pmp_range( +static struct pmpcfg generate_pmp_range( uintptr_t base, uintptr_t size, uintptr_t flags) { - pmpcfg_t p; + struct pmpcfg p; flags = flags & (PMP_R | PMP_W | PMP_X | PMP_L); p.cfg = flags | PMP_TOR; p.previous_address = base >> PMP_SHIFT; @@ -231,7 +231,7 @@ } /* Generate a PMP configuration */ -static pmpcfg_t generate_pmp(uintptr_t base, uintptr_t size, uintptr_t flags) +static struct pmpcfg generate_pmp(uintptr_t base, uintptr_t size, uintptr_t flags) { if (IS_POWER_OF_2(size) && (size >= 4) && ((base & (size - 1)) == 0)) return generate_pmp_napot(base, size, flags); @@ -289,7 +289,7 @@ /* set up PMP record */ void setup_pmp(uintptr_t base, uintptr_t size, uintptr_t flags) { - pmpcfg_t p; + struct pmpcfg p; int is_range, n; p = generate_pmp(base, size, flags); diff --git a/src/arch/riscv/ramdetect.c b/src/arch/riscv/ramdetect.c index 3382435..048d396 100644 --- a/src/arch/riscv/ramdetect.c +++ b/src/arch/riscv/ramdetect.c @@ -13,7 +13,7 @@ ABORT_CHECKER_TRIGGERED, } abort_state = ABORT_CHECKER_NOT_TRIGGERED; -extern void (*trap_handler)(trapframe *tf); +extern void (*trap_handler)(struct trapframe *tf); static int get_instruction_len(uintptr_t addr) { @@ -31,7 +31,7 @@ die("Not a 16bit or 32bit instruction 0x%x\n", ins); } -static void ramcheck_trap_handler(trapframe *tf) +static void ramcheck_trap_handler(struct trapframe *tf) { abort_state = ABORT_CHECKER_TRIGGERED; diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c index 415ea94..8bf21b7 100644 --- a/src/arch/riscv/sbi.c +++ b/src/arch/riscv/sbi.c @@ -55,7 +55,7 @@ * function : register a7 * return : register a0 */ -void handle_sbi(trapframe *tf) +void handle_sbi(struct trapframe *tf) { uintptr_t ret = 0; uintptr_t arg0 = tf->gpr[10]; diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 4cbccc5..f3968bb 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -46,7 +46,7 @@ return "unknown"; } -static void print_trap_information(const trapframe *tf) +static void print_trap_information(const struct trapframe *tf) { const char *previous_mode; bool mprv = !!(tf->status & MSTATUS_MPRV); @@ -69,7 +69,7 @@ printk(BIOS_DEBUG, "Stored sp: %p\n", (void *)tf->gpr[2]); } -static void interrupt_handler(trapframe *tf) +static void interrupt_handler(struct trapframe *tf) { uint64_t cause = tf->cause & ~0x8000000000000000ULL; @@ -109,9 +109,9 @@ } } -void (*trap_handler)(trapframe *tf) = default_trap_handler; +void (*trap_handler)(struct trapframe *tf) = default_trap_handler; -void default_trap_handler(trapframe *tf) +void default_trap_handler(struct trapframe *tf) { if (tf->cause & 0x8000000000000000ULL) { interrupt_handler(tf); -- To view, visit https://review.coreboot.org/c/coreboot/+/81124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id51eda53b6b53ed2cc66c0339c03c855c12c1bd8 Gerrit-Change-Number: 81124 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2024