coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Rewrite acpi_create_drhd
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81048?usp=email ) Change subject: soc/intel/xeon_sp: Rewrite acpi_create_drhd ...................................................................... Patch Set 6: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/81048?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idcfa899c764ffe51db5ed202ead07ad7b6868864 Gerrit-Change-Number: 81048 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 04:20:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add utils to find stack from device or domain
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81109?usp=email ) Change subject: soc/intel/xeon_sp: Add utils to find stack from device or domain ...................................................................... soc/intel/xeon_sp: Add utils to find stack from device or domain TEST=intel/archercity CRB Change-Id: Id0bf83975e66937a3860378074749dbecbef4eb9 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h 2 files changed, 26 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/81109/1 diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index f061b87..fbeedf1 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -11,19 +11,37 @@ #include <soc/util.h> #include <stdlib.h> -static const STACK_RES *domain_to_stack_res(const struct device *dev) +const STACK_RES *domain_to_stack_res(struct device *dev) { - assert(dev->path.type == DEVICE_PATH_DOMAIN); + if ((!dev) && (dev->path.type != DEVICE_PATH_DOMAIN)) + return NULL; + + const IIO_UDS *hob = get_iio_uds(); + if (hob == NULL) + return NULL; + const union xeon_domain_path dn = { .domain_path = dev->path.domain.domain }; - - const IIO_UDS *hob = get_iio_uds(); - assert(hob != NULL); - return &hob->PlatformData.IIO_resource[dn.socket].StackRes[dn.stack]; } +const STACK_RES *device_to_stack_res(struct device *dev) +{ + if (!dev) + return NULL; + + struct device *domain; + if (dev->path.type == DEVICE_PATH_DOMAIN) + domain = dev; + else + domain = dev_get_pci_domain(dev); + if (!domain) + return NULL; + + return domain_to_stack_res(domain); +} + /** * Find all device of a given vendor and type for the specified socket. * The function iterates over all PCI domains of the specified socket diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index d61f23a..faf9717 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -58,6 +58,8 @@ struct device *dev_find_device_on_socket(uint8_t socket, u16 vendor, u16 device); struct device *dev_find_all_devices_on_socket(uint8_t socket, u16 vendor, u16 device, struct device *from); struct device *dev_find_all_devices_on_stack(uint8_t socket, uint8_t stack, u16 vendor, u16 device, struct device *from); +const STACK_RES *domain_to_stack_res(struct device *dev); +const STACK_RES *device_to_stack_res(struct device *dev); int iio_pci_domain_socket_from_dev(struct device *dev); int iio_pci_domain_stack_from_dev(struct device *dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/81109?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0bf83975e66937a3860378074749dbecbef4eb9 Gerrit-Change-Number: 81109 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: device: Add dev_find_device_filter
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81108?usp=email ) Change subject: device: Add dev_find_device_filter ...................................................................... device: Add dev_find_device_filter The new utils allows to find devices based on a filter function. TEST=intel/archercity CRB Change-Id: Id657830e557389bb776a929ac049af2b9545027d Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/device/device_util.c M src/include/device/device.h 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/81108/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index b5d0d98..f5d7934 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -55,6 +55,28 @@ } /** + * Find a device by a filter function + * + * @param filter Pointer to a filter function. + * @param from Pointer to the device structure, used as a starting point in + * the linked list of all_devices, which can be 0 to start at the + * head of the list (i.e. all_devices). + * @return Pointer to the device struct. + */ +struct device *dev_find_device_filter(dev_filter_t filter, struct device *from) +{ + if (!from) + from = all_devices; + else + from = from->next; + + while (from && (!filter(from))) + from = from->next; + + return from; +} + +/** * Find a device of a given class. * * @param class Class of the device. diff --git a/src/include/device/device.h b/src/include/device/device.h index 25f730b..35f648f 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -210,6 +210,8 @@ size_t nested_path_length); struct device *alloc_find_dev(struct bus *parent, struct device_path *path); struct device *dev_find_device(u16 vendor, u16 device, struct device *from); +typedef int (*dev_filter_t)(struct device *dev); +struct device *dev_find_device_filter(dev_filter_t filter, struct device *from); struct device *dev_find_class(unsigned int class, struct device *from); DEVTREE_CONST struct device *dev_find_path( DEVTREE_CONST struct device *prev_match, -- To view, visit https://review.coreboot.org/c/coreboot/+/81108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id657830e557389bb776a929ac049af2b9545027d Gerrit-Change-Number: 81108 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Rewrite acpi_create_satc
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81049?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Code-Review+2 by Patrick Rudolph, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Rewrite acpi_create_satc ...................................................................... soc/intel/xeon_sp: Rewrite acpi_create_satc SATC is for RCiEPs (Root Complex Integrated EndPoints) but not limited to IOAT domains. Rewrite the func by iterating all domains and its RCiEPs. Currently the codes only support 1 PCIe segment. TEST=intel/archercity CRB coreboot SATC generation logs are unchanged before and after. Change-Id: I1dfc56ccf279b77cfab4ae3457aa8799d2d57a34 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/uncore_acpi.c 1 file changed, 16 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/81049/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/81049?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1dfc56ccf279b77cfab4ae3457aa8799d2d57a34 Gerrit-Change-Number: 81049 Gerrit-PatchSet: 10 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: util/docker: Update Dockerfiles for building documentation
by Nicholas Chin (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Felix Singer, Martin L Roth. Hello Felix Singer, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80312?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/docker: Update Dockerfiles for building documentation ...................................................................... util/docker: Update Dockerfiles for building documentation Update all pip packages related to coreboot's documentation to their latest available version, and update the doc.coreboot.org base image to Alpine 3.19.1. Add myst-parser in preparation to switch from Recommonmark to MyST Parser. TEST: The documentation builds and renders properly when built using the updated container. Change-Id: I8df4aadabc49c0201a836333745fe138184595ac Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/docker/coreboot-jenkins-node/Dockerfile M util/docker/doc.coreboot.org/Dockerfile 2 files changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/80312/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/80312?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8df4aadabc49c0201a836333745fe138184595ac Gerrit-Change-Number: 80312 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/brya/var/xol: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NO...
by Eric Lai (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, SH Kim, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81107?usp=email ) Change subject: mb/google/brya/var/xol: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85c3c1c7ccaae9d46b66d3e7a2efea6dc9056188 Gerrit-Change-Number: 81107 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Mar 2024 02:29:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: payload/external/edk2: Explicitly define the build arch
by Nicholas Sudsgaard (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Benjamin Doron, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Sean Rhodes. Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80883?usp=email ) Change subject: payload/external/edk2: Explicitly define the build arch ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Seems they broke it for RISC: […] I'm not very familiar with the RISCV side of things, but it seems like coreboot has support (sifive mainboards and qemu). -- To view, visit https://review.coreboot.org/c/coreboot/+/80883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5 Gerrit-Change-Number: 80883 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 00:06:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/riscv: use PMP
by ron minnich (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81090?usp=email to look at the new patch set (#16). Change subject: arch/riscv: use PMP ...................................................................... arch/riscv: use PMP With this change, a simple S-mode payload works: 1: li a7, 1 li a0, 48 ecall j 1b Without this change, it will not work. Linux also boots with this on the command line: clk_ignore_unused Resolving that problem will require a separate patch. Getting this to build on RV32 required changes to the API, as it was incorrect. In RV32, PMP entries are 34 bits. Hence, the setup_pmp needed to accept u64. So, uinptr_t can not be used, as on 32 bits they are only 32 bit numbers. The internal API uses uintptr_t, but the exported API uses u64, so external code does not have to think about right shifts on base and size. Errors are detected: an error in base and size will result in a BIOS_EMERG print, but not a panic. Boots not bricks if possible. There are small changes to the internal API to reduce stack pressure: there's no need to have two pmpcfg_t on the stack when one will do. PMPs are just packed with all kinds of special cases. There are no requirements that you read back what you wrote to the PMPaddr registers. An SoC can just decide it only does 4096-byte granularity, and that is your problem if you wanted finer granulatiry. SoC's don't have to implement all the high order bits either. Finally, since it's a memory address range, the SoC need only implement enough bits for the memory bus, not the address space of the chip! PMPs are best used sparingly. Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/include/arch/pmp.h M src/arch/riscv/payload.c M src/arch/riscv/pmp.c 3 files changed, 130 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/81090/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/81090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Gerrit-Change-Number: 81090 Gerrit-PatchSet: 16 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: arch/riscv: use PMP
by ron minnich (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81090?usp=email to look at the new patch set (#15). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/riscv: use PMP ...................................................................... arch/riscv: use PMP With this change, a simple S-mode payload works: 1: li a7, 1 li a0, 48 ecall j 1b Without this change, it will not work. Linux also boots with this on the command line: clk_ignore_unused Resolving that problem will require a separate patch. Getting this to build on RV32 required changes to the API, as it was incorrect. In RV32, PMP entries are 34 bits. Hence, the setup_pmp needed to accept u64. So, uinptr_t can not be used, as on 32 bits they are only 32 bit numbers. The internal API uses uintptr_t, but the exported API uses u64, so external code does not have to think about right shifts on base and size. Errors are detected: an error in base and size will result in a BIOS_EMERG print, but not a panic. Boots not bricks if possible. There are small changes to the internal API to reduce stack pressure: there's no need to have two pmpcfg_t on the stack when one will do. PMPs are just packed with all kinds of special cases. Also, there are no requirements that you read back what you wrote to the PMPaddr registers. An SoC can just decided it only does 4096-byte granularity, and that is your problem. SoC's don't have to implement all the high order bits either. Finally, since it's a memory address range, the SoC need only implement enough bits for the memory bus, not the address space of the chip! Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/include/arch/pmp.h M src/arch/riscv/payload.c M src/arch/riscv/pmp.c 3 files changed, 130 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/81090/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/81090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Gerrit-Change-Number: 81090 Gerrit-PatchSet: 15 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: drivers/i2c/tas5825m: Allow using I2C bus
by Tim Crawford (Code Review) 07 Mar '24

07 Mar '24

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81126?usp=email ) Change subject: drivers/i2c/tas5825m: Allow using I2C bus ...................................................................... drivers/i2c/tas5825m: Allow using I2C bus The latest Clevo boards connect the TAS5825M to one of the I2C connections instead of the SMBus connection. The I2C ops are compatible with SMBus, so always use them. Tested on system76/oryp6 (uses SMBus) and in-development system76/oryp12 (uses I2C3). TAS5825M init is successful and speaker output works. Change-Id: I2233d6977fd460b53e27260cdfabe42e30b98041 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/drivers/i2c/tas5825m/tas5825m.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/81126/1 diff --git a/src/drivers/i2c/tas5825m/tas5825m.c b/src/drivers/i2c/tas5825m/tas5825m.c index 9f14059..ead1b16 100644 --- a/src/drivers/i2c/tas5825m/tas5825m.c +++ b/src/drivers/i2c/tas5825m/tas5825m.c @@ -1,23 +1,24 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <device/smbus.h> -#include <device/pci.h> +#include <device/i2c_bus.h> #include "chip.h" #include "tas5825m.h" int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value) { - return smbus_write_byte(dev, addr, value); + return i2c_dev_writeb_at(dev, addr, value); } -//TODO: use I2C block write for better performance int tas5825m_write_block_at(struct device *dev, uint8_t addr, const uint8_t *values, uint8_t length) { + // TODO: use I2C block write for better performance; SMBus does not + // have `transfer` op for it. + int res = 0; for (uint8_t i = 0; i < length; i++) { - res = smbus_write_byte(dev, addr + i, values[i]); + res = i2c_dev_writeb_at(dev, addr + i, values[i]); if (res < 0) return res; } @@ -45,8 +46,7 @@ static void tas5825m_init(struct device *dev) { - if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && - ops_smbus_bus(get_pbus_smbus(dev))) { + if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && i2c_link(dev)) { printk(BIOS_DEBUG, "tas5825m at %s\n", dev_path(dev)); struct drivers_i2c_tas5825m_config *config = dev->chip_info; -- To view, visit https://review.coreboot.org/c/coreboot/+/81126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2233d6977fd460b53e27260cdfabe42e30b98041 Gerrit-Change-Number: 81126 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-MessageType: newchange

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