coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Rewrite acpi_create_satc
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81049?usp=email ) Change subject: soc/intel/xeon_sp: Rewrite acpi_create_satc ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81049/comment/b88b5894_19598451 : PS9, Line 9: RCiEPs > Please mention once what this means. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81049?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1dfc56ccf279b77cfab4ae3457aa8799d2d57a34 Gerrit-Change-Number: 81049 Gerrit-PatchSet: 11 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 06:22:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Create CXL domains
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81099?usp=email ) Change subject: soc/intel/xeon_sp: Create CXL domains ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/81099/comment/c5587b0f_33b0ab3d : PS4, Line 274: BusBase > Will add some comments in codes. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80 Gerrit-Change-Number: 81099 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 06:22:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Create CXL domains
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81099?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Create CXL domains ...................................................................... soc/intel/xeon_sp: Create CXL domains TEST=intel/archercity CRB P.S. The SUT is not with CXL cards however we hope this refactor could be integrated first as an improvement of the design. Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/spr/include/soc/soc_util.h 4 files changed, 99 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/81099/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/81099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80 Gerrit-Change-Number: 81099 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Create CXL domains
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81099?usp=email ) Change subject: soc/intel/xeon_sp: Create CXL domains ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/81099/comment/e9188662_649a4969 : PS4, Line 274: BusBase > Both bridges are all enumerable bridges by generic PCI codes. […] Will add some comments in codes. -- To view, visit https://review.coreboot.org/c/coreboot/+/81099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80 Gerrit-Change-Number: 81099 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 06:16:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Create CXL domains
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81099?usp=email ) Change subject: soc/intel/xeon_sp: Create CXL domains ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/81099/comment/13fd4df1_6abdc0a5 : PS4, Line 274: BusBase > > From what I understand looking that the Intel reference code the PCI domain always covers all buss […] Both bridges are all enumerable bridges by generic PCI codes. The PCI bridge only contains RCiEP. The CXL bridge only contains CXL 1.0 end-points. -- To view, visit https://review.coreboot.org/c/coreboot/+/81099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80 Gerrit-Change-Number: 81099 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 06:11:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81098?usp=email ) Change subject: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: can we move ahead for merge this one? -- To view, visit https://review.coreboot.org/c/coreboot/+/81098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Gerrit-Change-Number: 81098 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 05:36:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/alderlake: select UDK_202111_BINDING for ADL-N
by Ronak Kanabar (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Paul Menzel, V Sowmya. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80274?usp=email ) Change subject: soc/intel/alderlake: select UDK_202111_BINDING for ADL-N ...................................................................... Patch Set 7: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80274/comment/d3d05b57_e542699b : PS6, Line 10: This patch select edk2-stable202111 for ADL-N and add CFLAGS > This patch select*s* … and add*s* […] Done https://review.coreboot.org/c/coreboot/+/80274/comment/4e94fc03_95efb26e : PS6, Line 11: pltform > platform Done https://review.coreboot.org/c/coreboot/+/80274/comment/20b814fa_e9395b88 : PS6, Line 11: while > during Done https://review.coreboot.org/c/coreboot/+/80274/comment/2727d923_e3ce8ab8 : PS6, Line 11: > One space. Done https://review.coreboot.org/c/coreboot/+/80274/comment/5a2992cb_a158f14e : PS6, Line 12: compilation. > Please paste the compiler error. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If277ede4307515035389cd0e9d34c15cc80f278c Gerrit-Change-Number: 80274 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Mar 2024 05:33:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/alderlake: select UDK_202111_BINDING for ADL-N
by Ronak Kanabar (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, V Sowmya. Hello Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik, V Sowmya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80274?usp=email to look at the new patch set (#7). Change subject: soc/intel/alderlake: select UDK_202111_BINDING for ADL-N ...................................................................... soc/intel/alderlake: select UDK_202111_BINDING for ADL-N ADL-N FSP uses 202111 Edk2. select UDK_202111_BINDING Kconfig for ADL-N SoC. This patch selects edk2-stable202111 for ADL-N and adds CFLAGS -fshort-wchar for platform using 202111 Edk2 to fix STATIC_ASSERT during compilation. Compilation error: src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h:807:25: error: static assertion failed: "sizeof (L\'A\') does not meet UEFI Specification Data Type requirements" src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h:807:25: error: static assertion failed: "sizeof (L\"A\") does not meet UEFI Specification Data Type requirements" BUG=b:296433836 TEST=Able to build google/crassk. Change-Id: If277ede4307515035389cd0e9d34c15cc80f278c Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.mk 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/80274/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/80274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If277ede4307515035389cd0e9d34c15cc80f278c Gerrit-Change-Number: 80274 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/brya/var/xol: Disable unused controllers
by SH Kim (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81105?usp=email ) Change subject: mb/google/brya/var/xol: Disable unused controllers ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81105/comment/68a29142_ba560fea : PS1, Line 14: - PCIE RP8 : - PCIE RP9 > > > Does softstrap mean mfit config? […] Yeah, I understand your remark, it must be a more powerful way to disable PCIe RP. RP8 is under PCIe 5-8 group and PR9 is under PCIe 9-12. Currently PCIe 5-8 is set as 4x1 and PCIe 9-12 is set as 1x4. It's following baseboard config. I'd like to keep current softstrap for future. I believe the runtime job to disable PCIe RPs in coreboot/FSP is not a big deal. Now we are under proto stage, there is a posibility to support another device through PCIe port in future. Then we only need coreboot change for it. -- To view, visit https://review.coreboot.org/c/coreboot/+/81105?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1be7caf8234c32406aa2cff8fc7fe9fa39b16d89 Gerrit-Change-Number: 81105 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Mar 2024 05:22:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: device: Add dev_find_device_filter
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81108?usp=email ) Change subject: device: Add dev_find_device_filter ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I move this patch out from my dependency chain due to compatibility issue, however, I personally think the usage model of this patch might be worthwhile for a discussion. The ideal model could be, struct device *dev_find_all_devices_on_stack(uint8_t socket, uint8_t stack, u16 vendor, u16 device, struct device *from) { int filter_device_on_stack(struct device *dev) { struct device *domain = dev_get_pci_domain(dev); if (!domain) return 0; union xeon_domain_path dn; dn.domain_path = domain->path.domain.domain; if (socket != XEONSP_SOCKET_MAX && dn.socket != socket) return 0; if (stack != XEONSP_STACK_MAX && dn.stack != stack) return 0; if (vendor != XEONSP_VENDOR_MAX && dev->vendor != vendor) return 0; if (device != XEONSP_DEVICE_MAX && dev->device != device) return 0; return 1; }; return dev_find_device_filter(filter_device_on_stack, from); } This is allowed by my C99 compiler for intel/archercity, but not fit for all platform configurations. Not sure if this still has values to be adopted in some cases. -- To view, visit https://review.coreboot.org/c/coreboot/+/81108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id657830e557389bb776a929ac049af2b9545027d Gerrit-Change-Number: 81108 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 05:22:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2024