coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: soc/intel/mtl: Add debug message for get_max_tcss_port()
by Tyler Wang (Code Review) 08 Mar '24

08 Mar '24

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81111?usp=email ) Change subject: soc/intel/mtl: Add debug message for get_max_tcss_port() ...................................................................... soc/intel/mtl: Add debug message for get_max_tcss_port() Modify debug message to make it more complete and less confusing for developers. BUG=none TEST=none Change-Id: I26e882d2d9dcbef84718924aaab3864d89c58f39 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/soc/intel/meteorlake/soc_info.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/81111/1 diff --git a/src/soc/intel/meteorlake/soc_info.c b/src/soc/intel/meteorlake/soc_info.c index b5333bd..0c2e1f8 100644 --- a/src/soc/intel/meteorlake/soc_info.c +++ b/src/soc/intel/meteorlake/soc_info.c @@ -24,7 +24,7 @@ uint8_t get_max_tcss_port(void) { uint8_t tcss_port = MAX_TYPE_C_PORTS; - printk(BIOS_DEBUG, "soc_info: tcss_port:%d\n", tcss_port); + printk(BIOS_DEBUG, "soc_info: max_tcss_port:%d\n", tcss_port); return tcss_port; } -- To view, visit https://review.coreboot.org/c/coreboot/+/81111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I26e882d2d9dcbef84718924aaab3864d89c58f39 Gerrit-Change-Number: 81111 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add device and domain find utils for stacks
by Patrick Rudolph (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81043?usp=email ) Change subject: soc/intel/xeon_sp: Add device and domain find utils for stacks ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/81043/comment/74194c04_33ed4b8b : PS7, Line 99: all_devices It would be nice to have a new generic method dev_find_device_on_domain() that works like dev_find_device() but takes a domain device as additional input. it would only look for device on the specified domain. -- To view, visit https://review.coreboot.org/c/coreboot/+/81043?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I163eacae363334919fd66d571b7e0415e77bd52d Gerrit-Change-Number: 81043 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 08:30:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add domain role checking utils
by Patrick Rudolph (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81046?usp=email ) Change subject: soc/intel/xeon_sp: Add domain role checking utils ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81046?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b31c29564c774c27e86f55749ca9eca057a0cfe Gerrit-Change-Number: 81046 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 08:20:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_add_dram_resources
by Patrick Rudolph (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81110?usp=email ) Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81110/comment/f356100f_dd390713 : PS1, Line 9: SoC This seems to move code around for no apparent reason. Is there a follow up patch to this? https://review.coreboot.org/c/coreboot/+/81110/comment/e6c9a6f2_18195cf2 : PS1, Line 10: acorss across File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/81110/comment/79dfa205_5fb37af6 : PS1, Line 201: uint64_t static uint64_t https://review.coreboot.org/c/coreboot/+/81110/comment/baed4aa1_49485a0a : PS1, Line 304: Ahe The -- To view, visit https://review.coreboot.org/c/coreboot/+/81110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b0bb8e8c51ef20467958826b9fdd5a995e14901 Gerrit-Change-Number: 81110 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 08:19:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/xol: Update psys_pmax value to 122W
by Kapil Porwal (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Nick Vaccaro, SH Kim. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81104?usp=email ) Change subject: mb/google/brya/var/xol: Update psys_pmax value to 122W ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8bc58343d5736e2457db006972dc229e16d3fe59 Gerrit-Change-Number: 81104 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Mar 2024 08:14:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/xol: Configure Acoustic noise mitigation
by Kapil Porwal (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Nick Vaccaro, SH Kim. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81103?usp=email ) Change subject: mb/google/brya/var/xol: Configure Acoustic noise mitigation ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6165ae6ca73d1467a1d2cc7bd545298bd4c2f54f Gerrit-Change-Number: 81103 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Mar 2024 08:13:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_add_dram_resources
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81110?usp=email ) Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources ...................................................................... soc/intel/xeon_sp: Add soc_add_dram_resources SoC specific DRAM resource, e.g. 4GB above memory map, are different acorss SoC generations. TEST=intel/archercity CRB Change-Id: I8b0bb8e8c51ef20467958826b9fdd5a995e14901 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/uncore.c 2 files changed, 45 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/81110/1 diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 729ab58..f4a028f 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -54,6 +54,7 @@ void soc_create_ioat_domains(union xeon_domain_path path, struct bus *bus, const STACK_RES *sr); void soc_create_cxl_domains(const union xeon_domain_path dp, struct bus *bus, const STACK_RES *sr); +int soc_add_dram_resources(struct device *dev, int start_index); struct device *dev_find_device_on_socket(uint8_t socket, u16 vendor, u16 device); struct device *dev_find_all_devices_on_socket(uint8_t socket, u16 vendor, u16 device, struct device *from); diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 952ca4d..4c94d61 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -8,6 +8,7 @@ #include <device/pci_ids.h> #include <drivers/ocp/include/vpd.h> #include <soc/acpi.h> +#include <soc/chip_common.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> @@ -197,10 +198,10 @@ * +--------------------------+ 0 */ +uint64_t mc_values[NUM_MAP_ENTRIES]; static void mc_add_dram_resources(struct device *dev, int *res_count) { const struct resource *res; - uint64_t mc_values[NUM_MAP_ENTRIES]; uint64_t top_of_ram; int index = *res_count; struct range_entry fsp_mem; @@ -266,6 +267,47 @@ mc_values[TOLM_REG]); LOG_RESOURCE("mmio_tolm", dev, res); + /* Add SoC specific resources */ + index += soc_add_dram_resources(dev, index); + + /* add MMIO CFG resource */ + res = mmio_from_to(dev, index++, mc_values[MMCFG_BASE_REG], + mc_values[MMCFG_LIMIT_REG] + 1); + LOG_RESOURCE("mmiocfg_res", dev, res); + + /* add Local APIC resource */ + res = mmio_range(dev, index++, LAPIC_DEFAULT_BASE, 0x00001000); + LOG_RESOURCE("apic_res", dev, res); + + /* + * Add legacy region as reserved - 0xa000 - 1MB + * Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xfffff: RAM + */ + res = mmio_range(dev, index++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + LOG_RESOURCE("legacy_mmio", dev, res); + + res = reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); + LOG_RESOURCE("legacy_write_protect", dev, res); + + *res_count = index; +} + +/* + * Add SoC specific DRAM resources + * + * @param dev Pointer of the device to add resource on. + * @param start_index The start index for the SoC specific resources. + * + * @return Ahe added resource counts. + */ +int soc_add_dram_resources(struct device *dev, int start_index) +{ + const struct resource *res; + int index = start_index; + if (CONFIG(SOC_INTEL_HAS_CXL)) { /* 4GiB -> CXL Memory */ uint32_t gi_mem_size; @@ -310,29 +352,7 @@ LOG_RESOURCE("high_ram", dev, res); } - /* add MMIO CFG resource */ - res = mmio_from_to(dev, index++, mc_values[MMCFG_BASE_REG], - mc_values[MMCFG_LIMIT_REG] + 1); - LOG_RESOURCE("mmiocfg_res", dev, res); - - /* add Local APIC resource */ - res = mmio_range(dev, index++, LAPIC_DEFAULT_BASE, 0x00001000); - LOG_RESOURCE("apic_res", dev, res); - - /* - * Add legacy region as reserved - 0xa000 - 1MB - * Reserve everything between A segment and 1MB: - * - * 0xa0000 - 0xbffff: legacy VGA - * 0xc0000 - 0xfffff: RAM - */ - res = mmio_range(dev, index++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - LOG_RESOURCE("legacy_mmio", dev, res); - - res = reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); - LOG_RESOURCE("legacy_write_protect", dev, res); - - *res_count = index; + return index - start_index; } static void mmapvtd_read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/81110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b0bb8e8c51ef20467958826b9fdd5a995e14901 Gerrit-Change-Number: 81110 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add device and domain find utils for stacks
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81043?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+2 by Arthur Heymans, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/xeon_sp: Add device and domain find utils for stacks ...................................................................... soc/intel/xeon_sp: Add device and domain find utils for stacks TEST=intel/archercity CRB Change-Id: I163eacae363334919fd66d571b7e0415e77bd52d Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h 2 files changed, 76 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/81043/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/81043?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I163eacae363334919fd66d571b7e0415e77bd52d Gerrit-Change-Number: 81043 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81098?usp=email to look at the new patch set (#6). Change subject: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP ...................................................................... soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP With this patch, all domain creation logics are moved into the scope of attach_iio_stack/chip_common.c for the ease of maintenance and future SoC integration where the domain creation process for specific stack types might be overridden. TEST=intel/archercity CRB 1. Boot to CentOS 9 Stream Cloud. 2. Compare PCIe enumeration and ACPI table generation logs before and and after this patch, no changes. Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/ioat.c M src/soc/intel/xeon_sp/uncore_acpi.c 7 files changed, 62 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/81098/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/81098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Gerrit-Change-Number: 81098 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81098?usp=email ) Change subject: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > Yeah, this issue is handled. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/81098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Gerrit-Change-Number: 81098 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 08:08:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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coreboot-gerrit March 2024