coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

1 participants
3668 discussions

[XS] Change in coreboot[main]: soc/intel/mtl: Modify debug message for get_max_tcss_port()
by Subrata Banik (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Ravishankar Sarawadi, Tarun, Tyler Wang. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81111?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/mtl: Modify debug message for get_max_tcss_port() ...................................................................... Patch Set 5: (1 comment)… [View More]

1 0

[XS] Change in coreboot[main]: soc/intel/mtl: Modify debug message for get_max_tcss_port()
by Kapil Porwal (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Ravishankar Sarawadi, Subrata Banik, Tarun, Tyler Wang. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81111?usp=email ) Change subject: soc/intel/mtl: Modify debug message for get_max_tcss_port() ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/… [View More]

1 0

[XS] Change in coreboot[main]: soc/intel/mtl: Modify debug message for get_max_tcss_port()
by Tyler Wang (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Ravishankar Sarawadi, Subrata Banik, Tarun. Tyler Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81111?usp=email ) Change subject: soc/intel/mtl: Modify debug message for get_max_tcss_port() ...................................................................... Patch Set 5: This change is ready for review. -- To view, visit https://review.… [View More]

1 0

[S] Change in coreboot[main]: soc/intel/alderlake: Add Raptor Lake System Agent Device IDs
by Angel Pons (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Dinesh Gehlot, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81115?usp=email ) Change subject: soc/intel/alderlake: Add Raptor Lake System Agent Device IDs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81115?usp=email To … [View More]

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Create CXL domains
by Patrick Rudolph (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81099?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/xeon_sp: Create CXL domains ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/xeon_sp/… [View More]chip_common.c: https://review.coreboot.org/c/coreboot/+/81099/comment/50140f13_6501a83f : PS4, Line 274: BusBase > Done This is still not clear to me. Please be specific and use "host bridge" and "PCI bridge" instead of just bridge. From what I understand the PCI host bridge only has RCiEP, thus there are no PCI bridges on that host bridge and thus only 1 bus. From what I understand all CXL 1.0/1.1 devices are also RCiEP. In that case there would be also 1 bus on the CXL domain. By using BusLimit on the CXL domain you could have more buses. Is that for CXL2.0 devices, which could appear as PCI bridges? -- To view, visit https://review.coreboot.org/c/coreboot/+/81099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80 Gerrit-Change-Number: 81099 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 09:20:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment [View Less]

1 0

[S] Change in coreboot[main]: soc/intel/xeon_sp: Rewrite acpi_create_satc
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81049?usp=email ) Change subject: soc/intel/xeon_sp: Rewrite acpi_create_satc ...................................................................... Patch Set 13: (1 comment) Patchset: PS13: should we move ahead to merge this? -- To view, visit https://review.… [View More]

1 0

[XS] Change in coreboot[main]: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80795?usp=email ) Change subject: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80795/comment/… [View More]

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Add device and domain find utils for stacks
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81043?usp=email ) Change subject: soc/intel/xeon_sp: Add device and domain find utils for stacks ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/… [View More]

1 0

[XS] Change in coreboot[main]: arch/x86/include/arch: Add feature check macros
by Arthur Heymans (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Jincheng Li, Jérémy Compostella, Shuo Liu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81133?usp=email ) Change subject: arch/x86/include/arch: Add feature check macros ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81133?usp=email To unsubscribe, or for help writing mail filters, visit https:… [View More]

1 0

[XS] Change in coreboot[main]: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION
by Ronak Kanabar (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Krishna P Bhat D, Nick Vaccaro, Subrata Banik, V Sowmya. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81038?usp=email ) Change subject: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81038/comment/… [View More]

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2024