coreboot-gerrit March 2024

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[S] Change in coreboot[main]: soc/intel/common/mp_init: Fix USE_INTEL_FSP_MP_INIT use-case
by Subrata Banik (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80575?usp=email ) Change subject: soc/intel/common/mp_init: Fix USE_INTEL_FSP_MP_INIT use-case ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80575?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb8cdfef7b4279da2c7dff344c95fe446a605934 Gerrit-Change-Number: 80575 Gerrit-PatchSet: 9 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 08 Mar 2024 17:00:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
by Subrata Banik (Code Review) 08 Mar '24

08 Mar '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80275?usp=email ) Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support ...................................................................... drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support Intel Firmware Support Package 2.4 specification (document 736809) brings some significant changes compared to version 2.3 (document 644852): 1. It supports FSP-M multi-phase init. Some fields have been added to the FSP header data structure for this purpose. 2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively. 3. It support 64-bits FSP but 64-bits support will be provided by subsequent patch. Note that similarly to what is done for silicon initialization, timestamps and post-codes are used during the memory initialization multi-phase. [736809] https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf [644852] https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-… TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80275 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/commonlib/include/commonlib/console/post_codes.h M src/commonlib/include/commonlib/timestamp_serialized.h M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/upd_display.c M util/cbfstool/eventlog.c 10 files changed, 124 insertions(+), 19 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h index c0b15c5..d581bc4 100644 --- a/src/commonlib/include/commonlib/console/post_codes.h +++ b/src/commonlib/include/commonlib/console/post_codes.h @@ -362,6 +362,20 @@ #define POSTCODE_FSP_NOTIFY_AFTER_FINALIZE 0xa3 /** + * \brief Before calling FSP Multiphase MemoryInit + * + * Going to call into FSP binary for Multiple phase MEM Init + */ +#define POSTCODE_FSP_MULTI_PHASE_MEM_INIT_ENTRY 0xa4 + +/** + * \brief After calling FSP Multiphase MemoryInit + * + * FSP binary returned from Multiple phase MEM Init + */ +#define POSTCODE_FSP_MULTI_PHASE_MEM_INIT_EXIT 0xa5 + +/** * \brief Invalid or corrupt ROM * * Set if firmware failed to find or validate a resource that is stored in ROM. diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index e4439cd..0ccb3b9 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -138,6 +138,8 @@ TS_FSP_END_OF_FIRMWARE_END = 961, TS_FSP_MULTI_PHASE_SI_INIT_START = 962, TS_FSP_MULTI_PHASE_SI_INIT_END = 963, + TS_FSP_MULTI_PHASE_MEM_INIT_START = 964, + TS_FSP_MULTI_PHASE_MEM_INIT_END = 965, TS_FSP_MEMORY_INIT_LOAD = 970, TS_FSP_SILICON_INIT_LOAD = 971, @@ -319,6 +321,9 @@ TS_NAME_DEF(TS_FSP_MULTI_PHASE_SI_INIT_START, TS_FSP_MULTI_PHASE_SI_INIT_END, "calling FspMultiPhaseSiInit"), TS_NAME_DEF(TS_FSP_MULTI_PHASE_SI_INIT_END, 0, "returning from FspMultiPhaseSiInit"), + TS_NAME_DEF(TS_FSP_MULTI_PHASE_MEM_INIT_START, TS_FSP_MULTI_PHASE_MEM_INIT_END, + "calling FspMultiPhaseMemInit"), + TS_NAME_DEF(TS_FSP_MULTI_PHASE_MEM_INIT_END, 0, "returning from FspMultiPhaseMemInit"), TS_NAME_DEF(TS_FSP_ENUMERATE_START, TS_FSP_ENUMERATE_END, "calling FspNotify(AfterPciEnumeration)"), TS_NAME_DEF(TS_FSP_ENUMERATE_END, 0, "returning from FspNotify(AfterPciEnumeration)"), diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 274c3e5..754b04a 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -39,6 +39,18 @@ 1. Added ExtendedImageRevision field in FSP_INFO_HEADER 2. Added FSP_NON_VOLATILE_STORAGE_HOB2 +config PLATFORM_USES_FSP2_4 + bool + default n + select PLATFORM_USES_FSP2_3 + help + Include FSP 2.4 wrappers and functionality. + Features added into FSP 2.4 specification that impact coreboot are: + 1. FSP-M multi phase init support + 2. FSPM_ARCH2_UPD and FSPS_ARCH2_UPD data structures must be + used in place of FSPM_ARCH_UPD and FSPS_ARCH_UPD respectively + 3. 64-bits support + if PLATFORM_USES_FSP2_0 config PLATFORM_USES_FSP2_X86_32 diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 40a64e6..971be0d 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -48,6 +48,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); /* Callbacks for SoC/Mainboard specific overrides */ +void platform_fsp_memory_multi_phase_init_cb(uint32_t phase_index); void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index); /* Check if MultiPhase Si Init is enabled */ bool fsp_is_multi_phase_init_enabled(void); diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index fceebec7e..f495822 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -37,6 +37,8 @@ uint32_t fsp_multi_phase_si_init_entry_offset; uint16_t extended_image_revision; uint16_t res4; + uint32_t fsp_multi_phase_mem_init_entry_offset; + uint32_t res5; } __packed; #else #error You need to implement this struct for x86_64 FSP diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index acf337f..bed4fcb 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -16,6 +16,14 @@ #define FSP_VER_LEN 30 +#if CONFIG(PLATFORM_USES_FSP2_4) +#define FSPM_ARCHx_UPD FSPM_ARCH2_UPD +#define FSPS_ARCHx_UPD FSPS_ARCH2_UPD +#else +#define FSPM_ARCHx_UPD FSPM_ARCH_UPD +#define FSPS_ARCHx_UPD FSPS_ARCH_UPD +#endif + /* Macro for checking and loading array type configs into array type UPDs */ #define FSP_ARRAY_LOAD(dst, src) \ do { \ @@ -48,6 +56,11 @@ void *multi_phase_param_ptr; }; +struct fsp_multi_phase_get_number_of_phases_params { + uint32_t number_of_phases; + uint32_t phases_executed; +}; + struct hob_resource { uint8_t owner_guid[16]; uint32_t type; @@ -198,7 +211,7 @@ typedef asmlinkage uint32_t (*fsp_memory_init_fn) (void *raminit_upd, void **hob_list); typedef asmlinkage uint32_t (*fsp_silicon_init_fn)(void *silicon_upd); -typedef asmlinkage uint32_t (*fsp_multi_phase_si_init_fn)(struct fsp_multi_phase_params *); +typedef asmlinkage uint32_t (*fsp_multi_phase_init_fn)(struct fsp_multi_phase_params *); typedef asmlinkage uint32_t (*fsp_notify_fn)(struct fsp_notify_params *); #include <fsp/debug.h> diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index c096e86..922bca2 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -28,6 +28,12 @@ #include <intelbasecode/ramtop.h> #endif +/* Callbacks for SoC/Mainboard specific overrides */ +void __weak platform_fsp_memory_multi_phase_init_cb(uint32_t phase_index) +{ + /* Leave for the SoC/Mainboard to implement if necessary. */ +} + static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); /* @@ -84,7 +90,7 @@ romstage_handoff_init(s3wake); } -static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t version) +static void fsp_fill_mrc_cache(FSPM_ARCHx_UPD *arch_upd, uint32_t version) { void *data; size_t mrc_size; @@ -127,7 +133,7 @@ return CB_SUCCESS; } -static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd, +static enum cb_err setup_fsp_stack_frame(FSPM_ARCHx_UPD *arch_upd, const struct memranges *memmap) { uintptr_t stack_begin; @@ -148,7 +154,7 @@ return CB_SUCCESS; } -static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, +static enum cb_err fsp_fill_common_arch_params(FSPM_ARCHx_UPD *arch_upd, bool s3wake, uint32_t version, const struct memranges *memmap) { @@ -275,12 +281,68 @@ return ver; } +static void fspm_return_value_handler(const char *context, uint32_t status, bool die_on_error) +{ + if (status == FSP_SUCCESS) + return; + + fsp_handle_reset(status); + if (die_on_error) + die_with_post_code(POSTCODE_RAM_FAILURE, "%s returned with error 0x%zx!\n", + context, (size_t)status); + + printk(BIOS_SPEW, "%s returned 0x%zx\n", context, (size_t)status); +} + +static void fspm_multi_phase_init(const struct fsp_header *hdr) +{ + uint32_t status; + fsp_multi_phase_init_fn fsp_multi_phase_init; + struct fsp_multi_phase_params multi_phase_params; + struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number; + + if (!hdr->fsp_multi_phase_mem_init_entry_offset) + return; + + fsp_multi_phase_init = (fsp_multi_phase_init_fn)(uintptr_t) + (hdr->image_base + hdr->fsp_multi_phase_mem_init_entry_offset); + + post_code(POSTCODE_FSP_MULTI_PHASE_MEM_INIT_ENTRY); + timestamp_add_now(TS_FSP_MULTI_PHASE_MEM_INIT_START); + + /* Get number of phases */ + multi_phase_params.multi_phase_action = GET_NUMBER_OF_PHASES; + multi_phase_params.phase_index = 0; + multi_phase_params.multi_phase_param_ptr = &multi_phase_get_number; + status = fsp_multi_phase_init(&multi_phase_params); + fspm_return_value_handler("FspMultiPhaseMemInit NumberOfPhases", status, false); + + /* Execute all phases */ + for (uint32_t i = 1; i <= multi_phase_get_number.number_of_phases; i++) { + printk(BIOS_SPEW, "Executing Phase %u of FspMultiPhaseMemInit\n", i); + /* + * Give SoC/mainboard a chance to perform any operation before + * Multi Phase Execution + */ + platform_fsp_memory_multi_phase_init_cb(i); + + multi_phase_params.multi_phase_action = EXECUTE_PHASE; + multi_phase_params.phase_index = i; + multi_phase_params.multi_phase_param_ptr = NULL; + status = fsp_multi_phase_init(&multi_phase_params); + fspm_return_value_handler("FspMultiPhaseMemInit Execute", status, false); + } + + post_code(POSTCODE_FSP_MULTI_PHASE_MEM_INIT_EXIT); + timestamp_add_now(TS_FSP_MULTI_PHASE_MEM_INIT_END); +} + static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) { uint32_t status; fsp_memory_init_fn fsp_raminit; FSPM_UPD fspm_upd, *upd; - FSPM_ARCH_UPD *arch_upd; + FSPM_ARCHx_UPD *arch_upd; uint32_t version; const struct fsp_header *hdr = &context->header; const struct memranges *memmap = &context->memmap; @@ -371,11 +433,10 @@ timestamp_add_now(TS_FSP_MEMORY_INIT_END); /* Handle any errors returned by FspMemoryInit */ - fsp_handle_reset(status); - if (status != FSP_SUCCESS) { - die_with_post_code(POSTCODE_RAM_FAILURE, - "FspMemoryInit returned with error 0x%08x!\n", status); - } + fspm_return_value_handler("FspMemoryInit", status, true); + + if (CONFIG(PLATFORM_USES_FSP2_4)) + fspm_multi_phase_init(hdr); do_fsp_post_memory_init(s3wake, version); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 4be4b61..4da5098 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -21,11 +21,6 @@ struct fsp_header fsps_hdr; -struct fsp_multi_phase_get_number_of_phases_params { - uint32_t number_of_phases; - uint32_t phases_executed; -}; - /* Callbacks for SoC/Mainboard specific overrides */ void __weak platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index) { @@ -84,7 +79,7 @@ static void fsp_fill_common_arch_params(FSPS_UPD *supd) { #if CONFIG(FSPS_HAS_ARCH_UPD) - FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd; + FSPS_ARCHx_UPD *s_arch_cfg = &supd->FspsArchUpd; s_arch_cfg->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled(); #endif } @@ -94,7 +89,7 @@ FSPS_UPD *upd, *supd; fsp_silicon_init_fn silicon_init; uint32_t status; - fsp_multi_phase_si_init_fn multi_phase_si_init; + fsp_multi_phase_init_fn multi_phase_si_init; struct fsp_multi_phase_params multi_phase_params; struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number; diff --git a/src/drivers/intel/fsp2_0/upd_display.c b/src/drivers/intel/fsp2_0/upd_display.c index 63d6e60..0883390 100644 --- a/src/drivers/intel/fsp2_0/upd_display.c +++ b/src/drivers/intel/fsp2_0/upd_display.c @@ -16,8 +16,8 @@ } } -static void fspm_display_arch_params(const FSPM_ARCH_UPD *old, - const FSPM_ARCH_UPD *new) +static void fspm_display_arch_params(const FSPM_ARCHx_UPD *old, + const FSPM_ARCHx_UPD *new) { /* Display the architectural parameters for MemoryInit */ printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: %p\n", diff --git a/util/cbfstool/eventlog.c b/util/cbfstool/eventlog.c index a87ca98..e090ebe 100644 --- a/util/cbfstool/eventlog.c +++ b/util/cbfstool/eventlog.c @@ -411,6 +411,8 @@ {POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT, "FPS-S Init Exit"}, {POSTCODE_FSP_NOTIFY_AFTER_ENUMERATE, "FSP Notify After Enumerate"}, {POSTCODE_FSP_NOTIFY_AFTER_FINALIZE, "FSP Notify After Finalize"}, + {POSTCODE_FSP_MULTI_PHASE_MEM_INIT_ENTRY, "FSP-M Init Enter"}, + {POSTCODE_FSP_MULTI_PHASE_MEM_INIT_EXIT, "FPS-M Init Exit"}, {POSTCODE_INVALID_ROM, "Invalid ROM"}, {POSTCODE_INVALID_CBFS, "Invalid CBFS"}, {POSTCODE_INVALID_VENDOR_BINARY, "Invalid Vendor Binary"}, -- To view, visit https://review.coreboot.org/c/coreboot/+/80275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Gerrit-Change-Number: 80275 Gerrit-PatchSet: 25 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Add "silicon" to the multiphase callback name
by Subrata Banik (Code Review) 08 Mar '24

08 Mar '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81094?usp=email ) Change subject: drivers/intel/fsp2_0: Add "silicon" to the multiphase callback name ...................................................................... drivers/intel/fsp2_0: Add "silicon" to the multiphase callback name The `platform_fsp_multi_phase_init_cb' callback is specific to FSP-S, let's rename it 'platform_fsp_silicon_multi_phase_init_cb' to avoid any confusion. Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81094 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/silicon_init.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/tigerlake/fsp_params.c 5 files changed, 6 insertions(+), 6 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Dinesh Gehlot: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index c035452..40a64e6 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -48,7 +48,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); /* Callbacks for SoC/Mainboard specific overrides */ -void platform_fsp_multi_phase_init_cb(uint32_t phase_index); +void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index); /* Check if MultiPhase Si Init is enabled */ bool fsp_is_multi_phase_init_enabled(void); /* diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index e543628..4be4b61 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -27,7 +27,7 @@ }; /* Callbacks for SoC/Mainboard specific overrides */ -void __weak platform_fsp_multi_phase_init_cb(uint32_t phase_index) +void __weak platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index) { /* Leave for the SoC/Mainboard to implement if necessary. */ } @@ -190,7 +190,7 @@ * Give SoC/mainboard a chance to perform any operation before * Multi Phase Execution */ - platform_fsp_multi_phase_init_cb(i); + platform_fsp_silicon_multi_phase_init_cb(i); multi_phase_params.multi_phase_action = EXECUTE_PHASE; multi_phase_params.phase_index = i; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index b432030..46555b0 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -1342,7 +1342,7 @@ * 1 | After TCSS initialization completed | for TCSS specific init * 2 | Before BIOS Reset CPL is set by FSP-S | for CPU specific init */ -void platform_fsp_multi_phase_init_cb(uint32_t phase_index) +void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index) { switch (phase_index) { case 1: diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 971fa33..a02d4b9 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -838,7 +838,7 @@ * 1 | After TCSS initialization completed | for TCSS specific init * 2 | Before BIOS Reset CPL is set by FSP-S | for CPU specific init */ -void platform_fsp_multi_phase_init_cb(uint32_t phase_index) +void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index) { switch (phase_index) { case 1: diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 358536e..3326935 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -659,7 +659,7 @@ * ------- + ------------------------------------------------ + ------------------------------- * 1 | After TCSS initialization completed | for TCSS specific init */ -void platform_fsp_multi_phase_init_cb(uint32_t phase_index) +void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index) { switch (phase_index) { case 1: -- To view, visit https://review.coreboot.org/c/coreboot/+/81094?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee Gerrit-Change-Number: 81094 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
by Subrata Banik (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Andrey Petrov, Bora Guvendik, Chen, Gang C, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Martin L Roth, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Tarun, Wonkyu Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80275?usp=email ) Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support ...................................................................... Patch Set 24: (1 comment) Patchset: PS24: > And could you submit it (along with the first one of the relation-chain) once it is Submittable ? Th […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/80275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Gerrit-Change-Number: 80275 Gerrit-PatchSet: 24 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 16:59:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
by Jérémy Compostella (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Andrey Petrov, Bora Guvendik, Chen, Gang C, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Martin L Roth, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, Wonkyu Kim. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80275?usp=email ) Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support ...................................................................... Patch Set 24: (1 comment) Patchset: PS24: > It has been over a day. […] And could you submit it (along with the first one of the relation-chain) once it is Submittable ? Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/80275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Gerrit-Change-Number: 80275 Gerrit-PatchSet: 24 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 16:55:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
by Jérémy Compostella (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Andrey Petrov, Bora Guvendik, Chen, Gang C, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Martin L Roth, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, Wonkyu Kim. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80275?usp=email ) Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support ...................................................................... Patch Set 24: (1 comment) Patchset: PS24: > please allow one more day for other to review the code, otherwise i will mark this comment done and […] It has been over a day. Could you mark this as done ? -- To view, visit https://review.coreboot.org/c/coreboot/+/80275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Gerrit-Change-Number: 80275 Gerrit-PatchSet: 24 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 16:54:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in libgfxinit[main]: gma: Update DP training with new fields
by Subrata Banik (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Angel Pons, Arthur Heymans, Jérémy Compostella, Nick Vaccaro, Nico Huber, Shelley Chen, Tarun Tuli, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/67490?usp=email ) Change subject: gma: Update DP training with new fields ...................................................................... Patch Set 24: (1 comment) Patchset: PS23: > No, I just meant to put them on a linear branch again. If you look at the > current relation chain (top right), it's rather broken. With mixed abandoned, > merged and out-of-date changes. It's hard for reviewers to see where to > continue, so I'll try to clear that up next week. thanks for the clarification. I will wait for the recipe. -- To view, visit https://review.coreboot.org/c/libgfxinit/+/67490?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: main Gerrit-Change-Id: I3f7f8a93408a74cfa29d1493a48c88ce73dc690c Gerrit-Change-Number: 67490 Gerrit-PatchSet: 24 Gerrit-Owner: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 15:45:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/docker/Makefile: Create Documentation/_build for docker-build-docs
by Nicholas Chin (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Felix Singer, Martin L Roth. Hello Felix Singer, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81127?usp=email to look at the new patch set (#2). Change subject: util/docker/Makefile: Create Documentation/_build for docker-build-docs ...................................................................... util/docker/Makefile: Create Documentation/_build for docker-build-docs If the host directory of a bind mount does not exist, Docker will create it. However, the newly created directory will be owned root user due to the Docker service running within a root context. The docker command in the recipe for docker-build-docs binds Documentation/_build to /data-out within the container, so if it doesn't already exist, the documentation builder will be unable to copy the HTML output into /data-out since it runs with the same UID and GID as the host user. By creating the directory if necessary before the `docker run` command, there should always be an existing _build directory owned by the host user for docker to bind /data-out to (ignoring the case of an existing _build directory the current user does not have permission to write to). Change-Id: I6be9bc1fdca48f4d924f5c07cc261189ab6862fd Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/docker/Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/81127/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81127?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6be9bc1fdca48f4d924f5c07cc261189ab6862fd Gerrit-Change-Number: 81127 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: util/docker/Makefile: Create Documentation/_build for docker-build-docs
by Nicholas Chin (Code Review) 08 Mar '24

08 Mar '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81127?usp=email ) Change subject: util/docker/Makefile: Create Documentation/_build for docker-build-docs ...................................................................... util/docker/Makefile: Create Documentation/_build for docker-build-docs If the _build directory doesn't exist, Docker will create it due to _build being specified as the host directory to bind mount to /data-in within the container. However, the newly created directory will be owned root user due to the way Docker operates, resulting in the container being unable to copy the HTML output into _build since it builds the documentation with the same UID and GID as the host user. Change-Id: I6be9bc1fdca48f4d924f5c07cc261189ab6862fd Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/docker/Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/81127/1 diff --git a/util/docker/Makefile b/util/docker/Makefile index 77526bb..45562d7 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -177,6 +177,7 @@ docker-build-docs: test-docker docker-build-docs: + mkdir -p $(top)/Documentation/_build $(DOCKER) run -it --rm \ --user $(UID):$(GID) \ -v "$(top)/:/data-in/:ro" \ -- To view, visit https://review.coreboot.org/c/coreboot/+/81127?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6be9bc1fdca48f4d924f5c07cc261189ab6862fd Gerrit-Change-Number: 81127 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/cmn/cse: Simplify logic to get CSE RW version
by Jon Murphy (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81051?usp=email ) Change subject: soc/intel/cmn/cse: Simplify logic to get CSE RW version ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > could you please share the full name or email ID? You're seeing hexdump in the docker image as an artifact of including bsdextrautils(https://github.com/coreboot/coreboot/blob/main/util/docker/co… as Paul pointed out previously, but it isn't explicitly called out as a dependency(https://github.com/coreboot/coreboot/blob/main/util/docker/coreb… or required installation. For what it's worth, I personally have never used the docker container to build(Downstream we also don't use the container and would need to ensure that hexdump is installed in the chroot). So I think it's worth explicitly adding it to the Dockerfile manifest and documentation showing that it's necessary to build coreboot. Without doing so, you have potential to break in the future when hexdump is no longer bundled with bsdextrautils by default or we remove that package all together. We should aim to have the most seamless and stable experience for the developers when adding these types of dependencies. -- To view, visit https://review.coreboot.org/c/coreboot/+/81051?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86f2848788d0576a8fe3557fa8048e4162e61e05 Gerrit-Change-Number: 81051 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 08 Mar 2024 13:59:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit March 2024