coreboot-gerrit March 2024

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[M] Change in coreboot[master]: checkpoint commit
by ron minnich (Code Review) 08 Mar '24

08 Mar '24

ron minnich has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81131?usp=email ) Change subject: checkpoint commit ...................................................................... Abandoned goddam it -- To view, visit https://review.coreboot.org/c/coreboot/+/81131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I013663c7b68abf7b3b8a9dd89d9a585445fee3f1 Gerrit-Change-Number: 81131 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[main]: Add a new config variable, RISCV_PRIV_VERSION
by ron minnich (Code Review) 08 Mar '24

08 Mar '24

ron minnich has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81088?usp=email ) Change subject: Add a new config variable, RISCV_PRIV_VERSION ...................................................................... Abandoned juice is not worth the squeeze -- To view, visit https://review.coreboot.org/c/coreboot/+/81088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife8d2b70f115c4193b9a8434ebe05893c20224b6 Gerrit-Change-Number: 81088 Gerrit-PatchSet: 3 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[main]: arch/riscv: use PMP
by ron minnich (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81153?usp=email ) Change subject: arch/riscv: use PMP ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: new CL. Gerrit won, I lost. -- To view, visit https://review.coreboot.org/c/coreboot/+/81153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6edce139d340783148cbb446cde004ba96e67944 Gerrit-Change-Number: 81153 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 18:28:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/riscv: use PMP
by ron minnich (Code Review) 08 Mar '24

08 Mar '24

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81153?usp=email ) Change subject: arch/riscv: use PMP ...................................................................... arch/riscv: use PMP With this change, a simple S-mode payload works: 1: li a7, 1 li a0, 48 ecall j 1b Without this change, it will not work. Linux also boots with this on the command line: clk_ignore_unused Resolving that problem will require a separate patch. Getting this to build on RV32 required changes to the API, as it was incorrect. In RV32, PMP entries are 34 bits. Hence, the setup_pmp needed to accept u64. So, uinptr_t can not be used, as on 32 bits they are only 32 bit numbers. The internal API uses uintptr_t, but the exported API uses u64, so external code does not have to think about right shifts on base and size. Errors are detected: an error in base and size will result in a BIOS_EMERG print, but not a panic. Boots not bricks if possible. There are small changes to the internal API to reduce stack pressure: there's no need to have two pmpcfg_t on the stack when one will do. PMPs are just packed with all kinds of special cases. There are no requirements that you read back what you wrote to the PMPaddr registers. An SoC can just decide it only does 4096-byte granularity, and that is your problem if you wanted finer granulatiry. SoC's don't have to implement all the high order bits either. Finally, since it's a memory address range, the SoC need only implement enough bits for the memory bus, not the address space of the chip! PMPs are best used sparingly. Change-Id: I6edce139d340783148cbb446cde004ba96e67944 Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/include/arch/pmp.h M src/arch/riscv/payload.c M src/arch/riscv/pmp.c 3 files changed, 140 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/81153/1 diff --git a/src/arch/riscv/include/arch/pmp.h b/src/arch/riscv/include/arch/pmp.h index b25fc96..f98adf7 100644 --- a/src/arch/riscv/include/arch/pmp.h +++ b/src/arch/riscv/include/arch/pmp.h @@ -14,7 +14,13 @@ /* reset PMP setting */ void reset_pmp(void); -/* set up PMP record */ -void setup_pmp(uintptr_t base, uintptr_t size, uintptr_t flags); +/* + * set up PMP record + * reminder: base and size are 34-bits on RV32. + */ +void setup_pmp(u64 base, u64 size, u8 flags); + +/* write the last PMP record, i.e. the "default" case. */ +void close_pmp(void); #endif /* __RISCV_PMP_H__ */ diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c index ee2ee8e..2a7d5d0 100644 --- a/src/arch/riscv/payload.c +++ b/src/arch/riscv/payload.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cbmem.h> #include <program_loading.h> #include <stdint.h> #include <arch/boot.h> #include <arch/encoding.h> +#include <arch/pmp.h> #include <arch/smp/atomic.h> #include <console/console.h> #include <vm.h> @@ -36,10 +38,35 @@ void (*doit)(int hart_id, void *fdt) = prog_entry(prog); int hart_id = read_csr(mhartid); uintptr_t status = read_csr(mstatus); + extern void *_text, *_estack; status = INSERT_FIELD(status, MSTATUS_MPIE, 0); switch (payload_mode) { case RISCV_PAYLOAD_MODE_S: + /* + * Set up a PMP to protect coreboot, then close the PMPs. + * If a mainboard or SoC needs other ranges + * set up, they should do so before this point, + * as close_pmp puts in a "match all" entry, and + * PMPs are processed in linear order. + */ + + /* + * On this code path, coreboot is providing the coreboot SBI, and must + * protect the ramstage, from _text to _estack, from S and U + * modes. Because the number of PMP registers may be very + * small, make this an NAPOT area. The linker scripts + * should round _text and _estack to 4K. + */ + setup_pmp((u64)(uintptr_t) _text, + (u64)(uintptr_t) _estack - (u64)(uintptr_t) _text, 0); + + /* + * All pmp operations should be finished when close_pmp is called. + * Presently, this requirement is not enforced. + */ + close_pmp(); + status = INSERT_FIELD(status, MSTATUS_MPP, PRV_S); /* Trap vector base address point to the payload */ write_csr(stvec, doit); diff --git a/src/arch/riscv/pmp.c b/src/arch/riscv/pmp.c index ee39ac4..08b3493 100644 --- a/src/arch/riscv/pmp.c +++ b/src/arch/riscv/pmp.c @@ -28,6 +28,12 @@ /* This variable is used to record which entries have been used. */ static uintptr_t pmp_entry_used_mask; +/* The architectural spec says that up to 16 PMP entries are available. */ +int pmp_entries_num(void) +{ + return 16; +} + /* helper function used to read pmpcfg[idx] */ static uintptr_t read_pmpcfg(int idx) { @@ -96,17 +102,21 @@ new = (old & ~((uintptr_t)0xff << shift)) | ((cfg & 0xff) << shift); write_csr(pmpcfg0, new); + printk(BIOS_INFO, "%s(%d, %lx) = %lx\n", __func__, idx, cfg, read_csr(pmpcfg0)); break; case 1: old = read_csr(pmpcfg2); new = (old & ~((uintptr_t)0xff << shift)) | ((cfg & 0xff) << shift); write_csr(pmpcfg2, new); + printk(BIOS_INFO, "%s(%d, %lx) = %lx\n", __func__, idx, cfg, read_csr(pmpcfg2)); break; } #endif - if (read_pmpcfg(idx) != cfg) - die("write pmpcfg failure!"); + if (read_pmpcfg(idx) != cfg) { + printk(BIOS_WARNING, "%s: PMPcfg%d: Wrote %lx, read %lx\n", __func__, idx, cfg, read_pmpcfg(idx)); + die("PMPcfg write failed"); + } } /* helper function used to read pmpaddr[idx] */ @@ -202,41 +212,64 @@ write_csr(pmpaddr15, val); break; } - if (read_pmpaddr(idx) != val) - die("write pmpaddr failure"); + + printk(BIOS_INFO, "%s(%d, %lx) = %lx\n", __func__, idx, val, read_pmpaddr(idx)); + /* The PMP is not required to return what we wrote. On some SoC, many bits are cleared. */ + if (read_pmpaddr(idx) != val) { + printk(BIOS_WARNING, "%s: PMPaddr%d: Wrote %lx, read %lx\n", __func__, + idx, val, read_pmpaddr(idx)); + } +} + +/* Generate a PMP configuration for all memory */ +static void generate_pmp_all(pmpcfg_t *p) +{ + p->cfg = PMP_NAPOT | PMP_R | PMP_W | PMP_X; + p->previous_address = 0; + p->address = (uintptr_t) -1; } /* Generate a PMP configuration of type NA4/NAPOT */ -static pmpcfg_t generate_pmp_napot( - uintptr_t base, uintptr_t size, uintptr_t flags) +static void generate_pmp_napot(pmpcfg_t *p, uintptr_t base, uintptr_t size, u8 flags) { - pmpcfg_t p; flags = flags & (PMP_R | PMP_W | PMP_X | PMP_L); - p.cfg = flags | (size > GRANULE ? PMP_NAPOT : PMP_NA4); - p.previous_address = 0; - p.address = (base + (size / 2 - 1)) >> PMP_SHIFT; - return p; + p->cfg = flags | (size > GRANULE ? PMP_NAPOT : PMP_NA4); + p->previous_address = 0; + p->address = (base + (size / 2 - 1)); } /* Generate a PMP configuration of type TOR */ -static pmpcfg_t generate_pmp_range( - uintptr_t base, uintptr_t size, uintptr_t flags) +static void generate_pmp_range(pmpcfg_t *p, uintptr_t base, uintptr_t size, u8 flags) { - pmpcfg_t p; flags = flags & (PMP_R | PMP_W | PMP_X | PMP_L); - p.cfg = flags | PMP_TOR; - p.previous_address = base >> PMP_SHIFT; - p.address = (base + size) >> PMP_SHIFT; - return p; + p->cfg = flags | PMP_TOR; + p->previous_address = base; + p->address = (base + size); } -/* Generate a PMP configuration */ -static pmpcfg_t generate_pmp(uintptr_t base, uintptr_t size, uintptr_t flags) +/* + * Generate a PMP configuration. + * reminder: base and size are 34 bit numbers on RV32. + */ +static int generate_pmp(pmpcfg_t *p, u64 base, u64 size, u8 flags) { - if (IS_POWER_OF_2(size) && (size >= 4) && ((base & (size - 1)) == 0)) - return generate_pmp_napot(base, size, flags); - else - return generate_pmp_range(base, size, flags); + uintptr_t b = (uintptr_t) base >> PMP_SHIFT, s = (uintptr_t) size >> PMP_SHIFT; +#if __riscv_xlen == 32 + /* verify that base + size fits in 34 bits */ + if ((base + size - 1) >> 34) { + printk(BIOS_EMERG, "%s: base (%llx) + size (%llx) - 1 is more than 34 bits\n", + __func__, base, size); + return 1; + } +#endif + if (base == (u64)-1) { + generate_pmp_all(p); + } else if (IS_POWER_OF_2(size) && (size >= 4) && ((base & (size - 1)) == 0)) { + generate_pmp_napot(p, b, s, flags); + } else { + generate_pmp_range(p, b, s, flags); + } + return 0; } /* @@ -279,30 +312,72 @@ { for (int i = 0; i < pmp_entries_num(); i++) { if (read_pmpcfg(i) & PMP_L) - die("Some PMP configurations are locked " - "and cannot be reset!"); + die("Some PMP configurations are locked and cannot be reset!"); write_pmpcfg(i, 0); write_pmpaddr(i, 0); } } -/* set up PMP record */ -void setup_pmp(uintptr_t base, uintptr_t size, uintptr_t flags) +/* + * set up PMP record + * Why are these u64 and not uintptr_t? + * because, per the spec: + * The Sv32 page-based virtual-memory scheme described in Section 4.3 + * supports 34-bit physical addresses for RV32, so the PMP scheme must + * support addresses wider than XLEN for RV32. + * Yes, in RV32, these are 34-bit numbers. + * Rather than require every future user of these to remember that, + * this ABI is 64 bits. + * generate_pmp will check for out of range values. + */ +void setup_pmp(u64 base, u64 size, u8 flags) { pmpcfg_t p; int is_range, n; - p = generate_pmp(base, size, flags); + if (generate_pmp(&p, base, size, flags)) + return; + is_range = ((p.cfg & PMP_A) == PMP_TOR); n = find_empty_pmp_entry(is_range); + /* + * NOTE! you MUST write the cfg register first, or on (e.g.) + * the SiFive FU740, it will not take all the bits. + * This is different than QEMU. NASTY! + */ + write_pmpcfg(n, p.cfg); + write_pmpaddr(n, p.address); if (is_range) write_pmpaddr(n - 1, p.previous_address); - write_pmpcfg(n, p.cfg); mask_pmp_entry_used(n); if (is_range) mask_pmp_entry_used(n - 1); } + +/* + * close_pmp will "close" the pmp. + * This consists of adding the "match every address" entry. + * This should be the last pmp function that is called. + * Because we can not be certain that there is not some reason for it + * NOT to be last, we do not check -- perhaps, later, a check would + * make sense, but, for now, we do not check. + * If previous code has used up all pmp entries, print a warning + * and continue. + * The huge constant for the memory size may seem a bit odd here. + * Recall that PMP is to protect a *limited* number of M mode + * memory ranges from S and U modes. Therefore, the last range + * entry should cover all possible addresses, up to + * an architectural limit. It is entirely acceptable + * for it to cover memory that does not exist -- PMP + * protects M mode, nothing more. + * Think of this range as the final catch-all else + * in an if-then-else. + */ +void close_pmp(void) +{ + setup_pmp((u64)-1, 0, PMP_R|PMP_W|PMP_X); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/81153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6edce139d340783148cbb446cde004ba96e67944 Gerrit-Change-Number: 81153 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: arch/riscv: use PMP
by ron minnich (Code Review) 08 Mar '24

08 Mar '24

ron minnich has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81090?usp=email ) Change subject: arch/riscv: use PMP ...................................................................... Abandoned I am liking gerrit less by the day. -- To view, visit https://review.coreboot.org/c/coreboot/+/81090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Gerrit-Change-Number: 81090 Gerrit-PatchSet: 16 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: arch/riscv: use PMP
by ron minnich (Code Review) 08 Mar '24

08 Mar '24

ron minnich has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81152?usp=email ) Change subject: arch/riscv: use PMP ...................................................................... Abandoned goddam gerrit -- To view, visit https://review.coreboot.org/c/coreboot/+/81152?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Gerrit-Change-Number: 81152 Gerrit-PatchSet: 2 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: arch/riscv: use PMP
by ron minnich (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Philipp Hug, ron minnich. Hello Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81152?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: arch/riscv: use PMP ...................................................................... arch/riscv: use PMP With this change, a simple S-mode payload works: 1: li a7, 1 li a0, 48 ecall j 1b Without this change, it will not work. Linux also boots with this on the command line: clk_ignore_unused Resolving that problem will require a separate patch. Getting this to build on RV32 required changes to the API, as it was incorrect. In RV32, PMP entries are 34 bits. Hence, the setup_pmp needed to accept u64. So, uinptr_t can not be used, as on 32 bits they are only 32 bit numbers. The internal API uses uintptr_t, but the exported API uses u64, so external code does not have to think about right shifts on base and size. Errors are detected: an error in base and size will result in a BIOS_EMERG print, but not a panic. Boots not bricks if possible. There are small changes to the internal API to reduce stack pressure: there's no need to have two pmpcfg_t on the stack when one will do. PMPs are just packed with all kinds of special cases. There are no requirements that you read back what you wrote to the PMPaddr registers. An SoC can just decide it only does 4096-byte granularity, and that is your problem if you wanted finer granulatiry. SoC's don't have to implement all the high order bits either. Finally, since it's a memory address range, the SoC need only implement enough bits for the memory bus, not the address space of the chip! PMPs are best used sparingly. Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/include/arch/pmp.h M src/arch/riscv/payload.c M src/arch/riscv/pmp.c 3 files changed, 140 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/81152/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81152?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Gerrit-Change-Number: 81152 Gerrit-PatchSet: 2 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Perform MP init post FSP-MultiPhase SI Init
by Subrata Banik (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Andrey Petrov, Jérémy Compostella, Ronak Kanabar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80691?usp=email ) Change subject: drivers/intel/fsp2_0: Perform MP init post FSP-MultiPhase SI Init ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80691?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec92 Gerrit-Change-Number: 80691 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 18:21:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Add a new config variable, RISCV_PRIV_VERSION
by Philipp Hug (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, ron minnich. Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81088?usp=email ) Change subject: Add a new config variable, RISCV_PRIV_VERSION ...................................................................... Patch Set 2: (2 comments) File src/arch/riscv/Kconfig: https://review.coreboot.org/c/coreboot/+/81088/comment/69f5e37f_7ecdb98f : PS2, Line 113: # Privilege version. There is no default that will work across all privileged specification version https://review.coreboot.org/c/coreboot/+/81088/comment/b6b99d44_f3be5dcb : PS2, Line 116: int can we have a choice instead of an int? I think this would be cleaner e.g. RISCV_PRIV_SPEC_VERSION_V1_10 RISCV_PRIV_SPEC_VERSION_V1_12 -- To view, visit https://review.coreboot.org/c/coreboot/+/81088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife8d2b70f115c4193b9a8434ebe05893c20224b6 Gerrit-Change-Number: 81088 Gerrit-PatchSet: 2 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 18:08:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/riscv: Remove typedefs
by Philipp Hug (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Martin L Roth, Maximilian Brune, ron minnich. Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81124?usp=email ) Change subject: arch/riscv: Remove typedefs ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id51eda53b6b53ed2cc66c0339c03c855c12c1bd8 Gerrit-Change-Number: 81124 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 17:57:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2024