coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION
by Ronak Kanabar (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Krishna P Bhat D, Nick Vaccaro, Ronak Kanabar, V Sowmya. Hello Dinesh Gehlot, Kapil Porwal, Krishna P Bhat D, Nick Vaccaro, Subrata Banik, V Sowmya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81038?usp=email to look at the new patch set (#5). Change subject: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION ...................................................................... soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION This patch is to add support to store MRC cache using MRC version in TWL. select MRC_CACHE_USING_MRC_VERSION if SOC_INTEL_TWINLAKE selcted. BUG=b:296433836 Change-Id: Icc7e4ecd84a7d2818d54acc6ac5d0592544bb9ce Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81038/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc7e4ecd84a7d2818d54acc6ac5d0592544bb9ce Gerrit-Change-Number: 81038 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Unshare SMM related Kconfigs
by Jincheng Li (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Shuo Liu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81134?usp=email to review the following change. Change subject: soc/intel/xeon_sp: Unshare SMM related Kconfigs ...................................................................... soc/intel/xeon_sp: Unshare SMM related Kconfigs Allow for options that platform is with FSP based SMM handlers. Change-Id: Icc5f71e44f573575d599d2617a037bfd14e79dec Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/spr/Kconfig 4 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/81134/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 52aaec17..1e9cdd3 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -13,7 +13,6 @@ select FSP_M_XIP select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS select FSP_T_XIP - select HAVE_SMI_HANDLER select INTEL_CAR_NEM # For postcar only now select INTEL_DESCRIPTOR_MODE_CAPABLE select PARALLEL_MP_AP_WORK @@ -29,7 +28,6 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE - select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_TCO select SOC_INTEL_COMMON_PCH_SERVER select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 51e545f..cd4fa3b 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -9,6 +9,8 @@ select HAVE_INTEL_FSP_REPO select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND select UDK_202005_BINDING + select HAVE_SMI_HANDLER + select SOC_INTEL_COMMON_BLOCK_SMM help Intel Cooper Lake-SP support diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 4a9e683..3913568 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -6,6 +6,8 @@ select PLATFORM_USES_FSP2_0 select NO_FSP_TEMP_RAM_EXIT select UDK_202005_BINDING + select HAVE_SMI_HANDLER + select SOC_INTEL_COMMON_BLOCK_SMM help Intel Skylake-SP support diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 3c3c45a..6264c51 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -16,6 +16,8 @@ select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND select UDK_202005_BINDING select SOC_INTEL_HAS_CXL + select HAVE_SMI_HANDLER + select SOC_INTEL_COMMON_BLOCK_SMM help Intel Sapphire Rapids-SP support -- To view, visit https://review.coreboot.org/c/coreboot/+/81134?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc5f71e44f573575d599d2617a037bfd14e79dec Gerrit-Change-Number: 81134 Gerrit-PatchSet: 1 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: arch/x86/include/arch: Add feature check macros
by Jincheng Li (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Shuo Liu. Hello Shuo Liu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81133?usp=email to review the following change. Change subject: arch/x86/include/arch: Add feature check macros ...................................................................... arch/x86/include/arch: Add feature check macros Add feature check macros for MCE (machine check exception) and MCA (machine check architecture) Change-Id: I014c25ced1dbe21f35486f8305b1de7669e932d0 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/arch/x86/include/arch/cpu.h M src/cpu/intel/common/hyperthreading.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/81133/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 0c4decf..ff59746 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -48,8 +48,10 @@ #define X86_VENDOR_UNKNOWN 0xff #define CPUID_FEATURE_PAE (1 << 6) +#define CPUID_FEATURE_MCE (1 << 7) +#define CPUID_FEATURE_MCA (1 << 14) #define CPUID_FEATURE_PSE36 (1 << 17) -#define CPUID_FEAURE_HTT (1 << 28) +#define CPUID_FEATURE_HTT (1 << 28) /* Structured Extended Feature Flags */ #define CPUID_STRUCT_EXTENDED_FEATURE_FLAGS 0x7 diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c index 85c4477..d034129 100644 --- a/src/cpu/intel/common/hyperthreading.c +++ b/src/cpu/intel/common/hyperthreading.c @@ -7,7 +7,7 @@ bool intel_ht_supported(void) { /* Is HyperThreading supported? */ - return !!(cpuid_edx(1) & CPUID_FEAURE_HTT); + return !!(cpuid_edx(1) & CPUID_FEATURE_HTT); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/81133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I014c25ced1dbe21f35486f8305b1de7669e932d0 Gerrit-Change-Number: 81133 Gerrit-PatchSet: 1 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: intel/alderlake/Kconfig: select Kconfig MRC_CACHE_USING_MRC_VERSION
by Subrata Banik (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Krishna P Bhat D, Nick Vaccaro, Ronak Kanabar, V Sowmya. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81038?usp=email ) Change subject: intel/alderlake/Kconfig: select Kconfig MRC_CACHE_USING_MRC_VERSION ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81038/comment/b27689ef_03186f0e : PS4, Line 6: : intel/alderlake/Kconfig soc/intel/adl: -- To view, visit https://review.coreboot.org/c/coreboot/+/81038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc7e4ecd84a7d2818d54acc6ac5d0592544bb9ce Gerrit-Change-Number: 81038 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 09:00:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_add_dram_resources
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81110?usp=email ) Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources ...................................................................... Patch Set 2: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81110/comment/680bbfd5_8d72df1f : PS1, Line 9: SoC > This seems to move code around for no apparent reason. […] Right, will have. https://review.coreboot.org/c/coreboot/+/81110/comment/8e2eaa57_1e8bac29 : PS1, Line 10: acorss > across Acknowledged Patchset: PS2: Good catches, thanks! File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/81110/comment/931861dc_02ae77a9 : PS1, Line 201: uint64_t > static uint64_t Acknowledged https://review.coreboot.org/c/coreboot/+/81110/comment/f42b9af4_97b9ac43 : PS1, Line 304: Ahe > The Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/81110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b0bb8e8c51ef20467958826b9fdd5a995e14901 Gerrit-Change-Number: 81110 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 08 Mar 2024 09:00:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_add_dram_resources
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81110?usp=email to look at the new patch set (#3). Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources ...................................................................... soc/intel/xeon_sp: Add soc_add_dram_resources SoC specific DRAM resource, e.g. 4GB above memory map, are different across SoC generations. This patch separates the codes so that later SoC integration would be based on this. TEST=intel/archercity CRB Change-Id: I8b0bb8e8c51ef20467958826b9fdd5a995e14901 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/uncore.c 2 files changed, 45 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/81110/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b0bb8e8c51ef20467958826b9fdd5a995e14901 Gerrit-Change-Number: 81110 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_add_dram_resources
by Shuo Liu (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81110?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources ...................................................................... soc/intel/xeon_sp: Add soc_add_dram_resources SoC specific DRAM resource, e.g. 4GB above memory map, are different acorss SoC generations. This patch separates the codes so that later SoC integration would be based on this. TEST=intel/archercity CRB Change-Id: I8b0bb8e8c51ef20467958826b9fdd5a995e14901 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/uncore.c 2 files changed, 45 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/81110/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b0bb8e8c51ef20467958826b9fdd5a995e14901 Gerrit-Change-Number: 81110 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/brya: Create nova variant
by David Wu (Code Review) 08 Mar '24

08 Mar '24

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81132?usp=email ) Change subject: mb/google/brya: Create nova variant ...................................................................... mb/google/brya: Create nova variant Create the nova variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:328711879 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_NOVA Change-Id: Ie1cee43f0e2545288130bcc5152075603695c395 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/nova/include/variant/ec.h A src/mainboard/google/brya/variants/nova/include/variant/gpio.h A src/mainboard/google/brya/variants/nova/overridetree.cb 5 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/81132/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index b85aa5a..bf0825d 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -331,6 +331,10 @@ config BOARD_GOOGLE_NOKRIS select BOARD_GOOGLE_BASEBOARD_NISSA +config BOARD_GOOGLE_NOVA + select BOARD_GOOGLE_BASEBOARD_BRASK + select SOC_INTEL_RAPTORLAKE + config BOARD_GOOGLE_OMNIGUL select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_WIFI_SAR if CHROMEOS @@ -597,6 +601,7 @@ default 0x0 if BOARD_GOOGLE_ANRAGGAR default 0x1 if BOARD_GOOGLE_XOL default 0x0 if BOARD_GOOGLE_GLASSWAY + default 0x1 if BOARD_GOOGLE_NOVA config DRIVER_TPM_I2C_ADDR hex @@ -681,6 +686,7 @@ default "Anraggar" if BOARD_GOOGLE_ANRAGGAR default "Xol" if BOARD_GOOGLE_XOL default "Glassway" if BOARD_GOOGLE_GLASSWAY + default "Nova" if BOARD_GOOGLE_NOVA config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -736,6 +742,7 @@ default "anraggar" if BOARD_GOOGLE_ANRAGGAR default "xol" if BOARD_GOOGLE_XOL default "glassway" if BOARD_GOOGLE_GLASSWAY + default "nova" if BOARD_GOOGLE_NOVA config VBOOT select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index bea92b6..c126558 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -160,3 +160,6 @@ config BOARD_GOOGLE_XOL bool "-> Xol" + +config BOARD_GOOGLE_NOVA + bool "-> Nova" diff --git a/src/mainboard/google/brya/variants/nova/include/variant/ec.h b/src/mainboard/google/brya/variants/nova/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/nova/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/nova/include/variant/gpio.h b/src/mainboard/google/brya/variants/nova/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/nova/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/nova/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/81132?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie1cee43f0e2545288130bcc5152075603695c395 Gerrit-Change-Number: 81132 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[main]: lib/device_tree: Add some FDT helper functions
by Jakub Czapiga (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Julius Werner, Martin L Roth, Maximilian Brune. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81081?usp=email ) Change subject: lib/device_tree: Add some FDT helper functions ...................................................................... Patch Set 6: (3 comments) Patchset: PS6: > > Test failed with exception: Segmentation fault(11) […] I tested it on my machine and it fails too. There is incorrect memory access in `tests_lib_device_tree-test(tests).test_fdt_find_node_by_path` 1. You should align arrays: > The devicetree blob shall be located at an 8-byte-aligned address. To maintain backwards compatibilty for 32-bit machines, 4-byte alignment is supported by some software, but this is not DTSpec-compliant. ``` uint8_ dtb[] __attribute__((aligned(8))) = ... ``` 2. Code segfaults at: ```log [==========] tests_lib_device_tree-test(tests): Running 4 test(s). [ RUN ] test_fdt_find_node_by_path Program received signal SIGSEGV, Segmentation fault. 0x0000000000401ac0 in fdt_find_multiple_nodes_by_path (blob=blob@entry=0x41d980 <dtb>, path=<optimized out>, path@entry=0x4020ad "/cpus/cpu@*", addrcp=addrcp@entry=0x7fffffffce50, sizecp=sizecp@entry=0x7fffffffce54, results=results@entry=0x7fffffffce58, count_results=count_results@entry=0x7fffffffce4e) at src/lib/device_tree.c:272 272 node_offset = results[(*count_results)++] = off; // save occurrence (gdb) where #0 0x0000000000401ac0 in fdt_find_multiple_nodes_by_path (blob=blob@entry=0x41d980 <dtb>, path=<optimized out>, path@entry=0x4020ad "/cpus/cpu@*", addrcp=addrcp@entry=0x7fffffffce50, sizecp=sizecp@entry=0x7fffffffce54, results=results@entry=0x7fffffffce58, count_results=count_results@entry=0x7fffffffce4e) at src/lib/device_tree.c:272 #1 0x00000000004015a3 in test_fdt_find_node_by_path (state=<optimized out>) at tests/lib/device_tree-test.c:50 #2 0x00007ffff7fbb75d in cmocka_run_one_test_or_fixture () from build/tests/util/cmocka/src/libcmocka.so.0 #3 0x00007ffff7fbba2b in cmocka_run_one_tests () from build/tests/util/cmocka/src/libcmocka.so.0 #4 0x00007ffff7fbbfb1 in _cmocka_run_group_tests () from build/tests/util/cmocka/src/libcmocka.so.0 #5 0x00000000004010ab in main () at tests/lib/device_tree-test.c:97 ``` `count_results` reaches absurd numbers in thousands, because you use it without initialization, as was passed from caller. ALSO please fix checkpatch issues wherever possible. xxd files can be omited. File src/lib/device_tree.c: https://review.coreboot.org/c/coreboot/+/81081/comment/4d305d44_016460a1 : PS6, Line 67: size = fdt_next_node_name(blob, offset, &name); `int size = ...`. Let's not multiply code without need. https://review.coreboot.org/c/coreboot/+/81081/comment/38d9202f_d945ef0d : PS6, Line 272: node_offset = results[(*count_results)++] = off; // save occurrence `count_results` is left uninitialized. More info in another comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/81081?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8 Gerrit-Change-Number: 81081 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Mar 2024 08:43:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS
by Patrick Rudolph (Code Review) 08 Mar '24

08 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80795?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+2 by Arthur Heymans, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS ...................................................................... soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS Drop SPI_BASE_ADDRESS from _CRS since this address is just a regular PCI BAR on the FASTSPI PCI device. Currently the PCI device is always visible and thus doesn't need special care in the host-bridge _CRS. In case the PCI device will be hidden in PCI config space the fast_spi driver could be updated to generate the _CRS and thus mark the SPI_BASE_ADDRESS as reserved. Change-Id: I150397a7ac5d60719f327f6ac6480a38fe295c32 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/spr/soc_acpi.c 3 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/80795/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/80795?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I150397a7ac5d60719f327f6ac6480a38fe295c32 Gerrit-Change-Number: 80795 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2024