coreboot-gerrit March 2024

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[M] Change in coreboot[main]: arch/riscv: use PMP
by ron minnich (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81090?usp=email to look at the new patch set (#10). Change subject: arch/riscv: use PMP ...................................................................... arch/riscv: use PMP With this change, a simple S-mode payload works: 1: li a7, 1 li a0, 48 ecall j 1b Without this change, it will not work. Linux also boots with this on the command line: clk_ignore_unused Resolving that problem will require a separate patch. Getting this to build on RV32 required changes to the API, as it was incorrect. In RV32, PMP entries are 34 bits. Hence, the setup_pmp needed to accept u64. So, uinptr_t can not be used, as on 32 bits they are only 32 bit numbers. The internal API uses uintptr_t, but the exported API uses u64, so external code does not have to think about right shifts on base and size. Errors are detected: an error in base and size will result in a BIOS_EMERG print, but not a panic. Boots not bricks if possible. There are small changes to the internal API to reduce stack pressure: there's no need to have two pmpcfg_t on the stack when one will do. Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/include/arch/pmp.h M src/arch/riscv/payload.c M src/arch/riscv/pmp.c 3 files changed, 109 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/81090/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/81090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Gerrit-Change-Number: 81090 Gerrit-PatchSet: 10 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: arch/riscv: use PMP
by ron minnich (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81090?usp=email to look at the new patch set (#9). Change subject: arch/riscv: use PMP ...................................................................... arch/riscv: use PMP With this change, a simple S-mode payload works: 1: li a7, 1 li a0, 48 ecall j 1b Without this change, it will not work. Linux also boots with this on the command line: clk_ignore_unused Resolving that problem will require a separate patch. Getting this to build on RV32 required changes to the API, as it was incorrect. In RV32, PMP entries are 34 bits. Hence, the setup_pmp needed to accept u64. So, uinptr_t can not be used, as on 32 bits they are only 32 bit numbers. The internal API uses uintptr_t, but the exported API uses u64, so external code does not have to think about right shifts on base and size. Errors are detected: an error in base and size will result in a BIOS_EMERG print, but not a panic. Boots not bricks if possible. There are small changes to the internal API to reduce stack pressure: there's no need to have two pmpcfg_t on the stack when one will do. Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/include/arch/pmp.h M src/arch/riscv/payload.c M src/arch/riscv/pmp.c 3 files changed, 109 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/81090/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/81090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Gerrit-Change-Number: 81090 Gerrit-PatchSet: 9 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: vc/intel/fsp2: Drop superfluous Raptor Lake headers
by Felix Singer (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81117?usp=email to look at the new patch set (#3). Change subject: vc/intel/fsp2: Drop superfluous Raptor Lake headers ...................................................................... vc/intel/fsp2: Drop superfluous Raptor Lake headers The Raptor Lake FSP from the Intel FSP repo is already hooked up and thus these headers are superfluous. Remove them. Change-Id: Id8154f8309836d34a8c69b4e0b6a19e32af5227f Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/alderlake/Kconfig D src/vendorcode/intel/fsp/fsp2_0/raptorlake/FirmwareVersionInfoHob.h D src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h D src/vendorcode/intel/fsp/fsp2_0/raptorlake/MemInfoHob.h 6 files changed, 0 insertions(+), 8,897 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/81117/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id8154f8309836d34a8c69b4e0b6a19e32af5227f Gerrit-Change-Number: 81117 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: vc/intel/fsp2: Drop superfluous Raptor Lake headers
by Felix Singer (Code Review) 07 Mar '24

07 Mar '24

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81117?usp=email ) Change subject: vc/intel/fsp2: Drop superfluous Raptor Lake headers ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/81117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id8154f8309836d34a8c69b4e0b6a19e32af5227f Gerrit-Change-Number: 81117 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Mar 2024 18:06:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/alderlake: Drop superfluous default for ADL-N FSP headers
by Felix Singer (Code Review) 07 Mar '24

07 Mar '24

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81116?usp=email ) Change subject: soc/intel/alderlake: Drop superfluous default for ADL-N FSP headers ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/81116?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I143380a35618d51260be2400d334533434e8df21 Gerrit-Change-Number: 81116 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Mar 2024 18:03:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/alderlake: Add Raptor Lake System Agent Device IDs
by Angel Pons (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81115?usp=email ) Change subject: soc/intel/alderlake: Add Raptor Lake System Agent Device IDs ...................................................................... Patch Set 1: Code-Review+1 (6 comments) File src/soc/intel/alderlake/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/81115/comment/c1b47a95_16552346 : PS1, Line 87: { PCI_DID_INTEL_RPL_P_ID_1, "Raptorlake-H/H Refresh (6+8)" }, There's two platforms with ID 0xA706: - H 6P+8E - P 6P+8E Looks like the name should be `Raptorlake-H/P (6+8)` https://review.coreboot.org/c/coreboot/+/81115/comment/990224ff_4ab8b3cc : PS1, Line 88: { PCI_DID_INTEL_RPL_P_ID_2, "Raptorlake-H/H Refresh (4+8)" }, There's two platforms with ID 0xA707: - H 4P+8E - P 4P+8E Looks like the name should be `Raptorlake-H/P (4+8)` File src/soc/intel/alderlake/vr_config.c: https://review.coreboot.org/c/coreboot/+/81115/comment/2518de62_d1c9dc09 : PS1, Line 131: { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, For another patch: I think this table is missing an entry for `PCI_DID_INTEL_RPL_P_ID_1` RPL-P (28W), it only has the entry for `PCI_DID_INTEL_RPL_P_ID_1` RPL-H (45W). https://review.coreboot.org/c/coreboot/+/81115/comment/b2d5ed85_f8009782 : PS1, Line 195: { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, Same as above https://review.coreboot.org/c/coreboot/+/81115/comment/01818dcd_81aac476 : PS1, Line 259: { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, Same as above https://review.coreboot.org/c/coreboot/+/81115/comment/a7edc903_3ccb6752 : PS1, Line 323: { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, Same as above -- To view, visit https://review.coreboot.org/c/coreboot/+/81115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I805040c65852742f1bbc43b443e115bcb0a930aa Gerrit-Change-Number: 81115 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 07 Mar 2024 18:01:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/alderlake: Add Raptor Lake System Agent Device IDs
by Arthur Heymans (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Subrata Banik. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81115?usp=email ) Change subject: soc/intel/alderlake: Add Raptor Lake System Agent Device IDs ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I805040c65852742f1bbc43b443e115bcb0a930aa Gerrit-Change-Number: 81115 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 07 Mar 2024 16:54:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/alderlake: Add Raptor Lake System Agent Device IDs
by Lean Sheng Tan (Code Review) 07 Mar '24

07 Mar '24

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81115?usp=email ) Change subject: soc/intel/alderlake: Add Raptor Lake System Agent Device IDs ...................................................................... soc/intel/alderlake: Add Raptor Lake System Agent Device IDs Add System Agent IDs for Raptor Lake SKUs based on RPL Datasheet (Doc ID: 743844). Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I805040c65852742f1bbc43b443e115bcb0a930aa --- M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/vr_config.c M src/soc/intel/common/block/systemagent/systemagent.c 7 files changed, 35 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/81115/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index f980f4e..1ae09f0 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4285,6 +4285,9 @@ #define PCI_DID_INTEL_RPL_P_ID_3 0xa708 #define PCI_DID_INTEL_RPL_P_ID_4 0xa71b #define PCI_DID_INTEL_RPL_P_ID_5 0xa71c +#define PCI_DID_INTEL_RPL_P_ID_6 0xa709 +#define PCI_DID_INTEL_RPL_P_ID_7 0xa70a +#define PCI_DID_INTEL_RPL_P_ID_8 0xa716 #define PCI_DID_INTEL_LNL_M_ID 0x6400 /* Intel SMBUS device Ids */ diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 2a4f31a..cb07727 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -84,11 +84,14 @@ { PCI_DID_INTEL_RPL_HX_ID_6, "Raptorlake-HX (8+8)" }, { PCI_DID_INTEL_RPL_HX_ID_7, "Raptorlake-HX (6+8)" }, { PCI_DID_INTEL_RPL_HX_ID_8, "Raptorlake-HX (6+4)" }, - { PCI_DID_INTEL_RPL_P_ID_1, "Raptorlake-P" }, - { PCI_DID_INTEL_RPL_P_ID_2, "Raptorlake-P" }, - { PCI_DID_INTEL_RPL_P_ID_3, "Raptorlake-P" }, - { PCI_DID_INTEL_RPL_P_ID_4, "Raptorlake-P" }, - { PCI_DID_INTEL_RPL_P_ID_5, "Raptorlake-P" }, + { PCI_DID_INTEL_RPL_P_ID_1, "Raptorlake-H/H Refresh (6+8)" }, + { PCI_DID_INTEL_RPL_P_ID_2, "Raptorlake-H/H Refresh (4+8)" }, + { PCI_DID_INTEL_RPL_P_ID_3, "Raptorlake-U/U Refresh (2+8)" }, + { PCI_DID_INTEL_RPL_P_ID_4, "Raptorlake-U/U Refresh (2+4)" }, + { PCI_DID_INTEL_RPL_P_ID_5, "Raptorlake-U (1+4)" }, + { PCI_DID_INTEL_RPL_P_ID_6, "Raptorlake-PX (6+8)" }, + { PCI_DID_INTEL_RPL_P_ID_7, "Raptorlake-PX (4+8)" }, + { PCI_DID_INTEL_RPL_P_ID_8, "Raptorlake-H (4+4)" }, { PCI_DID_INTEL_RPL_S_ID_1, "Raptorlake-S (8+16)" }, { PCI_DID_INTEL_RPL_S_ID_2, "Raptorlake-S (8+0)" }, { PCI_DID_INTEL_RPL_S_ID_3, "Raptorlake-S (8+8)" }, diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 437d675..1620c10 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -176,6 +176,9 @@ { PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W }, { PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W }, { PCI_DID_INTEL_RPL_P_ID_5, RPL_P_282_242_142_15W_CORE, TDP_15W }, + { PCI_DID_INTEL_RPL_P_ID_6, RPL_P_682_642_482_45W_CORE, TDP_45W }, + { PCI_DID_INTEL_RPL_P_ID_7, RPL_P_682_642_482_45W_CORE, TDP_45W }, + { PCI_DID_INTEL_RPL_P_ID_8, RPL_P_682_642_482_45W_CORE, TDP_45W }, { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_35W_CORE, TDP_35W }, { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_65W_CORE, TDP_65W }, { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_95W_CORE, TDP_95W }, diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 2d25bb6..5b1a690 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -268,6 +268,9 @@ PCI_DID_INTEL_RPL_P_ID_3, PCI_DID_INTEL_RPL_P_ID_4, PCI_DID_INTEL_RPL_P_ID_5, + PCI_DID_INTEL_RPL_P_ID_6, + PCI_DID_INTEL_RPL_P_ID_7, + PCI_DID_INTEL_RPL_P_ID_8, }; const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT), diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index b432030..0790ec7 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -528,6 +528,9 @@ case PCI_DID_INTEL_RPL_P_ID_3: case PCI_DID_INTEL_RPL_P_ID_4: case PCI_DID_INTEL_RPL_P_ID_5: + case PCI_DID_INTEL_RPL_P_ID_6: + case PCI_DID_INTEL_RPL_P_ID_7: + case PCI_DID_INTEL_RPL_P_ID_8: tdp = get_cpu_tdp(); if (tdp == TDP_45W) return ICC_MAX_TDP_45W; diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 6718e89..c3584ba 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -134,6 +134,9 @@ { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, + { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, + { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, + { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, @@ -195,6 +198,9 @@ { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, + { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, + { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, + { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_ICC(240, 30) }, @@ -256,6 +262,9 @@ { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, @@ -317,6 +326,9 @@ { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, + { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, + { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, + { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 99c145d..b53814e3 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -535,6 +535,9 @@ PCI_DID_INTEL_RPL_P_ID_3, PCI_DID_INTEL_RPL_P_ID_4, PCI_DID_INTEL_RPL_P_ID_5, + PCI_DID_INTEL_RPL_P_ID_6, + PCI_DID_INTEL_RPL_P_ID_7, + PCI_DID_INTEL_RPL_P_ID_8, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/81115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I805040c65852742f1bbc43b443e115bcb0a930aa Gerrit-Change-Number: 81115 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/common/block: Add support for watchdog
by Marek Maślanka (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Jakub Czapiga, Michał Żygowski, Subrata Banik. Marek Maślanka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79909?usp=email ) Change subject: soc/intel/common/block: Add support for watchdog ...................................................................... Patch Set 15: (1 comment) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/79909/comment/37717f54_34e9e7a6 : PS14, Line 408: tcobase > > every usage of `tco_get_bar()` assumes it's already programmed, but in case if it isn't performed […] Yes, good point, and I've thought about it, but these functions are very specific, which doesn't fit any other usage, so I decided to check this condition in the caller. If you feel that this argument is not sufficient, let me know, I will add additional checks. -- To view, visit https://review.coreboot.org/c/coreboot/+/79909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1 Gerrit-Change-Number: 79909 Gerrit-PatchSet: 15 Gerrit-Owner: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Comment-Date: Thu, 07 Mar 2024 16:49:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marek Maślanka <mmaslanka(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: lib/device_tree: Add some FDT helper functions
by Maximilian Brune (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Jakub Czapiga, Julius Werner, Martin L Roth. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81081?usp=email ) Change subject: lib/device_tree: Add some FDT helper functions ...................................................................... Patch Set 6: (1 comment) This change is ready for review. Patchset: PS6: > Test failed with exception: Segmentation fault(11) I am lost why the test fails for jenkins, but if I do ``` make unit-tests COV=1 ``` on my local system it works fine (two different PCs). Any Ideas? -- To view, visit https://review.coreboot.org/c/coreboot/+/81081?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8 Gerrit-Change-Number: 81081 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Mar 2024 16:35:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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