coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/alderlake: select UDK_202111_BINDING for ADL-N
by Paul Menzel (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, V Sowmya. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80274?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/alderlake: select UDK_202111_BINDING for ADL-N ...................................................................... Patch Set 6: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80274/comment/ae4688e8_52c83bf1 : PS6, Line 10: This patch select edk2-stable202111 for ADL-N and add CFLAGS This patch select*s* … and add*s* Better: Select … and add … https://review.coreboot.org/c/coreboot/+/80274/comment/b641af7f_2a8c3a22 : PS6, Line 11: while during https://review.coreboot.org/c/coreboot/+/80274/comment/e6862670_2a53ed33 : PS6, Line 11: pltform platform https://review.coreboot.org/c/coreboot/+/80274/comment/ecff5a4d_5081466f : PS6, Line 11: One space. https://review.coreboot.org/c/coreboot/+/80274/comment/ba77fcf6_0ca0c6b5 : PS6, Line 12: compilation. Please paste the compiler error. -- To view, visit https://review.coreboot.org/c/coreboot/+/80274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If277ede4307515035389cd0e9d34c15cc80f278c Gerrit-Change-Number: 80274 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 07 Mar 2024 16:01:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/common/block: Add support for watchdog
by Subrata Banik (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Jakub Czapiga, Marek Maślanka, Michał Żygowski. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79909?usp=email ) Change subject: soc/intel/common/block: Add support for watchdog ...................................................................... Patch Set 15: (2 comments) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/79909/comment/dc51913e_220f73d9 : PS13, Line 396: rightmost_bit_offset > thanks, the `__builtin_ctzll` is doing what I needed. Acknowledged File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/79909/comment/0b49d1c7_9f422631 : PS14, Line 408: tcobase > every usage of `tco_get_bar()` assumes it's already programmed, but in case if it isn't performed yet it doesn't hurt to go forward what if in future we have some other caller for fill_wdat_timeout_entry() function do you expect that every caller will do the needful check of `tcobar` before calling to fill_wdat_timeout_entry()? -- To view, visit https://review.coreboot.org/c/coreboot/+/79909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1 Gerrit-Change-Number: 79909 Gerrit-PatchSet: 15 Gerrit-Owner: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Comment-Date: Thu, 07 Mar 2024 15:24:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marek Maślanka <mmaslanka(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: Docs: Replace Recommonmark with MyST Parser
by Nicholas Chin (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Angel Pons, Jason Glenesk, Martin L Roth. Hello Angel Pons, Daniel Maslowski, Felix Singer, Jason Glenesk, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73158?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Docs: Replace Recommonmark with MyST Parser ...................................................................... Docs: Replace Recommonmark with MyST Parser Recommonmark has been deprecated since 2021 [1] and the last release was over 3 years ago [2]. As per their announcement, Markedly Structured Text (MyST) Parser [3] is the recommended replacement. For the most part, the existing documentation is compatible with MyST, as both parsers are built around the CommonMark flavor of Markdown. The main difference that affects coreboot is how the Sphinx toctree is generated. Recommonmark has a feature called auto_toc_tree, which converts single level lists of references into a toctree: * [Part 1: Starting from scratch](part1.md) * [Part 2: Submitting a patch to coreboot.org](part2.md) * [Part 3: Writing unit tests](part3.md) * [Managing local additions](managing_local_additions.md) * [Flashing firmware](flashing_firmware/index.md) MyST Parser does not provide a replacement for this feature, meaning the toctree must be defined manually. This is done using MyST's syntax for Sphinx directives: ```{toctree} :maxdepth: 1 Part 1: Starting from scratch <part1.md> Part 2: Submitting a patch to coreboot.org <part2.md> Part 3: Writing unit tests <part3.md> Managing local additions <managing_local_additions.md> Flashing firmware <flashing_firmware/index.md> ``` Internally, auto_toc_tree essentially converts lists of references into the Sphinx toctree structure that the MyST syntax above more directly represents. The toctrees were converted to the MyST syntax using the following command and Python script: `find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py` ``` import re import sys in_list = False f = open(sys.argv[1]) lines = f.readlines() f.close() with open(sys.argv[1], "w") as f: for line in lines: match = re.match(r"^[-*+] \[(.*)\]$(.*)$$", line) if match is not None: if not in_list: in_list = True f.write("```{toctree}\n") f.write(":maxdepth: 1\n\n") f.write(match.group(1) + " <" + match.group(2) + ">\n") else: if in_list: f.write("```\n") f.write(line) in_list = False if in_list: f.write("```\n") ``` While this does add a little more work for creating the toctree, this does give more control over exactly what goes into the toctree. For instance, lists of links to external resources currently end up in the toctree, but we may want to limit it to pages within coreboot. This change does break rendering and navigation of the documentation in applications that can render Markdown, such as Okular, Gitiles, or the GitHub mirror. Assuming the docs are mainly intended to be viewed after being rendered to doc.coreboot.org, this is probably not an issue in practice. Another difference is that MyST natively supports Markdown tables, whereas with Recommonmark, tables had to be written in embedded rST [6]. However, MyST also supports embedded rST, so the existing tables can be easily converted as the syntax is nearly identical. These were converted using `find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"` Makefile.sphinx and conf.py were regenerated from scratch by running `sphinx-quickstart` using the updated version of Sphinx, which removes a lot of old commented out boilerplate. Any relevant changes coreboot had made on top of the previous autogenerated versions of these files were ported over to the newly generated file. From some initial testing the generated webpages appear and function identically to the existing documentation built with Recommonmark. [1] https://github.com/readthedocs/recommonmark/issues/221 [2] https://pypi.org/project/recommonmark/ [3] https://myst-parser.readthedocs.io/en/latest/ [4] https://doc.coreboot.org/getting_started/writing_documentation.html Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/Makefile.sphinx M Documentation/acpi/index.md M Documentation/acronyms.md M Documentation/arch/index.md M Documentation/arch/x86/index.md M Documentation/community/index.md M Documentation/conf.py M Documentation/contributing/index.md M Documentation/drivers/index.md M Documentation/drivers/smmstore.md M Documentation/drivers/smmstorev2.md M Documentation/external_docs.md M Documentation/getting_started/build_system.md M Documentation/getting_started/gpio.md M Documentation/getting_started/index.md M Documentation/getting_started/kconfig.md M Documentation/gfx/display-panel.md M Documentation/index.md M Documentation/infrastructure/builders.md M Documentation/infrastructure/index.md M Documentation/lib/index.md M Documentation/lib/payloads/index.md M Documentation/mainboard/acer/g43t-am3.md M Documentation/mainboard/amd/pademelon/pademelon.md M Documentation/mainboard/asrock/h110m-dvs.md M Documentation/mainboard/asrock/h77pro4-m.md M Documentation/mainboard/asrock/h81m-hds.md M Documentation/mainboard/asus/a88xm-e.md M Documentation/mainboard/asus/f2a85-m.md M Documentation/mainboard/asus/p2b-ls.md M Documentation/mainboard/asus/p3b-f.md M Documentation/mainboard/asus/p5q.md M Documentation/mainboard/asus/p8c_ws.md M Documentation/mainboard/asus/p8h61-m_lx.md M Documentation/mainboard/asus/p8h61-m_pro.md M Documentation/mainboard/asus/p8h77-v.md M Documentation/mainboard/asus/p8z77-m.md M Documentation/mainboard/asus/p8z77-m_pro.md M Documentation/mainboard/asus/p8z77-v.md M Documentation/mainboard/asus/wifigo_v1.md M Documentation/mainboard/cavium/cn8100_sff_evb.md M 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Documentation/mainboard/lenovo/codenames.md M Documentation/mainboard/lenovo/ivb_internal_flashing.md M Documentation/mainboard/lenovo/montevina_series.md M Documentation/mainboard/lenovo/t410.md M Documentation/mainboard/libretrend/lt1000.md M Documentation/mainboard/msi/ms7707/ms7707.md M Documentation/mainboard/ocp/deltalake.md M Documentation/mainboard/ocp/tiogapass.md M Documentation/mainboard/opencellular/elgon.md M Documentation/mainboard/pcengines/apu1.md M Documentation/mainboard/pcengines/apu2.md M Documentation/mainboard/portwell/pq7-m107.md M Documentation/mainboard/prodrive/hermes.md M Documentation/mainboard/protectli/fw2b_fw4b.md M Documentation/mainboard/protectli/fw6.md M Documentation/mainboard/protectli/vp2420.md M Documentation/mainboard/protectli/vp46xx.md M Documentation/mainboard/purism/librem_14.md M Documentation/mainboard/purism/librem_mini.md M Documentation/mainboard/starlabs/labtop_cml.md M Documentation/mainboard/starlabs/labtop_kbl.md M Documentation/mainboard/starlabs/lite_glk.md M Documentation/mainboard/starlabs/lite_glkr.md M Documentation/mainboard/starlabs/starbook_adl.md M Documentation/mainboard/starlabs/starbook_tgl.md M Documentation/mainboard/supermicro/x10slm-f.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md M Documentation/mainboard/supermicro/x9sae.md M Documentation/mainboard/system76/addw1.md M Documentation/mainboard/system76/addw2.md M Documentation/mainboard/system76/addw3.md M Documentation/mainboard/system76/bonw14.md M Documentation/mainboard/system76/bonw15.md M Documentation/mainboard/system76/darp6.md M Documentation/mainboard/system76/darp7.md M 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Documentation/mainboard/ti/beaglebone-black.md M Documentation/mainboard/up/squared/index.md M Documentation/northbridge/index.md M Documentation/northbridge/intel/haswell/index.md M Documentation/northbridge/intel/haswell/known-issues.md M Documentation/northbridge/intel/index.md M Documentation/northbridge/intel/sandybridge/index.md M Documentation/northbridge/intel/sandybridge/nri.md M Documentation/northbridge/intel/sandybridge/nri_features.md M Documentation/northbridge/intel/sandybridge/nri_freq.md M Documentation/northbridge/intel/sandybridge/nri_read.md M Documentation/northbridge/intel/sandybridge/nri_registers.md M Documentation/releases/boards_supported_on_branches.md M Documentation/releases/checklist.md M Documentation/releases/coreboot-4.17-relnotes.md M Documentation/releases/coreboot-4.19-relnotes.md M Documentation/releases/coreboot-4.20.1-relnotes.md M Documentation/releases/coreboot-4.21-relnotes.md M Documentation/releases/coreboot-4.22-relnotes.md M Documentation/releases/index.md M Documentation/releases/templates.md M Documentation/security/index.md M Documentation/security/memory_clearing.md M Documentation/security/vboot/index.md M Documentation/soc/amd/index.md M Documentation/soc/amd/psp_integration.md M Documentation/soc/cavium/cn81xx/index.md M Documentation/soc/cavium/index.md M Documentation/soc/index.md M Documentation/soc/intel/broadwell/index.md M Documentation/soc/intel/code_development_model/code_development_model.md M Documentation/soc/intel/fit.md M Documentation/soc/intel/fsp/index.md M Documentation/soc/intel/fsp/ppi/mp_service_ppi.md M Documentation/soc/intel/fsp/ppi/ppi.md M Documentation/soc/intel/index.md M Documentation/soc/intel/mp_init/mp_init.md M Documentation/soc/intel/xeon_sp/index.md M Documentation/soc/qualcomm/index.md M Documentation/superio/index.md M Documentation/superio/nuvoton/npcd378.md M Documentation/technotes/asan.md M Documentation/technotes/console.md M Documentation/technotes/index.md M Documentation/tutorial/flashing_firmware/index.md M Documentation/tutorial/index.md M Documentation/tutorial/part3.md M Documentation/util.md M Documentation/util/cbfstool/index.md M Documentation/util/ifdtool/index.md M Documentation/util/ifdtool/layout.md M Documentation/vendorcode/cavium/index.md M Documentation/vendorcode/eltan/index.md M Documentation/vendorcode/index.md 178 files changed, 1,260 insertions(+), 1,020 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/73158/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/73158?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804 Gerrit-Change-Number: 73158 Gerrit-PatchSet: 10 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP
by Shuo Liu (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81098?usp=email ) Change subject: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/spr/chip.c: https://review.coreboot.org/c/coreboot/+/81098/comment/b8e9d241_525eeee3 : PS4, Line 130: attach_iio_stacks > Does it need to run after fsp_silicon_init() or can it be run before that? Put it after fsp_silicon_init() is a safe implementation to make sure all stacks, include IOAT, are usable after that, although in some implementation, it can be pull in to before fsp_silicon_init() (and after fsp_memory_init()). -- To view, visit https://review.coreboot.org/c/coreboot/+/81098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Gerrit-Change-Number: 81098 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 07 Mar 2024 13:38:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP
by Patrick Rudolph (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81098?usp=email ) Change subject: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/spr/chip.c: https://review.coreboot.org/c/coreboot/+/81098/comment/0c4d3329_6d217530 : PS4, Line 130: attach_iio_stacks > Done Does it need to run after fsp_silicon_init() or can it be run before that? -- To view, visit https://review.coreboot.org/c/coreboot/+/81098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Gerrit-Change-Number: 81098 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 07 Mar 2024 13:34:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/spr: Fix IOAT resources
by Lean Sheng Tan (Code Review) 07 Mar '24

07 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80793?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp/spr: Fix IOAT resources ...................................................................... soc/intel/xeon_sp/spr: Fix IOAT resources Do not generate empty mem32 resources for CPMx or HQMx stacks. Switch existing arguments to make sure that base is bigger than limit to indicate that the resource is invalid. Change-Id: I679563e97c33c7ee35d402674972e55f521eafa8 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80793 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/spr/ioat.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified Shuo Liu: Looks good to me, but someone else must approve diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index 5528efa..bde7eba 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -101,7 +101,7 @@ mem64_limit = mem64_base + CPM_MMIO_SIZE - 1; bus_base = sr->BusBase + CPM_BUS_OFFSET; bus_limit = bus_base + CPM_RESERVED_BUS; - create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit, + create_ioat_domain(path, bus, bus_base, bus_limit, -1, 0, mem64_base, mem64_limit, DOMAIN_TYPE_CPM0); /* HQM0 */ @@ -109,7 +109,7 @@ mem64_limit = mem64_base + HQM_MMIO_SIZE - 1; bus_base = sr->BusBase + HQM_BUS_OFFSET; bus_limit = bus_base + HQM_RESERVED_BUS; - create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit, + create_ioat_domain(path, bus, bus_base, bus_limit, -1, 0, mem64_base, mem64_limit, DOMAIN_TYPE_HQM0); /* CPM1 (optional) */ @@ -118,7 +118,7 @@ bus_base = sr->BusBase + CPM1_BUS_OFFSET; bus_limit = bus_base + CPM_RESERVED_BUS; if (bus_limit <= sr->BusLimit) - create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit, + create_ioat_domain(path, bus, bus_base, bus_limit, -1, 0, mem64_base, mem64_limit, DOMAIN_TYPE_CPM1); /* HQM1 (optional) */ @@ -127,7 +127,7 @@ bus_base = sr->BusBase + HQM1_BUS_OFFSET; bus_limit = bus_base + HQM_RESERVED_BUS; if (bus_limit <= sr->BusLimit) - create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit, + create_ioat_domain(path, bus, bus_base, bus_limit, -1, 0, mem64_base, mem64_limit, DOMAIN_TYPE_HQM1); /* DINO */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I679563e97c33c7ee35d402674972e55f521eafa8 Gerrit-Change-Number: 80793 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP
by Shuo Liu (Code Review) 07 Mar '24

07 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81098?usp=email ) Change subject: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/spr/chip.c: https://review.coreboot.org/c/coreboot/+/81098/comment/8d9dcb03_b18f6d6c : PS4, Line 130: attach_iio_stacks > I suppose this location should be functionally equal to in chip_enable_dev, but it looks more straig […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Gerrit-Change-Number: 81098 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 07 Mar 2024 13:30:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Share numa.c among Xeon-SP platforms
by Lean Sheng Tan (Code Review) 07 Mar '24

07 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81042?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Share numa.c among Xeon-SP platforms ...................................................................... soc/intel/xeon_sp: Share numa.c among Xeon-SP platforms NUMA will be supported by SPR and future generations. TEST=intel/archercity CRB Change-Id: I0d494f8e560059d9c8d5338cef9a6ffe34e59e26 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81042 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.mk R src/soc/intel/xeon_sp/numa.c M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/intel/xeon_sp/spr/Makefile.mk 5 files changed, 6 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 59335a1..52aaec17 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -106,4 +106,7 @@ config HAVE_IOAT_DOMAINS bool +config SOC_INTEL_HAS_CXL + bool + endif ## SOC_INTEL_XEON_SP diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index a732c78..5891544 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -13,7 +13,7 @@ ramstage-y += memmap.c pch.c lockdown.c finalize.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c -ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c +ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c numa.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c smm-y += smihandler.c pmutil.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/spr/numa.c b/src/soc/intel/xeon_sp/numa.c similarity index 100% rename from src/soc/intel/xeon_sp/spr/numa.c rename to src/soc/intel/xeon_sp/numa.c diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index acc5e4a..3c3c45a 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -15,6 +15,7 @@ select HAVE_IOAT_DOMAINS select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND select UDK_202005_BINDING + select SOC_INTEL_HAS_CXL help Intel Sapphire Rapids-SP support @@ -114,9 +115,6 @@ config SOC_INTEL_HAS_NCMEM def_bool y -config SOC_INTEL_HAS_CXL - def_bool y - config SOC_INTEL_PCIE_64BIT_ALLOC def_bool y diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk index 659e366..163b5ea 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.mk +++ b/src/soc/intel/xeon_sp/spr/Makefile.mk @@ -12,7 +12,7 @@ romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c -ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c numa.c reset.c +ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c reset.c ramstage-y += crashlog.c ioat.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c -- To view, visit https://review.coreboot.org/c/coreboot/+/81042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d494f8e560059d9c8d5338cef9a6ffe34e59e26 Gerrit-Change-Number: 81042 Gerrit-PatchSet: 10 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Unshare UDK binding among Xeon-SP platforms
by Lean Sheng Tan (Code Review) 07 Mar '24

07 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81041?usp=email ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Unshare UDK binding among Xeon-SP platforms ...................................................................... soc/intel/xeon_sp: Unshare UDK binding among Xeon-SP platforms TEST=intel/archercity CRB Change-Id: I285549daad87fe1ad6e8a94853e0a92cd5930e04 Signed-off-by: Li, Jincheng <jincheng.li(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81041 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/spr/Kconfig 4 files changed, 3 insertions(+), 1 deletion(-) Approvals: Lean Sheng Tan: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 18474ec..59335a1 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -47,7 +47,6 @@ bool default y select PLATFORM_USES_FSP2_0 - select UDK_202005_BINDING select POSTCAR_STAGE config MAX_SOCKET diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index b9d63d3..51e545f 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -8,6 +8,7 @@ select NO_FSP_TEMP_RAM_EXIT select HAVE_INTEL_FSP_REPO select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND + select UDK_202005_BINDING help Intel Cooper Lake-SP support diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 5d84387..4a9e683 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -5,6 +5,7 @@ select XEON_SP_COMMON_BASE select PLATFORM_USES_FSP2_0 select NO_FSP_TEMP_RAM_EXIT + select UDK_202005_BINDING help Intel Skylake-SP support diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index ace5c07..acc5e4a 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -14,6 +14,7 @@ select XEON_SP_COMMON_BASE select HAVE_IOAT_DOMAINS select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND + select UDK_202005_BINDING help Intel Sapphire Rapids-SP support -- To view, visit https://review.coreboot.org/c/coreboot/+/81041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I285549daad87fe1ad6e8a94853e0a92cd5930e04 Gerrit-Change-Number: 81041 Gerrit-PatchSet: 9 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add memory type check utils
by Lean Sheng Tan (Code Review) 07 Mar '24

07 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80632?usp=email ) Change subject: soc/intel/xeon_sp: Add memory type check utils ...................................................................... soc/intel/xeon_sp: Add memory type check utils FSP memory type representations change across Xeon-SP SoCs. This patch adds type check utils to abstract the differences. TEST=intel/archercity CRB Change-Id: I2f5f3c0f16dc50bc739146e46afce2e5fbf4f62c Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80632 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/uncore_acpi.c 5 files changed, 61 insertions(+), 8 deletions(-) Approvals: Lean Sheng Tan: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 5dbac98..2d6005b 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -121,3 +121,18 @@ } } } + +bool is_memtype_reserved(uint16_t mem_type) +{ + return !!(mem_type & MEM_TYPE_RESERVED); +} + +bool is_memtype_non_volatile(uint16_t mem_type) +{ + return !(mem_type & MEMTYPE_VOLATILE_MASK); +} + +bool is_memtype_processor_attached(uint16_t mem_type) +{ + return true; +} diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index dd84f0c..a7d5dac 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -19,6 +19,10 @@ void set_bios_init_completion(void); uint8_t soc_get_iio_ioapicid(int socket, int stack); +bool is_memtype_non_volatile(uint16_t mem_type); +bool is_memtype_reserved(uint16_t mem_type); +bool is_memtype_processor_attached(uint16_t mem_type); + struct iiostack_resource { uint8_t no_of_stacks; STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 12d30d4..38d834f 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -195,3 +195,18 @@ } return ioapic_id; } + +bool is_memtype_reserved(uint16_t mem_type) +{ + return !!(mem_type & MEM_TYPE_RESERVED); +} + +bool is_memtype_non_volatile(uint16_t mem_type) +{ + return !(mem_type & MEMTYPE_VOLATILE_MASK); +} + +bool is_memtype_processor_attached(uint16_t mem_type) +{ + return true; +} diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index b8f06ac..41b256c 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -167,3 +167,24 @@ cmos_write(new_mrc_status, CMOS_OFFSET_MRC_STATUS); } + +bool is_memtype_reserved(uint16_t mem_type) +{ + return !!(mem_type & MEM_TYPE_RESERVED); +} + +bool is_memtype_non_volatile(uint16_t mem_type) +{ + return !(mem_type & MEMTYPE_VOLATILE_MASK); +} + +bool is_memtype_processor_attached(uint16_t mem_type) +{ + /* + * Refer to the definition of MEM_TYPE enum type in + * vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h, + * values less than MemTypeCxlAccVolatileMem represents + * processor attached memory + */ + return (mem_type < MemTypeCxlAccVolatileMem); +} diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index b4856120..b7c6640 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -99,19 +99,17 @@ "ElementSize: 0x%x, type: %d, reserved: %d\n", e, addr, mem_element->BaseAddress, size, mem_element->ElementSize, mem_element->Type, - (mem_element->Type & MEM_TYPE_RESERVED)); + is_memtype_reserved(mem_element->Type)); assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); /* skip reserved memory region */ - if (mem_element->Type & MEM_TYPE_RESERVED) + if (is_memtype_reserved(mem_element->Type)) continue; -#if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP) - /* Skip all non processor attached memory regions */ - /* In other words, skip all the types >= MemTypeCxlAccVolatileMem */ - if (mem_element->Type >= MemTypeCxlAccVolatileMem) + /* skip all non processor attached memory regions */ + if (CONFIG(SOC_INTEL_HAS_CXL) && + (!is_memtype_processor_attached(mem_element->Type))) continue; -#endif /* skip if this address is already added */ bool skip = false; @@ -134,7 +132,7 @@ srat_mem[mmap_index].length_high = (uint32_t)(size >> 32); srat_mem[mmap_index].proximity_domain = mem_element->SocketId; srat_mem[mmap_index].flags = ACPI_SRAT_MEMORY_ENABLED; - if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) + if (is_memtype_non_volatile(mem_element->Type)) srat_mem[mmap_index].flags |= ACPI_SRAT_MEMORY_NONVOLATILE; ++mmap_index; } -- To view, visit https://review.coreboot.org/c/coreboot/+/80632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f5f3c0f16dc50bc739146e46afce2e5fbf4f62c Gerrit-Change-Number: 80632 Gerrit-PatchSet: 14 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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