coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: vc/amd/opensil/stub/mpio: change mpio_engine_type prefix to IFTYPE
by Felix Held (Code Review) 20 Mar '24

20 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81346?usp=email ) Change subject: vc/amd/opensil/stub/mpio: change mpio_engine_type prefix to IFTYPE ...................................................................... vc/amd/opensil/stub/mpio: change mpio_engine_type prefix to IFTYPE Change the prefix of the elements of the mpio_engine_type enum from ENGINE_ to IFTYPE_. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Matt DeVillier <matt.devillier(a)gmail.com> Change-Id: If81c5ea01ba147b71b423004a2199b348ffac99a Reviewed-on: https://review.coreboot.org/c/coreboot/+/81346 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/vendorcode/amd/opensil/stub/mpio/chip.h 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified Varshit Pandya: Looks good to me, approved diff --git a/src/vendorcode/amd/opensil/stub/mpio/chip.h b/src/vendorcode/amd/opensil/stub/mpio/chip.h index 53d22a0..f2fb5da 100644 --- a/src/vendorcode/amd/opensil/stub/mpio/chip.h +++ b/src/vendorcode/amd/opensil/stub/mpio/chip.h @@ -3,8 +3,8 @@ #include <types.h> enum mpio_engine_type { - ENGINE_PCIE, - ENGINE_SATA, + IFTYPE_PCIE, + IFTYPE_SATA, }; /* Sync with PCIE_HOTPLUG_TYPE */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81346?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If81c5ea01ba147b71b423004a2199b348ffac99a Gerrit-Change-Number: 81346 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: lib/ramdetect: Limit probe size to avoid uintptr_t overflow
by Alper Nebi Yasak (Code Review) 20 Mar '24

20 Mar '24

Alper Nebi Yasak has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/81366?usp=email ) Change subject: lib/ramdetect: Limit probe size to avoid uintptr_t overflow ...................................................................... lib/ramdetect: Limit probe size to avoid uintptr_t overflow The probe_mb() function used in DRAM size detection and its variants used for QEMU mainboards use the following address calculation which can overflow on 32-bit architectures: uintptr_t addr = dram_start + (size * MiB) - sizeof(uint32_t); This can be observed on 32-bit RISC-V QEMU virtual machines where DRAM starts at 2 GiB. The process starts bisecting RAM with an initial size of 2 GiB (half of uintptr_t maximum) which makes the probed address just below 4 GiB due to the last term. If we have less than 2 GiB of DRAM, that probe fails and everything goes fine. Otherwise, following iterations overflow and probe the [1 GiB, 2 GiB) address range mistaking it for [3 GiB, 4 GiB) of DRAM. Somehow all of those succeed and we get a wrong result of 4095 MiB. Make sure we don't pass sizes to probe_mb() that will result in these overflows. We could check for overflow in the calculation instead, but we already have other similar checks in probe_ramsize() and the primary user of this function (cbmem_top()) eventually returns uintptr_t anyway. Change-Id: I65d0e97fff8708a034d1fd82fda32f0aecfb3382 Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> --- M src/lib/ramdetect.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/81366/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81366?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65d0e97fff8708a034d1fd82fda32f0aecfb3382 Gerrit-Change-Number: 81366 Gerrit-PatchSet: 2 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: lib/ramdetect: Limit probe size to avoid uintptr_t overflow
by Alper Nebi Yasak (Code Review) 20 Mar '24

20 Mar '24

Alper Nebi Yasak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81366?usp=email ) Change subject: lib/ramdetect: Limit probe size to avoid uintptr_t overflow ...................................................................... lib/ramdetect: Limit probe size to avoid uintptr_t overflow The probe_mb() function used in DRAM size detection and its variants used for QEMU mainboards use the following address calculation which can overflow on 32-bit architectures: uintptr_t addr = dram_start + (size * MiB) - sizeof(uint32_t); This can be observed on 32-bit RISC-V QEMU virtual machines where DRAM starts at 2 GiB. The process starts bisecting RAM with an initial size of 2 GiB (half of uintptr_t maximum) which makes the probed address just below 4 GiB due to the last term. If we have less than 2 GiB of DRAM, that probe fails and everything goes fine. Otherwise, following iterations overflow and probe the [1 GiB, 2 GiB) address range mistaking it for [3 GiB, 4 GiB) of DRAM. Somehow all of those succeed and we get a wrong result of 4095 MiB. Make sure we don't pass sizes to probe_mb() that will result in these overflows. We could check for overflow in the calculation instead, but we already have other similar checks in probe_ramsize() and the primary user of this function (cbmem_top()) eventually returns uintptr_t anyway. Change-Id: I65d0e97fff8708a034d1fd82fda32f0aecfb3382 Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> --- M src/lib/ramdetect.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/81366/1 diff --git a/src/lib/ramdetect.c b/src/lib/ramdetect.c index cef3d57..6301e12 100644 --- a/src/lib/ramdetect.c +++ b/src/lib/ramdetect.c @@ -39,13 +39,14 @@ ssize_t i; size_t msb = 0; size_t discovered = 0; + size_t probe_safe = MIN(probe_size, (UINTPTR_MAX - dram_start) / MiB); static size_t saved_result; if (saved_result) return saved_result; /* Find the MSB + 1. */ - size_t tmp = probe_size; + size_t tmp = probe_safe; do { msb++; } while (tmp >>= 1); @@ -55,7 +56,7 @@ /* Compact binary search. */ for (i = msb; i >= 0; i--) { - if ((discovered | (1ULL << i)) > probe_size) + if ((discovered | (1ULL << i)) > probe_safe) continue; if (probe_mb(dram_start, (discovered | (1ULL << i)))) discovered |= (1ULL << i); -- To view, visit https://review.coreboot.org/c/coreboot/+/81366?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65d0e97fff8708a034d1fd82fda32f0aecfb3382 Gerrit-Change-Number: 81366 Gerrit-PatchSet: 1 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mainboard/qemu-riscv: Further limit DRAM size for safe probing
by Alper Nebi Yasak (Code Review) 20 Mar '24

20 Mar '24

Alper Nebi Yasak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81365?usp=email ) Change subject: mainboard/qemu-riscv: Further limit DRAM size for safe probing ...................................................................... mainboard/qemu-riscv: Further limit DRAM size for safe probing On QEMU 64-bit RISC-V virtual machines, the PCIe MMIO base is shortly after the top of DRAM, aligned to 16 GiB. Probing DRAM can't distinguish this MMIO range from actual RAM, so commit 8e365396d427 ("riscv/mb/qemu: fix DRAM probing") reduces the default DRAM probe size to 16 GiB on the qemu-riscv mainboards to avoid it entirely. However, DRAM starts at 2 GiB on these VMs so we can end up probing addresses up to 18 GiB. In particular, making 14 GiB of DRAM available to the VM means top of RAM is at 16GiB with the MMIO range immediately after it, which still triggers this confusion. Decrease the 64-bit limit further by 2 GiB to account for the DRAM start address. The MMIO base is fixed at 12 GiB for 32-bit RISC-V VMs, so also limit to 10 GiB there, although things are further limited by 32-bit uintptr_t on those. Fixes: 8e365396d427 ("riscv/mb/qemu: fix DRAM probing") Change-Id: If95d80054dcd8a6bd2381066d1b7c5eaebd46d65 Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> --- M src/mainboard/emulation/qemu-riscv/Kconfig 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/81365/1 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 94f9e56..9d56c9c 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -70,10 +70,13 @@ config DRAM_SIZE_MB int - default 16383 + default 14335 if ARCH_RISCV_RV64 + default 10239 if ARCH_RISCV_RV32 help - Qemu maps MMIO at ALIGN_UP(top_of_mem, 16 * GiB) - To avoid confusing the dram probing algorithm, avoid large dram sizes (16G - 1m) + QEMU maps MMIO at ALIGN_UP(top_of_mem, 16 * GiB) on RV64. + To avoid confusing the DRAM probing algorithm, avoid large DRAM sizes. + DRAM start is at 2G, so we can safely probe up to 16G - 1M - 2G of RAM. + On RV32, MMIO is at 12 GiB, so we have to limit to 12G - 1M - 2G. config OPENSBI_PLATFORM string -- To view, visit https://review.coreboot.org/c/coreboot/+/81365?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If95d80054dcd8a6bd2381066d1b7c5eaebd46d65 Gerrit-Change-Number: 81365 Gerrit-PatchSet: 1 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/alderlake: select UDK_202111_BINDING for ADL-N
by V Sowmya (Code Review) 20 Mar '24

20 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Ronak Kanabar, Subrata Banik. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80274?usp=email ) Change subject: soc/intel/alderlake: select UDK_202111_BINDING for ADL-N ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If277ede4307515035389cd0e9d34c15cc80f278c Gerrit-Change-Number: 80274 Gerrit-PatchSet: 8 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Wed, 20 Mar 2024 18:17:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brya: Create a tivviks variant
by V Sowmya (Code Review) 20 Mar '24

20 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81262?usp=email ) Change subject: mb/google/brya: Create a tivviks variant ...................................................................... Patch Set 2: (4 comments) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/81262/comment/c77a64e4_0ab16aa3 : PS1, Line 463: select SOC_INTEL_TWINLAKE > Acknowledged Done. https://review.coreboot.org/c/coreboot/+/81262/comment/c1a98ab7_ac01df37 : PS1, Line 464: select BOARD_ROMSIZE_KB_32768 : select DRIVERS_GENERIC_GPIO_KEYS : select DRIVERS_GENESYSLOGIC_GL9750 : select DRIVERS_I2C_SX9324 : select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER : select DRIVERS_INTEL_MIPI_CAMERA : select HAVE_WWAN_POWER_SEQUENCE : select INTEL_GMA_HAVE_VBT > why not something like this […] I initially tried it (https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/…) but it resulted in recursive dependency issue so reverted it back. https://review.coreboot.org/c/coreboot/+/81262/comment/6179a016_4b7a3f8c : PS1, Line 581: BOARD_GOOGLE_TIVVIKS > Acknowledged Done. https://review.coreboot.org/c/coreboot/+/81262/comment/e4588ab9_89a00198 : PS1, Line 665: BOARD_GOOGLE_TIVVIKS > Acknowledged Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/81262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia833a1dad45e13cd271506ade364b116c5880982 Gerrit-Change-Number: 81262 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 20 Mar 2024 18:04:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: V Sowmya <v.sowmya(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brya: Create a tivviks variant
by V Sowmya (Code Review) 20 Mar '24

20 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, V Sowmya. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81262?usp=email to look at the new patch set (#2). Change subject: mb/google/brya: Create a tivviks variant ...................................................................... mb/google/brya: Create a tivviks variant This patch creates a new tivviks variant, which is a Twinlake platform. This variant uses Nivviks board mounted with the Twinlake SOC and hence the plan is to reuse the existing nivviks code. BUG=b:327550938 TEST= Genearte the Tivviks firmware builds and verify with boot check. Change-Id: Ia833a1dad45e13cd271506ade364b116c5880982 Signed-off-by: Sowmya V <v.sowmya(a)intel.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/81262/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia833a1dad45e13cd271506ade364b116c5880982 Gerrit-Change-Number: 81262 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Enable x86_64 support
by Patrick Rudolph (Code Review) 20 Mar '24

20 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Nico Huber, Ray Ni, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81280?usp=email ) Change subject: soc/intel/xeon_sp/spr: Enable x86_64 support ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/xeon_sp/uncore_acpi.c: https://review.coreboot.org/c/coreboot/+/81280/comment/7ae92eb0_d9a4d6f7 : PS1, Line 473: } > That seems to be the most common use case. I was just surprised to […] Dropped RMRR entry. -- To view, visit https://review.coreboot.org/c/coreboot/+/81280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65 Gerrit-Change-Number: 81280 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 20 Mar 2024 17:15:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Enable x86_64 support
by Patrick Rudolph (Code Review) 20 Mar '24

20 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Nico Huber, Ray Ni, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81280?usp=email ) Change subject: soc/intel/xeon_sp/spr: Enable x86_64 support ...................................................................... Patch Set 3: (2 comments) File src/soc/intel/xeon_sp/uncore_acpi.c: https://review.coreboot.org/c/coreboot/+/81280/comment/842e726a_cf176b2e : PS1, Line 23: #include <stddef.h> > alphabetical order. Done https://review.coreboot.org/c/coreboot/+/81280/comment/9929fef8_8ca81ff5 : PS1, Line 459: l > Shouldn't we just be using PRIxPTR ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65 Gerrit-Change-Number: 81280 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 20 Mar 2024 17:14:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Enable x86_64 support
by Patrick Rudolph (Code Review) 20 Mar '24

20 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Ray Ni, Shuo Liu, Tim Chu. Hello Arthur Heymans, Arthur Heymans, Christian Walter, Johnny Lin, Jérémy Compostella, Lean Sheng Tan, Nico Huber, Ray Ni, Shuo Liu, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81280?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Code-Review+1 by Shuo Liu, Code-Review+2 by Arthur Heymans Change subject: soc/intel/xeon_sp/spr: Enable x86_64 support ...................................................................... soc/intel/xeon_sp/spr: Enable x86_64 support Fix compilation errors when compiled for x86_64. Test: Booted on ibm/sbp1 to linux payload. Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65 Signed-off-by: Arthur Heymans <arthur.heymans(a)9elements.com> --- M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/intel/xeon_sp/spr/romstage.c M src/soc/intel/xeon_sp/spr/upd_display.c 3 files changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/81280/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65 Gerrit-Change-Number: 81280 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2024