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Change subject: mb/google/zork: Update APCB to increase UMA size to 128MB
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/zork: Update APCB to increase UMA size to 128MB
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Patch Set 1: Code-Review+2
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Change subject: mb/google/zork: Update APCB to increase UMA size to 128MB
......................................................................
mb/google/zork: Update APCB to increase UMA size to 128MB
The previous value of 32MB was set to meet Google's ChromeOS reqs,
but hampers real-world performance in Linux/Windows, so increase it
to 128MB to match the "auto" default for the Picasso UEFI firmware.
TEST=build/boot Windows on google/zork (morphius), verify UMA set
to 128MB.
Change-Id: I8c6487a4cb8155f826d20fd3ceca87859829199c
Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/mainboard/google/zork/data.apcb
1 file changed, 0 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/81364/1
diff --git a/src/mainboard/google/zork/data.apcb b/src/mainboard/google/zork/data.apcb
index f7a3e78..ee12694 100644
--- a/src/mainboard/google/zork/data.apcb
+++ b/src/mainboard/google/zork/data.apcb
Binary files differ
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Change subject: arch/arm64: Add Clang as supported target
......................................................................
Patch Set 25:
(1 comment)
File src/arch/arm64/Kconfig:
https://review.coreboot.org/c/coreboot/+/74501/comment/f6e944aa_67fbc75d :
PS23, Line 7: default y if ARCH_ARM64
> AFAIK "no" is automatically the default for bool Kconfigs if no other is specified.
Done
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Change subject: arch/arm64: Add Clang as supported target
......................................................................
arch/arm64: Add Clang as supported target
QEMU aarch64 boots to payload when compiled with clang.
Split up the trogdor config in 2 files as enabling both TPM measured
boot and verified boot causes a too large bootblock for sc7180 so use 2
config files to achieve the same level of build testing.
Change-Id: I940a1ccf5cc4ec7bed5b6c8be92fc47922e1e747
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
R configs/config.google_trogdor.cbfs_verification
C configs/config.google_trogdor.tpm_measured_boot
M src/arch/arm64/Kconfig
3 files changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/74501/25
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Change subject: soc/qualcomm/sc7{1,2}80: Increase romstage/verstage section for clang
......................................................................
Patch Set 4:
(2 comments)
File src/soc/qualcomm/sc7180/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/80639/comment/66398eef_4a4a3ef9 :
PS3, Line 27: REGION(qcsdi, 0x1469C000, 55K, 4K)
> You're actually adjusting this downward here, you don't need to do that. […]
Done
File src/soc/qualcomm/sc7280/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/80639/comment/f5d589c2_a5c2e4e5 :
PS3, Line 30: REGION(modem_id, 0x146A7000, 4, 4)
> Unfortunately modem_id is used as a communication buffer with an external blob and cannot be moved i […]
Done
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Change subject: mainboard/qemu-riscv: Move DRAM resource setup to read_resources
......................................................................
mainboard/qemu-riscv: Move DRAM resource setup to read_resources
A previous commit adds PCI support to the qemu-riscv mainboard code, in
part by adding a read_resources() function. Move its DRAM resource setup
there, similar to qemu-aarch64.
Change-Id: Ic171cb7e22d9da2df18a9d171a5ab89c2cd3298b
Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com>
---
M src/mainboard/emulation/qemu-riscv/mainboard.c
1 file changed, 2 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/80379/2
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Change subject: mainboard/qemu-riscv: Add PCI support
......................................................................
mainboard/qemu-riscv: Add PCI support
Add PCI support for the qemu-riscv mainboard like how it is done for
qemu-aarch64. The resulting build can be used with a QEMU command line
like:
qemu-system-riscv64 \
-display gtk,show-tabs=on \
-bios build/coreboot.rom \
-drive if=pflash,file=build/coreboot.rom,format=raw \
-M virt -m 1G \
-device pcie-root-port \
-serial stdio -device bochs-display \
...
One complication is that the PCIe high MMIO base depends on the amount
of available RAM for 64-bit RISC-V VMs [1], but not for 32-bit ones.
[1] https://gitlab.com/qemu-project/qemu/-/blob/v8.2.2/hw/riscv/virt.c#L1474-14…
Change-Id: Ie57b35620af82c681d1f0d78fa8e514e4df0d2ac
Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com>
---
A src/arch/riscv/include/arch/pci_ops.h
M src/mainboard/emulation/qemu-riscv/Kconfig
M src/mainboard/emulation/qemu-riscv/devicetree.cb
M src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
M src/mainboard/emulation/qemu-riscv/mainboard.c
5 files changed, 64 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/80378/2
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Change subject: arch/arm64: Add Clang as supported target
......................................................................
Patch Set 24:
(1 comment)
Patchset:
PS24:
I need https://chromium-review.googlesource.com/c/chromiumos/platform/vboot_refere… to be in vboot for clang to be happy with the new neon code.
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Change subject: soc/intel/common/block/cse/Kconfig: Remove unused symbols
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> https://source.chromium.org/search?q=CSE_IOMP_FILE&ss=chromiumos […]
Just noticed the revert. We should come up with a long term plan, but we are ok for now. I'll add a skip to the downstream bot so this doesn't conflict again.
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