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Change subject: security/tpm: replace CONFIG(TPMx) checks with runtime check
......................................................................
Patch Set 34:
(5 comments)
File src/security/vboot/secdata_tpm.c:
https://review.coreboot.org/c/coreboot/+/69161/comment/a853dc3b_d31f92ed :
PS34, Line 33: CONFIG(TPM1)
Here too
https://review.coreboot.org/c/coreboot/+/69161/comment/1c9cca67_4a5029ea :
PS34, Line 615: }
I think this would be cleaner as
```
tpm_result_t rc = tlcl_write(index, data, length);
if (tlcl_get_family() == TPM_1 && rc == TPM_MAXNVWRITES) {
/* ...modified comment... */
RETURN_ON_FAILURE(tpm_clear_and_reenable());
rc = tlcl_write(index, data, length);
}
return rc;
```
https://review.coreboot.org/c/coreboot/+/69161/comment/706c4329_3bf3c369 :
PS34, Line 619: #if CONFIG(TPM1)
While you're rewriting all this, would you mind just separating the TPM version-specific stuff out into their own files (e.g. `secdata_tpm1.c` and `secdata_tpm2.c`, maybe with a `secdata_tpm_private.h` header for the internal shared macros and declarations)? If you do that and the `_factory_initialize_tpmX()` functions become non-static, you shouldn't need the `#if`s here anymore because references to the not configured versions should get compiled out.
https://review.coreboot.org/c/coreboot/+/69161/comment/930664ea_0e4f85bd :
PS34, Line 632: #if CONFIG(TPM1)
You shouldn't need these either, same reason.
File src/vendorcode/google/chromeos/cse_board_reset.c:
https://review.coreboot.org/c/coreboot/+/69161/comment/724c28f7_13564101 :
PS34, Line 25: * probably get away with it.
There are many other places where we use `CONFIG(TPM_GOOGLE_...)` to mean that that version is the one actually used anyway. If the `CONFIG(TPM2)` here bothers you you can take it out, it's superfluous (already implied by CR50).
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Change subject: soc/intel/xeon_sp/spr: Enable x86_64 support
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Patchset:
PS3:
do we need to merge https://review.coreboot.org/c/coreboot/+/81281 ahead?
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Hello Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: mb/google/nissa: Create sundance variant
......................................................................
mb/google/nissa: Create sundance variant
Create the sundance variant of nissa reference board by copying the
template files to a new directory named for the variant.
Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.
BUG=b:328505938
Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea
Signed-off-by: leo.chou <leo.chou(a)lcfc.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/sundance/include/variant/ec.h
A src/mainboard/google/brya/variants/sundance/include/variant/gpio.h
A src/mainboard/google/brya/variants/sundance/memory/Makefile.mk
A src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/sundance/overridetree.cb
8 files changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/81347/6
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Change subject: security/tpm: resolve conflicts in TSS implementations
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Patch Set 34: Code-Review+2
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Change subject: soc/qualcomm/sc7{1,2}80: Increase romstage/verstage section for clang
......................................................................
Patch Set 5:
(1 comment)
File src/soc/qualcomm/sc7280/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/80639/comment/0d321111_d0c90bb4 :
PS5, Line 29: 40192
I think it would be more readable to write this as `39K + 256` or `39K + 0x100`
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Change subject: drivers/intel/fsp2_0: Support FSP-T in long mode
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Patch Set 2:
(1 comment)
Patchset:
PS2:
I suppose this is also needed? P.S. I checked https://review.coreboot.org/c/coreboot/+/81280 with this one.
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Change subject: soc/intel/xeon_sp/spr: Enable x86_64 support
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Patch Set 3: Code-Review+2
(1 comment)
File src/soc/intel/xeon_sp/spr/Kconfig:
https://review.coreboot.org/c/coreboot/+/81280/comment/da78693f_69e44f34 :
PS1, Line 20: select HAVE_EXP_X86_64_SUPPORT
> Glad to see this!
Done
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Change subject: soc/intel/xeon_sp/spr: Enable x86_64 support
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Patch Set 3:
(1 comment)
File src/soc/intel/xeon_sp/spr/Kconfig:
https://review.coreboot.org/c/coreboot/+/81280/comment/fada03f2_65d28fea :
PS1, Line 20: select HAVE_EXP_X86_64_SUPPORT
> > Is there a reason why X86_64 support will be tagged with EXP? […]
Glad to see this!
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Change subject: arch/arm64: Add Clang as supported target
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Patch Set 26:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74501/comment/81b282ef_f06b8edd :
PS26, Line 13: config files to achieve the same level of build testing.
Can you just change the sc7180 memlayout to make a bit more space instead? You can steal a few KB from PRERAM_CBFS_CACHE if necessary.
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69161?usp=email )
Change subject: security/tpm: replace CONFIG(TPMx) checks with runtime check
......................................................................
Patch Set 34:
(2 comments)
File src/security/tpm/tspi/tspi.c:
https://review.coreboot.org/c/coreboot/+/69161/comment/d71f1708_29f764e6 :
PS33, Line 205: CONFIG(TPM1)
> Why can't you drop this here?
Not sure whether I tried and whether it worked with an older version of `tlcl_get_family()`, but it works now. In light of this made `TLCL_CALL()` use `tlcl_get_family()` and hid `tlcl_tpm_family` inside of it.
File src/security/tpm/tss.h:
https://review.coreboot.org/c/coreboot/+/69161/comment/d77b1462_af035d34 :
PS33, Line 45: else
> the use of the `else` keyword really is optional and it makes the code looks unnecessarily complicat […]
Done
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