coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: amdfwtool: Only update count in header in only one function
by Bao Zheng (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81372?usp=email to review the following change. Change subject: amdfwtool: Only update count in header in only one function ...................................................................... amdfwtool: Only update count in header in only one function Other function call don't have to worry the fletcher error. Change-Id: I7c9d653100b476b52d6d1d80c41d0c3d765f7be3 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/81372/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 00a366c..ebadb91 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -877,7 +877,7 @@ } count++; - pspdir->header.num_entries = count; + fill_dir_header(pspdir, count, ctx); ctx->current_table = current_table_save; } @@ -903,7 +903,6 @@ if (pspdir2_b != NULL) ctx->ish_b_dir = new_ish_dir(ctx); } - pspdir->header.num_entries = count; integrate_psp_ab(ctx, pspdir, pspdir2, ctx->ish_a_dir, AMD_FW_RECOVERYAB_A, cb_config->soc_id); if (pspdir2_b != NULL) @@ -915,7 +914,6 @@ use_only_a ? AMD_FW_RECOVERYAB_A : AMD_FW_RECOVERYAB_B, cb_config->soc_id); - count = pspdir->header.num_entries; } else if (pspdir2 != NULL) { assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); pspdir->entries[count].type = AMD_FW_L2_PTR; @@ -930,8 +928,8 @@ pspdir->entries[count].address_mode = SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); count++; + fill_dir_header(pspdir, count, ctx); } - fill_dir_header(pspdir, count, ctx); ctx->current_table = current_table_save; } -- To view, visit https://review.coreboot.org/c/coreboot/+/81372?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c9d653100b476b52d6d1d80c41d0c3d765f7be3 Gerrit-Change-Number: 81372 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: arch/x86: Fix typo for macro CPUID_FEATURE_HTT
by Jincheng Li (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Jérémy Compostella, Patrick Rudolph, Shuo Liu. Jincheng Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81260?usp=email ) Change subject: arch/x86: Fix typo for macro CPUID_FEATURE_HTT ...................................................................... Patch Set 9: (1 comment) File src/arch/x86/include/arch/cpu.h: https://review.coreboot.org/c/coreboot/+/81260/comment/3428d649_f50e5365 : PS7, Line 50: CPUID_FEATURE_PAE > src/arch/x86/cpu_common.c:59 isn't modified in this commit. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b29233e75483cda6bf7723cf79632f6b04233b0 Gerrit-Change-Number: 81260 Gerrit-PatchSet: 9 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 02:26:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Jincheng Li <jincheng.li(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: arch/x86: Fix typo for macro CPUID_FEATURE_HTT
by Jincheng Li (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Jincheng Li, Jérémy Compostella, Shuo Liu. Hello Jérémy Compostella, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81260?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/x86: Fix typo for macro CPUID_FEATURE_HTT ...................................................................... arch/x86: Fix typo for macro CPUID_FEATURE_HTT Change-Id: I9b29233e75483cda6bf7723cf79632f6b04233b0 Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/arch/x86/include/arch/cpu.h M src/cpu/intel/common/hyperthreading.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/81260/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/81260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b29233e75483cda6bf7723cf79632f6b04233b0 Gerrit-Change-Number: 81260 Gerrit-PatchSet: 9 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: amdfwtool: Use macro to get the table relative address
by Bao Zheng (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Felix Held, Fred Reitberger, Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78281?usp=email ) Change subject: amdfwtool: Use macro to get the table relative address ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > does this result in identical binaries for all socs? looks to me that the BUFF_TO_RUN_MODE macro doe […] Yes. The binary is identical. commit message is added. -- To view, visit https://review.coreboot.org/c/coreboot/+/78281?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iece4ba65e0476543a8d472168d93801714330dde Gerrit-Change-Number: 78281 Gerrit-PatchSet: 7 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 21 Mar 2024 02:20:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes
by Shuo Liu (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu. Hello Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81316?usp=email to look at the new patch set (#19). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes ...................................................................... soc/intel/xeon_sp: Add GraniteRapids initial codes coreboot GNR (GraniteRapids) is a FSP2.4 based, no-PCH, single IO-APIC Xeon-SP platform. The same set of codes is also used for SRF (SierraForest) SoC. This patch initially setups the code set. All register definitions are forked from SPR (SapphireRapids) and EBG (Emmisburg PCH)'s codes are reused. Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/chip_gen1.c A src/soc/intel/xeon_sp/chip_gen6.c A src/soc/intel/xeon_sp/gnr/Kconfig A src/soc/intel/xeon_sp/gnr/Makefile.inc A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl A src/soc/intel/xeon_sp/gnr/acpi/platform.asl A src/soc/intel/xeon_sp/gnr/chip.c A src/soc/intel/xeon_sp/gnr/chip.h A src/soc/intel/xeon_sp/gnr/cpu.c A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h A src/soc/intel/xeon_sp/gnr/ramstage.c A src/soc/intel/xeon_sp/gnr/romstage.c A src/soc/intel/xeon_sp/gnr/soc_acpi.c A src/soc/intel/xeon_sp/gnr/soc_util.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/fsp_upd.h M src/soc/intel/xeon_sp/lockdown.c M src/soc/intel/xeon_sp/uncore.c 25 files changed, 1,335 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 19 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes
by Shuo Liu (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes ...................................................................... Patch Set 18: (1 comment) File src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/81316/comment/53a9a2a3_f20d77eb : PS7, Line 12: > are all those defines really necessary to make it build? […] Yes ... they are still referenced by xeon-sp common codes. I added the tags as suggested on them. -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 18 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 01:21:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge)
by Joel Linn (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Matt DeVillier. Joel Linn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81368?usp=email ) Change subject: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge) ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Please be so kind to review these changes. I would be glad if you can suggest some other reviewers as my choice would basically be random. -- To view, visit https://review.coreboot.org/c/coreboot/+/81368?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf793fe915096cf2553572964faec5c7f8526b9a Gerrit-Change-Number: 81368 Gerrit-PatchSet: 2 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 01:16:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge)
by Joel Linn (Code Review) 21 Mar '24

21 Mar '24

Joel Linn has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/81368?usp=email ) Change subject: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge) ...................................................................... mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge) This is another readily available (used market) system. Based on autoport. All peripherals should work. Automatic fan control as well as S3 are working. The board was tested to boot Linux and Windows. EHCI debug is untested. When using MrChromebox edk2 with secure boot build in, the board will hang on each boot for about 20 seconds before continuing. There are some quirks for doing the first flash, see the documentation. Change-Id: Idf793fe915096cf2553572964faec5c7f8526b9a Signed-off-by: Joel Linn <jl(a)conductive.de> --- A Documentation/mainboard/hp/pro_3500_series.md A Documentation/mainboard/hp/pro_3500_series_flash.jpg A Documentation/mainboard/hp/pro_3500_series_jumper.jpg A src/mainboard/hp/pro_3500_series/Kconfig A src/mainboard/hp/pro_3500_series/Kconfig.name A src/mainboard/hp/pro_3500_series/Makefile.mk A src/mainboard/hp/pro_3500_series/acpi/ec.asl A src/mainboard/hp/pro_3500_series/acpi/platform.asl A src/mainboard/hp/pro_3500_series/acpi/superio.asl A src/mainboard/hp/pro_3500_series/acpi_tables.c A src/mainboard/hp/pro_3500_series/board_info.txt A src/mainboard/hp/pro_3500_series/common_defines.h A src/mainboard/hp/pro_3500_series/data.vbt A src/mainboard/hp/pro_3500_series/devicetree.cb A src/mainboard/hp/pro_3500_series/dsdt.asl A src/mainboard/hp/pro_3500_series/early_init.c A src/mainboard/hp/pro_3500_series/env_ctrl.c A src/mainboard/hp/pro_3500_series/gma-mainboard.ads A src/mainboard/hp/pro_3500_series/gpio.c A src/mainboard/hp/pro_3500_series/hda_verb.c A src/mainboard/hp/pro_3500_series/led.c A src/mainboard/hp/pro_3500_series/led.h A src/mainboard/hp/pro_3500_series/mainboard.c A src/mainboard/hp/pro_3500_series/smihandler.c M src/superio/ite/common/early_serial.c M src/superio/ite/common/ite.h 26 files changed, 784 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/81368/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81368?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf793fe915096cf2553572964faec5c7f8526b9a Gerrit-Change-Number: 81368 Gerrit-PatchSet: 2 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge)
by Joel Linn (Code Review) 21 Mar '24

21 Mar '24

Joel Linn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81368?usp=email ) Change subject: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge) ...................................................................... mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge) This is another readily available (used market) system. Based on autoport. All peripherals should work. Automatic fan control as well as S3 are working. The board was tested to boot Linux and Windows. EHCI debug is untested. When using MrChromebox edk2 with secure boot build in, the board will hang on each boot for about 20 seconds before continuing. There are some quirks for doing the first flash, see the documentation. Change-Id: Idf793fe915096cf2553572964faec5c7f8526b9a Signed-off-by: Joel Linn <jl(a)conductive.de> --- A Documentation/mainboard/hp/pro_3500_series.md A Documentation/mainboard/hp/pro_3500_series_flash.jpg A Documentation/mainboard/hp/pro_3500_series_jumper.jpg A src/mainboard/hp/pro_3500_series/Kconfig A src/mainboard/hp/pro_3500_series/Kconfig.name A src/mainboard/hp/pro_3500_series/Makefile.mk A src/mainboard/hp/pro_3500_series/acpi/ec.asl A src/mainboard/hp/pro_3500_series/acpi/platform.asl A src/mainboard/hp/pro_3500_series/acpi/superio.asl A src/mainboard/hp/pro_3500_series/acpi_tables.c A src/mainboard/hp/pro_3500_series/board_info.txt A src/mainboard/hp/pro_3500_series/common_defines.h A src/mainboard/hp/pro_3500_series/data.vbt A src/mainboard/hp/pro_3500_series/devicetree.cb A src/mainboard/hp/pro_3500_series/dsdt.asl A src/mainboard/hp/pro_3500_series/early_init.c A src/mainboard/hp/pro_3500_series/env_ctrl.c A src/mainboard/hp/pro_3500_series/gma-mainboard.ads A src/mainboard/hp/pro_3500_series/gpio.c A src/mainboard/hp/pro_3500_series/hda_verb.c A src/mainboard/hp/pro_3500_series/led.c A src/mainboard/hp/pro_3500_series/led.h A src/mainboard/hp/pro_3500_series/mainboard.c A src/mainboard/hp/pro_3500_series/smihandler.c M src/superio/ite/common/early_serial.c M src/superio/ite/common/ite.h 26 files changed, 784 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/81368/1 diff --git a/Documentation/mainboard/hp/pro_3500_series.md b/Documentation/mainboard/hp/pro_3500_series.md new file mode 100644 index 0000000..59952a7 --- /dev/null +++ b/Documentation/mainboard/hp/pro_3500_series.md @@ -0,0 +1,97 @@ +# HP Pro 3500 Series + +This page describes how to run coreboot on the [Pro 3500 Series] desktop +from [HP]. + +## State + +All peripherals should work. Automatic fan control as well as S3 are working. +The board was tested to boot Linux and Windows. EHCI debug is untested. +When using MrChromebox edk2 with secure boot build in, +the board will hang on each boot for about 20 seconds before continuing. +With disabled ME, the SuperIO will not get CPU temperatures via PECI and therefore the automatic fan control will not increase the fan speed. + +## Flashing coreboot + +```eval_rst ++---------------------+-------------------------+ +| Type | Value | ++=====================+=========================+ +| Socketed flash | No | ++---------------------+-------------------------+ +| Model | W25Q64FVSIG | ++---------------------+-------------------------+ +| Size | 8 MiB | ++---------------------+-------------------------+ +| In circuit flashing | Yes | ++---------------------+-------------------------+ +| Package | SOIC-8 | ++---------------------+-------------------------+ +| Write protection | See below | ++---------------------+-------------------------+ +| Dual BIOS feature | No | ++---------------------+-------------------------+ +| Internal flashing | Yes | ++---------------------+-------------------------+ +``` + +### Flash layout +The original layout of the flash should look like this: +``` +00000000:00000fff fd +00400000:007fffff bios +00001000:003fffff me +00fff000:00000fff gbe +00fff000:00000fff pd +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom] (although it reports as "N25Q064..3E", it works fine). + +With a missing FDO jumper, `fd` region is read-only, `bios` region is read-write and `me` region is locked. +Vendor firmware will additionally protect the flash chip. +After shorting the FDO jumper (E2) full read-write access is granted. + +Do **NOT shutdown** the operating system **after flashing** coreboot from the vendor firmware! +This will brick your device because the bios region will be modified on shutdown. +Cut the AC power or do a restart from the OS. + +**Position of FDO jumper (E2) close to the F_USB3** +![][pro_3500_jumper] + +[pro_3500_jumper]: pro_3500_series_jumper.jpg + +### External programming + +External programming with an SPI adapter and [flashrom] does work, but it powers the +whole southbridge complex. The average current will be 400mA but spikes may be higher. +Connect the power to the flash or the programming header next to the flash otherwise programming is unstable. +The supply needs to quickly reach 3V3 or else the chip is also unstable until cleanly power cycled. + +**Position of SOIC-8 flash IC near ATX power connector and programming header pin-out** +![][pro_3500_flash] + +[pro_3500_flash]: pro_3500_series_flash.jpg + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x (bd82h61) | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| SuperIO | ITE8779e (identifies as 8772f in register) | ++------------------+--------------------------------------------------+ +| EC | Fixed function as part of SuperIO | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel ME | ++------------------+--------------------------------------------------+ +``` + +[Pro 3500 Series]: https://support.hp.com/us-en/document/c03364089 +[HP]: https://www.hp.com/ +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/hp/pro_3500_series_flash.jpg b/Documentation/mainboard/hp/pro_3500_series_flash.jpg new file mode 100644 index 0000000..22c8817 --- /dev/null +++ b/Documentation/mainboard/hp/pro_3500_series_flash.jpg Binary files differ diff --git a/Documentation/mainboard/hp/pro_3500_series_jumper.jpg b/Documentation/mainboard/hp/pro_3500_series_jumper.jpg new file mode 100644 index 0000000..cf620c2 --- /dev/null +++ b/Documentation/mainboard/hp/pro_3500_series_jumper.jpg Binary files differ diff --git a/src/mainboard/hp/pro_3500_series/Kconfig b/src/mainboard/hp/pro_3500_series/Kconfig new file mode 100644 index 0000000..cbe92ef --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/Kconfig @@ -0,0 +1,40 @@ +if BOARD_HP_PRO_3500_SERIES + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_ITE_IT8772F + select USE_NATIVE_RAMINIT + +config CBFS_SIZE + default 0x400000 + +config MAINBOARD_DIR + string + default "hp/pro_3500_series" + +config MAINBOARD_PART_NUMBER + string + default "Pro 3500 Series" + +config VGA_BIOS_ID + string + default "8086,0152" + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/hp/pro_3500_series/Kconfig.name b/src/mainboard/hp/pro_3500_series/Kconfig.name new file mode 100644 index 0000000..cfc50ce --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_PRO_3500_SERIES + bool "Pro 3500 Series" diff --git a/src/mainboard/hp/pro_3500_series/Makefile.mk b/src/mainboard/hp/pro_3500_series/Makefile.mk new file mode 100644 index 0000000..b7c8165 --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/Makefile.mk @@ -0,0 +1,9 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-y += env_ctrl.c + +smm-y += led.c +bootblock-y += led.c diff --git a/src/mainboard/hp/pro_3500_series/acpi/ec.asl b/src/mainboard/hp/pro_3500_series/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/acpi/ec.asl diff --git a/src/mainboard/hp/pro_3500_series/acpi/platform.asl b/src/mainboard/hp/pro_3500_series/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/hp/pro_3500_series/acpi/superio.asl b/src/mainboard/hp/pro_3500_series/acpi/superio.asl new file mode 100644 index 0000000..829a391 --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/acpi/superio.asl @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Values should match those defined in devicetree.cb */ + +#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller +#undef SIO_ENABLE_COM1 // pnp 2e.1: Disable Serial Port 1 +#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard +#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse +#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR + +#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller +#define SIO_ENVC_IO0 0xa30 // pnp 2e.4: io 0x60 +#define SIO_ENVC_IO1 0xa20 // pnp 2e.4: io 0x62 +#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO +#define SIO_GPIO_IO0 0x0 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO1 0xa00 // pnp 2e.7: io 0x62 + +#include <superio/ite/it8772f/acpi/superio.asl> diff --git a/src/mainboard/hp/pro_3500_series/acpi_tables.c b/src/mainboard/hp/pro_3500_series/acpi_tables.c new file mode 100644 index 0000000..e275965 --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/acpi_tables.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <soc/nvs.h> + +/* FIXME: check this function. */ +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/pro_3500_series/board_info.txt b/src/mainboard/hp/pro_3500_series/board_info.txt new file mode 100644 index 0000000..1780394 --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/hp/pro_3500_series/common_defines.h b/src/mainboard/hp/pro_3500_series/common_defines.h new file mode 100644 index 0000000..4813974 --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/common_defines.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_COMMON_DEFINES_H +#define __MAINBOARD_COMMON_DEFINES_H + +#include <superio/ite/it8772f/it8772f.h> + +#define IT8772F_BASE 0x2e +#define EC_DEV PNP_DEV(IT8772F_BASE, IT8772F_EC) +#define GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) + +#endif /* __MAINBOARD_COMMON_DEFINES_H */ diff --git a/src/mainboard/hp/pro_3500_series/data.vbt b/src/mainboard/hp/pro_3500_series/data.vbt new file mode 100644 index 0000000..7309d99 --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/data.vbt Binary files differ diff --git a/src/mainboard/hp/pro_3500_series/devicetree.cb b/src/mainboard/hp/pro_3500_series/devicetree.cb new file mode 100644 index 0000000..916f311 --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/devicetree.cb @@ -0,0 +1,160 @@ +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + # XMM1: CH0S0 0x50 + # XMM3: CH1S0 0x52 + register "spd_addresses" = "{0x50, 0, 0x52, 0}" + + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x003c0a01" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + # SATA0: ata1 0x01 + # SATA1: ata2 0x02 + # SATA2: ata5 0x10 + # SATA3: ata6 0x20 + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device ref mei1 on # Management Engine Interface 1 + subsystemid 0x103c 0x2abf + end + device ref mei2 off # Management Engine Interface 2 + end + device ref me_ide_r off # Management Engine IDE-R + end + device ref me_kt off # Management Engine KT + end + device ref gbe off # Intel Gigabit Ethernet + end + device ref ehci2 on # USB2 EHCI #2 + subsystemid 0x103c 0x2abf + end + device ref hda on # High Definition Audio + subsystemid 0x103c 0x2abf + end + device ref pcie_rp1 off + subsystemid 0x103c 0x2abf + end + device ref pcie_rp2 on # MINI_PCIE + end + device ref pcie_rp3 on # PCIEx1_1 + end + device ref pcie_rp4 on # PCIEx1_2 + end + device ref pcie_rp5 on # PCIEx1_3 + end + device ref pcie_rp6 on # RTL8171EH + subsystemid 0x103c 0x2abf + end + device ref pcie_rp7 off + end + device ref pcie_rp8 off + end + device ref ehci1 on # USB2 EHCI #1 + subsystemid 0x103c 0x2abf + end + device ref pci_bridge off # PCI bridge + end + device ref lpc on # LPC bridge + subsystemid 0x103c 0x2abf + chip superio/ite/it8772f + #register "gpio_set1" = "0x00" + #register "gpio_set2" = "0xff" + #register "gpio_set3" = "0x00" + #register "gpio_set4" = "0x00" + #register "gpio_set5" = "0x00" + + register "ec.smbus_en" = "1" + #register "ec.smbus_24mhz" = "1" + register "TMPIN1.mode" = "THERMAL_MODE_DISABLED" + register "TMPIN2.mode" = "THERMAL_DIODE" # Near ATX_CPU connector + register "TMPIN3.mode" = "THERMAL_PECI" + register "TMPIN3.offset" = "CPU_TJ_MAX_OFFSET" + + # CPU fan + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" + register "FAN2.smart.tmpin" = "3" + register "FAN2.smart.tmp_off" = "-127" + register "FAN2.smart.tmp_start" = "40" + register "FAN2.smart.tmp_full" = "86" + register "FAN2.smart.tmp_delta" = "5" + register "FAN2.smart.pwm_start" = "25" + register "FAN2.smart.slope" = "6" + # System fan + register "FAN3.mode" = "FAN_SMART_AUTOMATIC" + register "FAN3.smart.tmpin" = "3" + register "FAN3.smart.tmp_off" = "-127" + register "FAN3.smart.tmp_start" = "40" + register "FAN3.smart.tmp_full" = "86" + register "FAN3.smart.tmp_delta" = "5" + register "FAN3.smart.pwm_start" = "34" + register "FAN3.smart.slope" = "11" + + register "FAN_VECA.tmpin" = "2" + register "FAN_VECA.fanout" = "2" + register "FAN_VECA.tmp_start" = "57" + register "FAN_VECA.tmp_delta" = "5" + register "FAN_VECA.slope" = "26" + + register "FAN_VECB.tmpin" = "2" + register "FAN_VECB.fanout" = "3" + register "FAN_VECB.tmp_start" = "48" + register "FAN_VECB.tmp_delta" = "5" + register "FAN_VECB.slope" = "5" + + register "ec.vin_mask" = "VIN_ALL" + + device pnp 2e.0 off end # FDC + device pnp 2e.1 off end # Serial Port 1 + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa30 + io 0x62 = 0xa20 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x0 + io 0x62 = 0xa00 + end + device pnp 2e.5 off end # Keyboard, enabled in vendor firmware but missing connector + device pnp 2e.6 off end # Mouse , enabled in vendor firmware but missing connector + device pnp 2e.a off end # IR + end + end + device ref sata1 on # SATA Controller 1 + subsystemid 0x103c 0x2abf + end + device ref smbus on # SMBus + subsystemid 0x103c 0x2abf + end + device ref sata2 off # SATA Controller 2 + end + device ref thermal off # Thermal + end + end + device ref host_bridge on # Host bridge Host bridge + subsystemid 0x103c 0x2abf + end + device ref peg10 on # PEG + subsystemid 0x103c 0x2abf + end + device ref igd on # iGPU + subsystemid 0x103c 0x2abf + end + end +end diff --git a/src/mainboard/hp/pro_3500_series/dsdt.asl b/src/mainboard/hp/pro_3500_series/dsdt.asl new file mode 100644 index 0000000..7d13c55 --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/dsdt.asl @@ -0,0 +1,30 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/hp/pro_3500_series/early_init.c b/src/mainboard/hp/pro_3500_series/early_init.c new file mode 100644 index 0000000..4823430 --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/early_init.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <superio/ite/common/mainboard_impl.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8772f/it8772f.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/hwm5_conf.h> +#include "common_defines.h" +#include "led.h" + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 6, 0 }, + { 1, 6, 0 }, + { 1, 6, 1 }, + { 1, 0, 1 }, // FIXME: Unknown current: RCBA(0x350c)=0x350c + { 1, 0, 2 }, // FIXME: Unknown current: RCBA(0x3510)=0x3510 + { 1, 0, 2 }, // FIXME: Unknown current: RCBA(0x3514)=0x3514 + { 1, 6, 3 }, + { 1, 6, 3 }, + { 1, 6, 4 }, + { 1, 0, 4 }, // FIXME: Unknown current: RCBA(0x3524)=0x3524 + { 1, 6, 6 }, + { 1, 0, 5 }, // FIXME: Unknown current: RCBA(0x352c)=0x352c + { 1, 6, 5 }, + { 1, 6, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1400); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); + + /* Early SuperIO setup */ + ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24); + /* Clear when resuming from S3: */ + ite_disable_3vsbsw(GPIO_DEV); + ite_pme_out_disable(EC_DEV); + ite_ac_resume_southbridge(EC_DEV); + // ite_kill_watchdog(GPIO_DEV); + + set_power_led(LED_WHITE); +} diff --git a/src/mainboard/hp/pro_3500_series/env_ctrl.c b/src/mainboard/hp/pro_3500_series/env_ctrl.c new file mode 100644 index 0000000..f5914d1 --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/env_ctrl.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/intel/model_206ax/model_206ax.h> +#include <cpu/x86/msr.h> +#include <superio/ite/common/mainboard_impl.h> + +u8 cpu_get_temp_offset(void) { + msr_t msr = rdmsr(MSR_TEMPERATURE_TARGET); + u8 tj_max = (msr.lo >> 16) & 0xFF; + u8 tcc_offset = (msr.lo >> 24) & 0xf; + + msr = rdmsr(MSR_PLATFORM_INFO); + if (msr.lo & (1 << 30)) { + return tj_max - tcc_offset; + } else { + return tj_max; + } +} diff --git a/src/mainboard/hp/pro_3500_series/gma-mainboard.ads b/src/mainboard/hp/pro_3500_series/gma-mainboard.ads new file mode 100644 index 0000000..c9e4326 --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/pro_3500_series/gpio.c b/src/mainboard/hp/pro_3500_series/gpio.c new file mode 100644 index 0000000..3ab365f --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/gpio.c @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_LOW, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/pro_3500_series/hda_verb.c b/src/mainboard/hp/pro_3500_series/hda_verb.c new file mode 100644 index 0000000..4b3104e --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0662, /* Codec Vendor / Device ID: Realtek */ + 0x103c2abf, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c2abf), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19830), + AZALIA_PIN_CFG(0, 0x19, 0x02a19831), + AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), + AZALIA_PIN_CFG(0, 0x1b, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/pro_3500_series/led.c b/src/mainboard/hp/pro_3500_series/led.c new file mode 100644 index 0000000..073f5f5 --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/led.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "common_defines.h" +#include "led.h" + +void set_power_led(int state) +{ + // Board has a dual color LED + it8772f_gpio_setup( + GPIO_DEV, + 2, /* set */ + 0xf3 | LED_BOTH, /* select, 0xf3 is default */ + state, /* polarity */ + 0x00, /* pullup */ + LED_BOTH, /* output */ + 0x00); /* enable */ +} diff --git a/src/mainboard/hp/pro_3500_series/led.h b/src/mainboard/hp/pro_3500_series/led.h new file mode 100644 index 0000000..fb663ba --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/led.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_LED_H +#define __MAINBOARD_LED_H + +#ifndef __ACPI__ +void set_power_led(int state); + +enum +{ + LED_WHITE = 1 << 2, // GPIO 22 + LED_YELLOW = 1 << 3, // GPIO 23 + LED_BOTH = LED_WHITE | LED_YELLOW, + LED_OFF = LED_BOTH +}; +#endif + +#endif /* __MAINBOARD_LED_H */ diff --git a/src/mainboard/hp/pro_3500_series/mainboard.c b/src/mainboard/hp/pro_3500_series/mainboard.c new file mode 100644 index 0000000..72d1fbf --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: untested. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/pro_3500_series/smihandler.c b/src/mainboard/hp/pro_3500_series/smihandler.c new file mode 100644 index 0000000..c611f56 --- /dev/null +++ b/src/mainboard/hp/pro_3500_series/smihandler.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <superio/ite/common/ite.h> +#include "common_defines.h" +#include "led.h" + +/* + * Change power led state based on sleep type. +*/ +void mainboard_smi_sleep(u8 slp_typ) +{ + printk(BIOS_DEBUG, "SMI: sleep S%d\n", slp_typ); + switch (slp_typ) { + case ACPI_S3: + /* + * Vendor firmware also only enables this when entering sleep. + * This saves some power when entering S5 via shutdown. + */ + ite_enable_3vsbsw(GPIO_DEV); + set_power_led(LED_YELLOW); + break; + case ACPI_S4: + /* Without 3vsbsw enabled the LED will be off in any case */ + case ACPI_S5: + set_power_led(LED_OFF); + break; + default: + break; + } +} diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index bc05da7..3facf03 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -106,6 +106,11 @@ ite_set_3vsbsw(dev, true); } +void ite_disable_3vsbsw(pnp_devfn_t dev) +{ + ite_set_3vsbsw(dev, false); +} + /* * * LDN 7, reg 0x2a, bit 0 - delay PWRGD3 rising edge after 3VSBSW# rising edge diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h index fe1f0c9..e9ffda5 100644 --- a/src/superio/ite/common/ite.h +++ b/src/superio/ite/common/ite.h @@ -18,6 +18,7 @@ void ite_set_3vsbsw(pnp_devfn_t dev, bool enable); /* Alias for backwards compatibility */ void ite_enable_3vsbsw(pnp_devfn_t dev); +void ite_disable_3vsbsw(pnp_devfn_t dev); void ite_delay_pwrgd3(pnp_devfn_t dev); void ite_kill_watchdog(pnp_devfn_t dev); void ite_pme_out_disable(pnp_devfn_t dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/81368?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf793fe915096cf2553572964faec5c7f8526b9a Gerrit-Change-Number: 81368 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-MessageType: newchange

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[XL] Change in coreboot[main]: lib/device_tree: Add some FDT helper functions
by Julius Werner (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Jakub Czapiga, Martin L Roth, Maximilian Brune. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81081?usp=email ) Change subject: lib/device_tree: Add some FDT helper functions ...................................................................... Patch Set 14: (3 comments) File src/lib/device_tree.c: https://review.coreboot.org/c/coreboot/+/81081/comment/a2252249_5f8b2a76 : PS12, Line 200: if (!strncmp(*path, node_name, path_sub_len)) { > Isn't that the same as creating variable length arrays? I thought we don't do that anymore in corebo […] Don't we? It's used in acpigen and vboot/ec_sync, for example. I think VLAs might be discouraged because they make it hard to see that a variable stack allocation takes place, but alloca makes it very explicit. I don't think the function is fundamentally bad in any way, you just need to be sure you know how you're using it (and in this case I think it's safe to assume that FDT paths will be reasonably bounded). https://review.coreboot.org/c/coreboot/+/81081/comment/9fe14573_1fe14861 : PS12, Line 235: } while (be32dec(blob + offset) != FDT_TOKEN_END_NODE); > Well `fdt_next_node_name` expects a `FDT_TOKEN_BEGIN_NODE`. […] Yeah, I think keeping the code simple is more important here. We're not writing a device tree verifier. As long as broken input doesn't cause it to crash or use bogus data, I think that's good enough. https://review.coreboot.org/c/coreboot/+/81081/comment/3b24cef0_ee1d7eb6 : PS12, Line 337: results[(*count_results)++] = offset; > Maybe do both? […] Ack, I think that's good enough. -- To view, visit https://review.coreboot.org/c/coreboot/+/81081?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8 Gerrit-Change-Number: 81081 Gerrit-PatchSet: 14 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 01:00:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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