coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: soc/intel/adl: Guard TWL SoC missing UPDs for build integrity
by Subrata Banik (Code Review) 21 Mar '24

21 Mar '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81376?usp=email ) Change subject: soc/intel/adl: Guard TWL SoC missing UPDs for build integrity ...................................................................... soc/intel/adl: Guard TWL SoC missing UPDs for build integrity Adds config-based guards for Usb4CmMode and CnviWifiCore UPDs, specific to Twin Lake SoCs (SOC_INTEL_TWINLAKE). Prevents compilation errors due to missing UPD definitions. BUG=b:330654700 TEST=Able to build google/tivviks. Change-Id: I6e0a9a7536df6295e23bf06003539e56bb98a311 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81376 Reviewed-by: V Sowmya <v.sowmya(a)intel.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Dinesh Gehlot: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified V Sowmya: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 4ddf1e4..33ebee3 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -683,7 +683,9 @@ s_cfg->UsbTcPortEn |= BIT(i); } +#if !CONFIG(SOC_INTEL_TWINLAKE) s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER); +#endif } static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, @@ -831,7 +833,9 @@ const struct soc_intel_alderlake_config *config) { /* CNVi */ +#if !CONFIG(SOC_INTEL_TWINLAKE) s_cfg->CnviWifiCore = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); +#endif s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); s_cfg->CnviBtCore = config->cnvi_bt_core; s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload; -- To view, visit https://review.coreboot.org/c/coreboot/+/81376?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e0a9a7536df6295e23bf06003539e56bb98a311 Gerrit-Change-Number: 81376 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/adl: Guard TWL SoC missing UPDs for build integrity
by Dinesh Gehlot (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik. Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81376?usp=email ) Change subject: soc/intel/adl: Guard TWL SoC missing UPDs for build integrity ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81376?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e0a9a7536df6295e23bf06003539e56bb98a311 Gerrit-Change-Number: 81376 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 07:11:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes
by Shuo Liu (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes ...................................................................... Patch Set 20: (2 comments) File src/soc/intel/xeon_sp/chip_gen6.c: https://review.coreboot.org/c/coreboot/+/81316/comment/05864c27_4fc2d2b7 : PS18, Line 145: soc_create_fsp24_domains(dp, upstream, sr, DOMAIN_TYPE_IOAT, pci_segment_group); > On gen1 there are multiple PCI domains of the same type on the same stack. It works on gen1. […] This will work, but I realized that in SPR, the domain names will be conflict with the static SSDT ASLs. I make some refactor of gen6 codes to use current way to support domain names and it looks not bad. Could you please review? File src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/81316/comment/06c67e59_a39b97d3 : PS7, Line 12: > Yes ... they are still referenced by xeon-sp common codes. I added the tags as suggested on them. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 20 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 06:58:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/adl: Guard TWL SoC missing UPDs for build integrity
by V Sowmya (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81376?usp=email ) Change subject: soc/intel/adl: Guard TWL SoC missing UPDs for build integrity ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81376?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e0a9a7536df6295e23bf06003539e56bb98a311 Gerrit-Change-Number: 81376 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 06:50:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes
by Patrick Rudolph (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, TangYiwei, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes ...................................................................... Patch Set 20: (1 comment) File src/soc/intel/xeon_sp/chip_gen6.c: https://review.coreboot.org/c/coreboot/+/81316/comment/f1d68edc_1f12039c : PS18, Line 145: soc_create_fsp24_domains(dp, upstream, sr, DOMAIN_TYPE_IOAT, pci_segment_group); > Alternative would be: we split iio_domain_set_acpi_name between gen1 and gen6, for gen6, the 2nd cha […] On gen1 there are multiple PCI domains of the same type on the same stack. It works on gen1. What's the problem here? A good solution would be: 1. Add root UID into union xeon_domain_path on gen1 2. Use root UID to increment 2nd char of DOMAIN_TYPE 3. Update gen1 to use new root UID 4. Drop define DOMAIN_TYPE_UBX1, DOMAIN_TYPE_HQM1, DOMAIN_TYPE_CPM1 5. Use new iio_domain_set_acpi_name on gen6 as well -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 20 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 06:44:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes
by Patrick Rudolph (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, TangYiwei, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes ...................................................................... Patch Set 20: (1 comment) File src/soc/intel/xeon_sp/lockdown.c: https://review.coreboot.org/c/coreboot/+/81316/comment/7a0e3267_e78b099b : PS17, Line 24: chipset_lockdown > it should be okay, since only GNR use CHIPSET_LOCKDOWN_FSP, previous generations are all CHIPSET_LOC […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 20 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 06:40:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Add support of _OSC ASL generation
by Shuo Liu (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81375?usp=email to look at the new patch set (#2). Change subject: soc/intel/xeon_sp: Add support of _OSC ASL generation ...................................................................... soc/intel/xeon_sp: Add support of _OSC ASL generation Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/gnr/soc_acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h 3 files changed, 340 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81375/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes
by Patrick Rudolph (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, TangYiwei, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes ...................................................................... Patch Set 20: (1 comment) File src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/81316/comment/704070c7_f2895d17 : PS7, Line 12: > Yes ... they are still referenced by xeon-sp common codes. I added the tags as suggested on them. This seems to be not true. see https://review.coreboot.org/c/coreboot/+/81369 -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 20 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 06:39:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp/spr: Drop unused defines
by Patrick Rudolph (Code Review) 21 Mar '24

21 Mar '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81369?usp=email ) Change subject: soc/intel/xeon_sp/spr: Drop unused defines ...................................................................... soc/intel/xeon_sp/spr: Drop unused defines Since there's no code using those defines drop them. TEST: Still builds. Change-Id: I507b08a62ebeae14a1e63f4340b0592605a32477 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/smmrelocate.c M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h M src/soc/intel/xeon_sp/spr/include/soc/soc_msr.h 3 files changed, 8 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/81369/1 diff --git a/src/soc/intel/xeon_sp/smmrelocate.c b/src/soc/intel/xeon_sp/smmrelocate.c index 89f35c2..c359237 100644 --- a/src/soc/intel/xeon_sp/smmrelocate.c +++ b/src/soc/intel/xeon_sp/smmrelocate.c @@ -7,6 +7,7 @@ #include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/smm_reloc.h> #include <console/console.h> +#include <device/device.h> #include <device/pci_ids.h> #include <smp/node.h> #include <soc/msr.h> diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h index 0ad5ea0..09953aa 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h @@ -8,18 +8,6 @@ #include <soc/pch_pci_devs.h> #include <types.h> -#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_##slot, 0) - -#if !defined(__SIMPLE_DEVICE__) -#include <device/device.h> -#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) -#else -#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_##slot, 0) -#endif - -#define UNCORE_BUS_0 0 -#define UNCORE_BUS_1 1 - /* UBOX Registers [U(1), D:0, F:1] */ #define SMM_FEATURE_CONTROL 0x8c #define SMM_CODE_CHK_EN BIT(2) @@ -37,19 +25,9 @@ #define SAD_ALL_PAM456_CSR 0x84 #define SAD_ALL_DEVID 0x344f -#if !defined(__SIMPLE_DEVICE__) -#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) -#else -#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) -#endif - -/* PCU [B:31, D:30, F:0->F:6] */ -#define PCU_IIO_STACK UNCORE_BUS_1 -#define PCU_DEV 30 - -#define PCU_CR0_FUN 0 +/* PCU [B:31, D:30, F:0] */ +#define PCU_IIO_STACK 1 #define PCU_CR0_DEVID 0x3258 -#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 #define TURBO_ACTIVATION_RATIO_LOCK BIT(31) @@ -60,37 +38,27 @@ #define PKG_PWR_LIM_LOCK_UPR BIT(31) #define PCU_CR0_PMAX 0xf0 #define PMAX_LOCK BIT(31) -#define PCU_CR0_VR_CURRENT_CONFIG_CFG 0xf8 -#define VR_CURRENT_CONFIG_LOCK BIT(31) -#define PCU_CR1_FUN 1 +/* PCU [B:31, D:30, F:1] */ #define PCU_CR1_DEVID 0x3259 -#define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN) #define PCU_CR1_BIOS_MB_DATA_REG 0x8c #define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 #define BIOS_MB_RUN_BUSY_MASK BIT(31) -#define BIOS_MB_CMD_MASK 0xff #define BIOS_CMD_READ_PCU_MISC_CFG 0x5 #define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 -#define BIOS_ERR_INVALID_CMD 0x01 #define PCU_CR1_BIOS_RESET_CPL_REG 0x94 -#define RST_CPL1_MASK BIT(1) -#define RST_CPL2_MASK BIT(2) #define RST_CPL3_MASK BIT(3) #define RST_CPL4_MASK BIT(4) -#define PCODE_INIT_DONE1_MASK BIT(9) -#define PCODE_INIT_DONE2_MASK BIT(10) #define PCODE_INIT_DONE3_MASK BIT(11) #define PCODE_INIT_DONE4_MASK BIT(12) #define PCU_CR1_DESIRED_CORES_CFG2_REG 0xbc #define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) -#define PCU_CR2_FUN 2 +/* PCU [B:31, D:30, F:2] */ #define PCU_CR2_DEVID 0x325a -#define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) #define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 #define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) #define DRAM_POWER_INFO_LOCK_UPR BIT(31) @@ -99,27 +67,15 @@ #define PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR (PCU_CR2_DRAM_PLANE_POWER_LIMIT_LWR + 4) #define PP_PWR_LIM_LOCK_UPR BIT(31) -#define PCU_CR3_FUN 3 +/* PCU [B:31, D:30, F:3] */ #define PCU_CR3_DEVID 0x325b -#define PCU_CR3_CAPID4 0x94 -#define ERR_SPOOFING_DIS 1 -#define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) #define PCU_CR3_CONFIG_TDP_CONTROL 0xd8 #define TDP_LOCK BIT(31) #define PCU_CR3_FLEX_RATIO 0xa0 #define OC_LOCK BIT(20) -#define PCU_CR4_FUN 4 -#define PCU_CR4_DEVID 0x325c -#define PCU_VIRAL_CONTROL 0x84 -#define PCU_FW_ERR_EN (1 << 10) -#define PCU_UC_ERR_EN (1 << 9) -#define PCU_HW_ERR_EN (1 << 8) -#define PCU_EMCA_MODE (1 << 2) - -#define PCU_CR6_FUN 6 +/* PCU [B:31, D:30, F:6] */ #define PCU_CR6_DEVID 0x325e -#define PCU_DEV_CR6(bus) _PCU_DEV(bus, PCU_CR6_FUN) #define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR 0xa8 #define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR (PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR + 4) #define PLT_PWR_LIM_LOCK_UPR BIT(31) @@ -128,10 +84,8 @@ #define PLT_PWR_INFO_LOCK_UPR BIT(31) /* Memory Map/VTD Device Functions - * These are available in each IIO stack + * These are available in each IIO stack at B:D.F = B:0.0 */ -#define MMAP_VTD_DEV 0x0 -#define MMAP_VTD_FUNC 0x0 #define VTD_TOLM_CSR 0xd0 #define VTD_TSEG_BASE_CSR 0xa8 @@ -146,9 +100,6 @@ #define VTD_BAR_CSR 0x180 #define VTD_LTDPR 0x290 -#define VMD_DEV_NUM 0x00 -#define VMD_FUNC_NUM 0x05 - #define MMAP_VTD_CFG_REG_DEVID 0x09a2 #define MMAP_VTD_STACK_CFG_REG_DEVID 0x09a2 #define VTD_DEV_NUM 0x0 @@ -162,18 +113,6 @@ /* Root port Registers */ -/* IEH */ -#define IEH_EXT_CAP_ID 0x7 /* At 0x160 */ -#define GSYSEVTCTL 0x104 /* Offset from IEH_EXT_CAP_ID */ -#define CE_ERR_UNMSK 1 -#define NON_FATAL_UNMSK (1 << 1) -#define FATAL_UNMSK (1 << 2) -#define GSYSEVTMAP 0x108 /* Offset from IEH_EXT_CAP_ID */ -#define CE_SMI 1 -#define NF_SMI (1 << 2) -#define FA_SMI (1 << 4) - - #define DMIRCBAR 0x50 #define DMI3_DEVID 0x2020 #define PCIE_ROOTCTL 0x5c diff --git a/src/soc/intel/xeon_sp/spr/include/soc/soc_msr.h b/src/soc/intel/xeon_sp/spr/include/soc/soc_msr.h index cfae169..3ebb4d4 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/soc_msr.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/soc_msr.h @@ -3,12 +3,6 @@ #ifndef _SOC_MSR_SPR_H_ #define _SOC_MSR_SPR_H_ -#define MSR_CPU_BUSNO 0x128 -#define BUSNO_VALID (1 << 31) /* used as msr.hi */ - -/* IA32_ERR_CTRL */ -#define CMCI_DISABLE (1 << 4) - /* MSR_PKG_CST_CONFIG_CONTROL */ #define PKG_CSTATE_NO_LIMIT (0x8 << PKG_CSTATE_LIMIT_SHIFT) @@ -37,15 +31,6 @@ #define CSTATE_PREWAKE_DISABLE_SHIFT 30 #define CSTATE_PREWAKE_DISABLE (1 << CSTATE_PREWAKE_DISABLE_SHIFT) -/* SPR has banks 0-20 and 29-31 */ -#define IA32_MC20_CTL2 0x294 -#define IA32_MC29_CTL2 0x29D -#define IA32_MC30_CTL2 0x29E -#define IA32_MC31_CTL2 0x29F - -#define MSR_PERRINJ_AT_IP 0x107 -#define MSR_PERRINJ_AT_IP_ENABLE BIT(31) - #define MSR_BIOS_DONE 0x151 #define XEON_SP_ENABLE_IA_UNTRUSTED BIT(0) -- To view, visit https://review.coreboot.org/c/coreboot/+/81369?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I507b08a62ebeae14a1e63f4340b0592605a32477 Gerrit-Change-Number: 81369 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/adl: Guard TWL SoC missing UPDs for build integrity
by Eric Lai (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik, V Sowmya. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81376?usp=email ) Change subject: soc/intel/adl: Guard TWL SoC missing UPDs for build integrity ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81376?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e0a9a7536df6295e23bf06003539e56bb98a311 Gerrit-Change-Number: 81376 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 06:25:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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