coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

1 participants
3668 discussions

[S] Change in coreboot[main]: mb/google/nissa: Create sundance variant
by Leo Chou (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Leo Chou, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik. Hello Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81347?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+2 by Eric Lai, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/google/nissa: Create sundance variant ...................................................................... mb/google/nissa: Create sundance variant Create the sundance variant of nissa reference board by copying the template files to a new directory named for the variant. Due to new_variant.py limitation that repo can no longer be used in inside, created this CL manually following google suggestion. BUG=b:328505938 Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea Signed-off-by: leo.chou <leo.chou(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/sundance/include/variant/ec.h A src/mainboard/google/brya/variants/sundance/include/variant/gpio.h A src/mainboard/google/brya/variants/sundance/memory/Makefile.mk A src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/sundance/overridetree.cb 8 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/81347/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/81347?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea Gerrit-Change-Number: 81347 Gerrit-PatchSet: 7 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Enable x86_64 support
by Nico Huber (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Ray Ni, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81280?usp=email ) Change subject: soc/intel/xeon_sp/spr: Enable x86_64 support ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65 Gerrit-Change-Number: 81280 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 09:36:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: [WIP]arch/x86: Support x86_64 kernel entry
by Patrick Rudolph (Code Review) 21 Mar '24

21 Mar '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81371?usp=email ) Change subject: [WIP]arch/x86: Support x86_64 kernel entry ...................................................................... [WIP]arch/x86: Support x86_64 kernel entry - Call payload in long mode when necessary. - Detect long mode in linux trampoline and call 64-bit kernel entry point. - Modify x86 code to run in long and protected mode TODO: Use different approach? - Detect x86_64 support in cbfstool? - Detect long mode at trampoline entry and duplicate code? Change-Id: Ia5e28bc61e759d14140b44ca738a03d4fdff7fdc Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M payloads/Kconfig M src/arch/x86/boot.c M util/cbfstool/linux_trampoline.S M util/cbfstool/linux_trampoline.c 4 files changed, 113 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/81371/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index ec1d40c..d3fa580 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -92,6 +92,17 @@ coreboot can compress them using the LZ4 algorithm. endchoice +config PAYLOAD_ELF_X86_32 + bool "Payload is an x86_32 executable" + depends on PAYLOAD_FILE + depends on ARCH_X86 + depends on USE_EXP_X86_64_SUPPORT + default n + help + Select this option if you have a payload image (an ELF file) + which coreboot should run in 32-bits (protected mode). + When false the payload is run in 64-bits (long mode). + config PAYLOAD_OPTIONS string "Additional cbfstool options" if PAYLOAD_FLAT_BINARY default "" diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c index 90af84f..130a0dd 100644 --- a/src/arch/x86/boot.c +++ b/src/arch/x86/boot.c @@ -21,7 +21,7 @@ void arch_prog_run(struct prog *prog) { -#if ENV_RAMSTAGE && ENV_X86_64 +#if ENV_RAMSTAGE && ENV_X86_64 && CONFIG(PAYLOAD_ELF_X86_32) const uint32_t arg = pointer_to_uint32_safe(prog_entry_arg(prog)); const uint32_t entry = pointer_to_uint32_safe(prog_entry(prog)); diff --git a/util/cbfstool/linux_trampoline.S b/util/cbfstool/linux_trampoline.S index 6a62ff0..c9369e8 100644 --- a/util/cbfstool/linux_trampoline.S +++ b/util/cbfstool/linux_trampoline.S @@ -17,8 +17,10 @@ #define ACPI_RSDP_ADDR 0x70 #define E820_NR_OFFSET 0x1e8 +#define LINUX_CODE64_START 0x200 #define PROTOCOL_VERSION 0x206 -#define LINUX_ENTRY_OFFSET 0x214 +#define LINUX_CODE32_START 0x214 +#define XLOADFLAGS 0x236 #define E820_OFFSET 0x2d0 .trampoline_start: @@ -66,7 +68,8 @@ * the year 2005 (Linux 2.6.11) to hold up to 128 entries. * Assume 128 entries when the boot protocol version is 2.04+. */ -cmpw $0x0204, (LINUX_PARAM_LOC + PROTOCOL_VERSION) +mov $(LINUX_PARAM_LOC + PROTOCOL_VERSION), %edi +cmpw $0x0204, (%edi) jge .e820big /* protocol version >= 2.04 can handle 128 entries of 5 dwords */ cmp $(32 * 5), %eax /* linux wants at most 32 entries of 5 dwords */ jng 1f @@ -81,15 +84,18 @@ mov %eax, %esi mov $5, %edi div %edi -mov %eax, (LINUX_PARAM_LOC + E820_NR_OFFSET) +mov $(LINUX_PARAM_LOC + E820_NR_OFFSET), %edi +mov %eax, (%edi) mov %esi, %eax xchg %eax, %ecx lea 8(%ebx), %esi /* e820 data source */ mov $(LINUX_PARAM_LOC + E820_OFFSET), %edi rep movsl xchg %eax, %ecx + /* e820 and LB_TAG_MEMORY type don't fully match: remap unknown type to 2, reserved memory */ -mov (LINUX_PARAM_LOC + E820_NR_OFFSET), %eax +mov $(LINUX_PARAM_LOC + E820_NR_OFFSET), %edi +mov (%edi), %eax mov $(LINUX_PARAM_LOC + E820_OFFSET), %edi .test_e820_entry: cmp $0, %eax @@ -99,7 +105,7 @@ /* Fixup the type to 2, reserved memory */ mov $2, 16(%edi) .next_e820_entry: -dec %eax +sub $1, %eax add $20, %edi jmp .test_e820_entry @@ -108,16 +114,18 @@ jne .testFramebuffer mov 8(%ebx), %eax -mov %eax, (LINUX_PARAM_LOC + ACPI_RSDP_ADDR) +mov $(LINUX_PARAM_LOC + ACPI_RSDP_ADDR), %edi +mov %eax, (%edi) mov 12(%ebx), %eax -mov %eax, (LINUX_PARAM_LOC + ACPI_RSDP_ADDR + 4) +mov %eax, 4(%edi) jmp .endScan .testFramebuffer: cmp $CB_TAG_FRAMEBUFFER, (%ebx) jne .endScan -cmpw $0x020f, (LINUX_PARAM_LOC + PROTOCOL_VERSION) +mov $(LINUX_PARAM_LOC + PROTOCOL_VERSION), %edi +cmpw $0x020f, (%edi) jge .framebufferSetup /* protocol version >= 2.15 can handle 64-bit address */ cmpl $0, 0x0c(%ebx) /* check if upper 32-bit of framebuffer address are 0 */ jne .endScan @@ -146,7 +154,7 @@ mov 0x1b(%ebx, %esi, 2), %ax rol %ax /* Order is reversed for Linux, hence swap. */ mov %ax, 0x24(%edi, %esi, 2) -dec %esi +sub $1, %esi jnz 1b #define VIDEO_CAPABILITY_64BIT_BASE (1 << 1) @@ -157,11 +165,13 @@ .endScan: add 4(%ebx), %ebx -dec %ecx +sub $1, %ecx jnz .tableScan /* Setup basic code and data segment selectors for Linux ** +** Keep in sync with arch/x86/include/arch/ram_segs.h! +** ** Flat code segment descriptor: ** selector: 0x10 ** base : 0x00000000 @@ -174,22 +184,71 @@ ** limit : 0xFFFFFFFF ** type : data, read/write ** +** Flat x64 code segment descriptor: +** selector: 0x48 +** base : 0x00000000 +** limit : 0xFFFFFFFF +** type : data, read/write +** ** Use TRAMPOLINE_ENTRY_LOC as a scratchpad. */ mov $TRAMPOLINE_ENTRY_LOC, %eax -movl $0x0000ffff, 16(%eax) // Set up the 2 new descriptors +movl $0x0000ffff, 16(%eax) // Set up the 3 new descriptors movl $0x00cf9b00, 20(%eax) movl $0x0000ffff, 24(%eax) movl $0x00cf9300, 28(%eax) -movb $0x2b, 0(%eax) // Set the size +movl $0x0000ffff, 72(%eax) +movl $0x00af9b00, 76(%eax) + +movb $0x4f, 0(%eax) // Set the size movl %eax, 2(%eax) // Set pointer to new GDT lgdt (%eax) // Load it /* finally: jump to kernel */ mov $LINUX_PARAM_LOC, %esi -jmp *(LINUX_PARAM_LOC + LINUX_ENTRY_OFFSET) +mov $(LINUX_PARAM_LOC + LINUX_CODE64_START), %eax +jmp *(%eax) +/* Check if CPU supports long mode */ +mov $0x80000001, %eax +cpuid +btl $29, %edx +jnc .long_mode_check_done + +/* Paging enabled? */ +mov %cr0, %eax +btl $31, %eax +jnc .long_mode_check_done + +/* Long mode enabled? */ +mov $0xC0000080, %ecx +rdmsr +btl $8, %eax +jnc .long_mode_check_done + +/* protocol version >= 2.12 provides xloadflags */ +mov $(LINUX_PARAM_LOC + PROTOCOL_VERSION), %edi +cmpw $0x020c, (%edi) +jl .long_mode_check_done + +/* XLF_KERNEL_64 bit set? */ +mov $(LINUX_PARAM_LOC + XLOADFLAGS), %edi +btl $0, (%edi) +jnc .long_mode_check_done + +/* finally: jump to kernel */ +mov $LINUX_PARAM_LOC, %esi +mov $(LINUX_PARAM_LOC + LINUX_CODE64_START), %eax +jmp *(%eax) + +.long_mode_check_done: + +/* finally: jump to kernel */ +mov $LINUX_PARAM_LOC, %esi +mov $(LINUX_PARAM_LOC + LINUX_CODE32_START), %eax +jmp *(%eax) + 2: hlt jmp 2b diff --git a/util/cbfstool/linux_trampoline.c b/util/cbfstool/linux_trampoline.c index 13c0edb..f245a6a 100644 --- a/util/cbfstool/linux_trampoline.c +++ b/util/cbfstool/linux_trampoline.c @@ -3,27 +3,33 @@ unsigned char trampoline[] = { 0xfc, 0x31, 0xd2, 0xb9, 0x00, 0x00, 0x00, 0x00, 0xbb, 0x00, 0x00, 0x01, 0x00, 0x01, 0xcb, 0x8b, 0x01, 0x3d, 0x4c, 0x42, 0x49, 0x4f, 0x74, 0x07, 0x83, 0xc1, 0x10, 0x39, 0xcb, 0x75, 0xe9, 0x39, - 0xcb, 0x0f, 0x84, 0x47, 0x01, 0x00, 0x00, 0x8b, 0x59, 0x04, 0x01, 0xcb, 0x8b, 0x49, 0x14, 0x83, - 0x3b, 0x11, 0x75, 0x05, 0x8b, 0x4b, 0x08, 0xeb, 0xcf, 0x83, 0x3b, 0x01, 0x75, 0x70, 0x8b, 0x43, - 0x04, 0x83, 0xe8, 0x08, 0xc1, 0xe8, 0x02, 0x66, 0x81, 0x3d, 0x06, 0x02, 0x09, 0x00, 0x04, 0x02, - 0x7d, 0x0e, 0x3d, 0xa0, 0x00, 0x00, 0x00, 0x7e, 0x13, 0xb8, 0xa0, 0x00, 0x00, 0x00, 0xeb, 0x0c, - 0x3d, 0x80, 0x02, 0x00, 0x00, 0x7e, 0x05, 0xb8, 0x80, 0x02, 0x00, 0x00, 0x89, 0xc6, 0xbf, 0x05, - 0x00, 0x00, 0x00, 0xf7, 0xf7, 0xa3, 0xe8, 0x01, 0x09, 0x00, 0x89, 0xf0, 0x91, 0x8d, 0x73, 0x08, - 0xbf, 0xd0, 0x02, 0x09, 0x00, 0xf3, 0xa5, 0x91, 0xa1, 0xe8, 0x01, 0x09, 0x00, 0xbf, 0xd0, 0x02, - 0x09, 0x00, 0x83, 0xf8, 0x00, 0x0f, 0x84, 0x94, 0x00, 0x00, 0x00, 0x83, 0x7f, 0x10, 0x0c, 0x7e, - 0x07, 0xc7, 0x47, 0x10, 0x02, 0x00, 0x00, 0x00, 0x48, 0x83, 0xc7, 0x14, 0xeb, 0xe4, 0x83, 0x3b, - 0x43, 0x75, 0x12, 0x8b, 0x43, 0x08, 0xa3, 0x70, 0x00, 0x09, 0x00, 0x8b, 0x43, 0x0c, 0xa3, 0x74, - 0x00, 0x09, 0x00, 0xeb, 0x6a, 0x83, 0x3b, 0x12, 0x75, 0x65, 0x66, 0x81, 0x3d, 0x06, 0x02, 0x09, - 0x00, 0x0f, 0x02, 0x7d, 0x06, 0x83, 0x7b, 0x0c, 0x00, 0x75, 0x54, 0xbf, 0x00, 0x00, 0x09, 0x00, - 0x8b, 0x43, 0x08, 0x89, 0x47, 0x18, 0x8b, 0x43, 0x0c, 0x89, 0x47, 0x3a, 0x8b, 0x43, 0x10, 0x66, - 0x89, 0x47, 0x12, 0x8b, 0x43, 0x14, 0x66, 0x89, 0x47, 0x14, 0x8b, 0x53, 0x18, 0x66, 0x89, 0x57, - 0x24, 0xf7, 0xe2, 0x89, 0x47, 0x1c, 0x66, 0x0f, 0xb6, 0x43, 0x1c, 0x66, 0x89, 0x47, 0x16, 0xbe, - 0x04, 0x00, 0x00, 0x00, 0x66, 0x8b, 0x44, 0x73, 0x1b, 0x66, 0xd1, 0xc0, 0x66, 0x89, 0x44, 0x77, - 0x24, 0x4e, 0x75, 0xf0, 0xc7, 0x47, 0x36, 0x02, 0x00, 0x00, 0x00, 0xc6, 0x47, 0x0f, 0x70, 0x03, - 0x5b, 0x04, 0x49, 0x0f, 0x85, 0xf6, 0xfe, 0xff, 0xff, 0xb8, 0x00, 0x00, 0x04, 0x00, 0xc7, 0x40, - 0x10, 0xff, 0xff, 0x00, 0x00, 0xc7, 0x40, 0x14, 0x00, 0x9b, 0xcf, 0x00, 0xc7, 0x40, 0x18, 0xff, - 0xff, 0x00, 0x00, 0xc7, 0x40, 0x1c, 0x00, 0x93, 0xcf, 0x00, 0xc6, 0x00, 0x2b, 0x89, 0x40, 0x02, - 0x0f, 0x01, 0x10, 0xbe, 0x00, 0x00, 0x09, 0x00, 0xff, 0x25, 0x14, 0x02, 0x09, 0x00, 0xf4, 0xeb, - 0xfd + 0xcb, 0x0f, 0x84, 0xb4, 0x01, 0x00, 0x00, 0x8b, 0x59, 0x04, 0x01, 0xcb, 0x8b, 0x49, 0x14, 0x83, + 0x3b, 0x11, 0x75, 0x05, 0x8b, 0x4b, 0x08, 0xeb, 0xcf, 0x83, 0x3b, 0x01, 0x75, 0x77, 0x8b, 0x43, + 0x04, 0x83, 0xe8, 0x08, 0xc1, 0xe8, 0x02, 0xbf, 0x06, 0x02, 0x09, 0x00, 0x66, 0x81, 0x3f, 0x04, + 0x02, 0x7d, 0x0e, 0x3d, 0xa0, 0x00, 0x00, 0x00, 0x7e, 0x13, 0xb8, 0xa0, 0x00, 0x00, 0x00, 0xeb, + 0x0c, 0x3d, 0x80, 0x02, 0x00, 0x00, 0x7e, 0x05, 0xb8, 0x80, 0x02, 0x00, 0x00, 0x89, 0xc6, 0xbf, + 0x05, 0x00, 0x00, 0x00, 0xf7, 0xf7, 0xbf, 0xe8, 0x01, 0x09, 0x00, 0x89, 0x07, 0x89, 0xf0, 0x91, + 0x8d, 0x73, 0x08, 0xbf, 0xd0, 0x02, 0x09, 0x00, 0xf3, 0xa5, 0x91, 0xbf, 0xe8, 0x01, 0x09, 0x00, + 0x8b, 0x07, 0xbf, 0xd0, 0x02, 0x09, 0x00, 0x83, 0xf8, 0x00, 0x0f, 0x84, 0x99, 0x00, 0x00, 0x00, + 0x83, 0x7f, 0x10, 0x0c, 0x7e, 0x07, 0xc7, 0x47, 0x10, 0x02, 0x00, 0x00, 0x00, 0x83, 0xe8, 0x01, + 0x83, 0xc7, 0x14, 0xeb, 0xe2, 0x83, 0x3b, 0x43, 0x75, 0x12, 0x8b, 0x43, 0x08, 0xbf, 0x70, 0x00, + 0x09, 0x00, 0x89, 0x07, 0x8b, 0x43, 0x0c, 0x89, 0x47, 0x04, 0xeb, 0x6d, 0x83, 0x3b, 0x12, 0x75, + 0x68, 0xbf, 0x06, 0x02, 0x09, 0x00, 0x66, 0x81, 0x3f, 0x0f, 0x02, 0x7d, 0x06, 0x83, 0x7b, 0x0c, + 0x00, 0x75, 0x56, 0xbf, 0x00, 0x00, 0x09, 0x00, 0x8b, 0x43, 0x08, 0x89, 0x47, 0x18, 0x8b, 0x43, + 0x0c, 0x89, 0x47, 0x3a, 0x8b, 0x43, 0x10, 0x66, 0x89, 0x47, 0x12, 0x8b, 0x43, 0x14, 0x66, 0x89, + 0x47, 0x14, 0x8b, 0x53, 0x18, 0x66, 0x89, 0x57, 0x24, 0xf7, 0xe2, 0x89, 0x47, 0x1c, 0x66, 0x0f, + 0xb6, 0x43, 0x1c, 0x66, 0x89, 0x47, 0x16, 0xbe, 0x04, 0x00, 0x00, 0x00, 0x66, 0x8b, 0x44, 0x73, + 0x1b, 0x66, 0xd1, 0xc0, 0x66, 0x89, 0x44, 0x77, 0x24, 0x83, 0xee, 0x01, 0x75, 0xee, 0xc7, 0x47, + 0x36, 0x02, 0x00, 0x00, 0x00, 0xc6, 0x47, 0x0f, 0x70, 0x03, 0x5b, 0x04, 0x83, 0xe9, 0x01, 0x0f, + 0x85, 0xea, 0xfe, 0xff, 0xff, 0xb8, 0x00, 0x00, 0x04, 0x00, 0xc7, 0x40, 0x10, 0xff, 0xff, 0x00, + 0x00, 0xc7, 0x40, 0x14, 0x00, 0x9b, 0xcf, 0x00, 0xc7, 0x40, 0x18, 0xff, 0xff, 0x00, 0x00, 0xc7, + 0x40, 0x1c, 0x00, 0x93, 0xcf, 0x00, 0xc7, 0x40, 0x48, 0xff, 0xff, 0x00, 0x00, 0xc7, 0x40, 0x4c, + 0x00, 0x9b, 0xaf, 0x00, 0xc6, 0x00, 0x4f, 0x89, 0x40, 0x02, 0x0f, 0x01, 0x10, 0xbe, 0x00, 0x00, + 0x09, 0x00, 0xb8, 0x00, 0x02, 0x09, 0x00, 0xff, 0x20, 0xb8, 0x01, 0x00, 0x00, 0x80, 0x0f, 0xa2, + 0x0f, 0xba, 0xe2, 0x1d, 0x73, 0x39, 0x0f, 0x20, 0xc0, 0x0f, 0xba, 0xe0, 0x1f, 0x73, 0x30, 0xb9, + 0x80, 0x00, 0x00, 0xc0, 0x0f, 0x32, 0x0f, 0xba, 0xe0, 0x08, 0x73, 0x23, 0xbf, 0x06, 0x02, 0x09, + 0x00, 0x66, 0x81, 0x3f, 0x0c, 0x02, 0x7c, 0x17, 0xbf, 0x36, 0x02, 0x09, 0x00, 0x0f, 0xba, 0x27, + 0x00, 0x73, 0x0c, 0xbe, 0x00, 0x00, 0x09, 0x00, 0xb8, 0x00, 0x02, 0x09, 0x00, 0xff, 0x20, 0xbe, + 0x00, 0x00, 0x09, 0x00, 0xb8, 0x14, 0x02, 0x09, 0x00, 0xff, 0x20, 0xf4, 0xeb, 0xfd }; -unsigned int trampoline_len = 369; +unsigned int trampoline_len = 478; -- To view, visit https://review.coreboot.org/c/coreboot/+/81371?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5e28bc61e759d14140b44ca738a03d4fdff7fdc Gerrit-Change-Number: 81371 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: acpi: Add soc_pci_domain_fill_ssdt
by Arthur Heymans (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Cliff Huang, Jincheng Li, Lance Zhao, Shuo Liu, Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81373?usp=email ) Change subject: acpi: Add soc_pci_domain_fill_ssdt ...................................................................... Patch Set 1: (1 comment) File src/acpi/acpigen_pci_root_resource_producer.c: https://review.coreboot.org/c/coreboot/+/81373/comment/14d69caf_fc999280 : PS1, Line 49: /* SoC specific settings, device object creation could be placed here */ : soc_pci_domain_fill_ssdt(domain); I don't think a soc specific way of creating objects is the way to go. This needs to be synchronised across all soc: Either always create it in SSDT or always have a DSDT and SSDT componenent. -- To view, visit https://review.coreboot.org/c/coreboot/+/81373?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I893eb64c776e78f46737072b475acde5e32a796a Gerrit-Change-Number: 81373 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 09:19:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: arch/ppc64: Add arch as supported by the clang compiler
by Angel Pons (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, ron minnich. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78448?usp=email ) Change subject: arch/ppc64: Add arch as supported by the clang compiler ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78448?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1aacff869663e1db74cd485787d7103b9ec5602e Gerrit-Change-Number: 78448 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 09:04:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: arch/ppc64: Fix inline assembly for clang
by Angel Pons (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Julius Werner, ron minnich. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78446?usp=email ) Change subject: arch/ppc64: Fix inline assembly for clang ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78446?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I516033c69e62dfdb38f83285c156d5527917ad55 Gerrit-Change-Number: 78446 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 09:04:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: cpu/x86/Kconfig: Mark 64bit support as stable
by Arthur Heymans (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Angel Pons, Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Jérémy Compostella, Martin L Roth, Matt DeVillier. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80338?usp=email ) Change subject: cpu/x86/Kconfig: Mark 64bit support as stable ...................................................................... Patch Set 11: (1 comment) File src/arch/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/80338/comment/2c7e4c6a_1dfb86dd : PS6, Line 83: This : is an experimental option: do not enable unless one wants to test it : and has the means to recover a system when coreboot fails to boot. > need to adjust here too? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcf0a1a5097a2d7c064bb709ec0b09ebee13a47d Gerrit-Change-Number: 80338 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 21 Mar 2024 09:04:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes
by Patrick Rudolph (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, TangYiwei, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes ...................................................................... Patch Set 20: (2 comments) File src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/81316/comment/89bb5db8_c27096ac : PS7, Line 166: IEH_EXT_CAP_ID > For these changes, we'd better to update later all at once? Done in https://review.coreboot.org/c/coreboot/+/81369 https://review.coreboot.org/c/coreboot/+/81316/comment/4f0d3109_642347b5 : PS7, Line 187: SYS_BUS_CFG2 > Should be moved into coreboot/src/soc/intel/xeon_sp/ebg. Not sure why this is in CPU headers. Done in https://review.coreboot.org/c/coreboot/+/81370 -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 20 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 09:04:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: cpu/x86/Kconfig: Mark 64bit support as stable
by Arthur Heymans (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Angel Pons, Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Jérémy Compostella, Martin L Roth, Matt DeVillier. Hello Jérémy Compostella, Martin L Roth, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80338?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Code-Review+1 by Matt DeVillier, Code-Review+2 by Martin L Roth, Verified+1 by build bot (Jenkins) Change subject: cpu/x86/Kconfig: Mark 64bit support as stable ...................................................................... cpu/x86/Kconfig: Mark 64bit support as stable With SMM holding page tables itself, we can consider SMM support stable and safe enough for general use. Also update the respective documentation. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ifcf0a1a5097a2d7c064bb709ec0b09ebee13a47d --- M Documentation/arch/x86/index.md M configs/config.emulation_qemu_x86_i440fx_x86_64 M configs/config.foxconn_g41m M configs/config.google_vilboz.x86_64 M configs/config.hp_compaq_8200_elite_sff_pc.x86_64 M configs/config.lenovo_t400_vboot_and_debug M configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi M configs/config.prodrive_hermes.x86_64 M src/arch/x86/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/qemu-x86/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/genoa_poc/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/intel/cannonlake/Kconfig 17 files changed, 23 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/80338/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/80338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcf0a1a5097a2d7c064bb709ec0b09ebee13a47d Gerrit-Change-Number: 80338 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder
by Patrick Rudolph (Code Review) 21 Mar '24

21 Mar '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81370?usp=email ) Change subject: soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder ...................................................................... soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder Move the XHCI code into soc/intel/xeon_sp/ebg where it belongs. TEST: Still builds. Change-Id: I2206ec5426a0f922cfce0e2d968e6806d349a6b2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/ebg/Makefile.mk R src/soc/intel/xeon_sp/ebg/include/soc/xhci.h R src/soc/intel/xeon_sp/ebg/soc_xhci.c M src/soc/intel/xeon_sp/spr/Makefile.mk M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h 5 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/81370/1 diff --git a/src/soc/intel/xeon_sp/ebg/Makefile.mk b/src/soc/intel/xeon_sp/ebg/Makefile.mk index ac73acb..b05c05b 100644 --- a/src/soc/intel/xeon_sp/ebg/Makefile.mk +++ b/src/soc/intel/xeon_sp/ebg/Makefile.mk @@ -2,6 +2,6 @@ bootblock-y += soc_gpio.c soc_pch.c romstage-y += soc_gpio.c soc_pmutil.c soc_pch.c -ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c +ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c soc_xhci.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/ebg/include diff --git a/src/soc/intel/xeon_sp/spr/include/soc/xhci.h b/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h similarity index 100% rename from src/soc/intel/xeon_sp/spr/include/soc/xhci.h rename to src/soc/intel/xeon_sp/ebg/include/soc/xhci.h diff --git a/src/soc/intel/xeon_sp/spr/xhci.c b/src/soc/intel/xeon_sp/ebg/soc_xhci.c similarity index 92% rename from src/soc/intel/xeon_sp/spr/xhci.c rename to src/soc/intel/xeon_sp/ebg/soc_xhci.c index 544ea16..f8aa37b 100644 --- a/src/soc/intel/xeon_sp/spr/xhci.c +++ b/src/soc/intel/xeon_sp/ebg/soc_xhci.c @@ -2,10 +2,13 @@ #include <console/console.h> #include <device/pci.h> -#include <soc/pci_devs.h> +#include <soc/pch_pci_devs.h> #include <soc/xhci.h> #include <types.h> +// XHCI register +#define SYS_BUS_CFG2 0x44 + static uint8_t *get_xhci_bar(void) { const struct resource *res; diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk index 163b5ea..fc8ab17 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.mk +++ b/src/soc/intel/xeon_sp/spr/Makefile.mk @@ -12,7 +12,7 @@ romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c -ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c reset.c +ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c reset.c ramstage-y += crashlog.c ioat.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h index 09953aa..510a67f 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h @@ -122,9 +122,6 @@ #define IIO_DFX_TSWCTL0 0x30c #define IIO_DFX_LCK_CTL 0x504 -// XHCI register -#define SYS_BUS_CFG2 0x44 - /* MSM registers */ #define MSM_BUS 0xF2 #define MSM_DEV 3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81370?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2206ec5426a0f922cfce0e2d968e6806d349a6b2 Gerrit-Change-Number: 81370 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2024