coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: payload/external/edk2: Explicitly define the build arch as X64
by Sean Rhodes (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Arthur Heymans, Benjamin Doron, Martin L Roth, Matt DeVillier, Nicholas Sudsgaard. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80883?usp=email ) Change subject: payload/external/edk2: Explicitly define the build arch as X64 ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5 Gerrit-Change-Number: 80883 Gerrit-PatchSet: 7 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 21 Mar 2024 15:29:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[NoOp] Change in coreboot[main]: mb/google/zork: Update APCB to increase UMA size to 128MB
by Matt DeVillier (Code Review) 21 Mar '24

21 Mar '24

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81364?usp=email ) Change subject: mb/google/zork: Update APCB to increase UMA size to 128MB ...................................................................... mb/google/zork: Update APCB to increase UMA size to 128MB The previous value of 32MB was set to meet Google's ChromeOS reqs, but hampers real-world performance in Linux/Windows, so increase it to 128MB to match the "auto" default for the Picasso UEFI firmware. TEST=build/boot Windows on google/zork (morphius), verify UMA set to 128MB. Change-Id: I8c6487a4cb8155f826d20fd3ceca87859829199c Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81364 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M src/mainboard/google/zork/data.apcb 1 file changed, 0 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Martin L Roth: Looks good to me, approved Jason Glenesk: Looks good to me, approved diff --git a/src/mainboard/google/zork/data.apcb b/src/mainboard/google/zork/data.apcb index f7a3e78..ee12694 100644 --- a/src/mainboard/google/zork/data.apcb +++ b/src/mainboard/google/zork/data.apcb Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/81364?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c6487a4cb8155f826d20fd3ceca87859829199c Gerrit-Change-Number: 81364 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge)
by Matt DeVillier (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Joel Linn, Nicholas Chin. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81368?usp=email ) Change subject: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge) ...................................................................... Patch Set 2: Code-Review+1 (9 comments) File src/mainboard/hp/pro_3500_series/Kconfig: https://review.coreboot.org/c/coreboot/+/81368/comment/bfa0f16f_4fdc18c7 : PS2, Line 37: # FIXME: check this if checked, remove fixme File src/mainboard/hp/pro_3500_series/acpi_tables.c: https://review.coreboot.org/c/coreboot/+/81368/comment/7cb94ace_9340ecfb : PS2, Line 6: /* FIXME: check this function. */ if this is from autoport and you've verified the temps, can probably remove the comment File src/mainboard/hp/pro_3500_series/common_defines.h: https://review.coreboot.org/c/coreboot/+/81368/comment/e8ce5707_ce1b335d : PS2, Line 8: #define IT8772F_BASE 0x2e : #define EC_DEV PNP_DEV(IT8772F_BASE, IT8772F_EC) : #define GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) tab align for readability File src/mainboard/hp/pro_3500_series/devicetree.cb: https://review.coreboot.org/c/coreboot/+/81368/comment/01a409a2_43194d11 : PS2, Line 3: register "gpu_cpu_backlight" = "0x00000000" : register "gpu_dp_b_hotplug" = "4" : register "gpu_dp_c_hotplug" = "0" : register "gpu_dp_d_hotplug" = "0" : register "gpu_panel_port_select" = "0" : register "gpu_panel_power_backlight_off_delay" = "0" : register "gpu_panel_power_backlight_on_delay" = "0" : register "gpu_panel_power_cycle_delay" = "4" : register "gpu_panel_power_down_delay" = "0" : register "gpu_panel_power_up_delay" = "0" : register "gpu_pch_backlight" = "0x00000000" these values look very suspect - the fixme comment might be applicable here https://review.coreboot.org/c/coreboot/+/81368/comment/cc524ca9_2671f541 : PS2, Line 78: #register "gpio_set1" = "0x00" : #register "gpio_set2" = "0xff" : #register "gpio_set3" = "0x00" : #register "gpio_set4" = "0x00" : #register "gpio_set5" = "0x00" can be removed since commented out File src/mainboard/hp/pro_3500_series/early_init.c: https://review.coreboot.org/c/coreboot/+/81368/comment/3ba52bb3_a81d1465 : PS2, Line 18: FIXME: Unknown current: RCBA(0x350c)=0x350c address fixme comments https://review.coreboot.org/c/coreboot/+/81368/comment/1f6682c0_9d1657f0 : PS2, Line 42: // ite_kill_watchdog(GPIO_DEV); remove commented line File src/mainboard/hp/pro_3500_series/mainboard.c: https://review.coreboot.org/c/coreboot/+/81368/comment/934e32f2_8a5af0d3 : PS2, Line 9: * FIXME: untested. */ tested? handler needed at all? File src/superio/ite/common/early_serial.c: PS2: > I would split the changes to src/superio/ite/common into a separate patch 2nd -- To view, visit https://review.coreboot.org/c/coreboot/+/81368?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf793fe915096cf2553572964faec5c7f8526b9a Gerrit-Change-Number: 81368 Gerrit-PatchSet: 2 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 15:18:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt
by Patrick Rudolph (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81374?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt ...................................................................... Patch Set 4: Code-Review+2 (2 comments) File src/soc/intel/xeon_sp/gnr/soc_acpi.c: https://review.coreboot.org/c/coreboot/+/81374/comment/8b2edb97_8c436baa : PS4, Line 83: acpigen_write_scope acpigen_write_scope(acpi_device_scope(domain)); https://review.coreboot.org/c/coreboot/+/81374/comment/34ec8d9a_a0b191e6 : PS4, Line 87: Those tabs after * are confusing. The `acpigen_` functions are trivial enough to not need any comments. -- To view, visit https://review.coreboot.org/c/coreboot/+/81374?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c Gerrit-Change-Number: 81374 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 14:40:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_acpigen_write_OSC_pci_domain
by Patrick Rudolph (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81375?usp=email ) Change subject: soc/intel/xeon_sp: Add soc_acpigen_write_OSC_pci_domain ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/acpi.c: https://review.coreboot.org/c/coreboot/+/81375/comment/0c2780dd_e37ab979 : PS3, Line 175: static void soc_acpigen_OSC_handle_pcie_request(const struct device *domain); > I made an attempt but not succeed, because this code refers to is_cxl_domain/is_pcie_domain, which i […] That can be passed as argument: `const bool is_cxl_domain` -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 14:35:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Kconfig: Make GBD_STUB and long mode mutually exclusive
by Arthur Heymans (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Jérémy Compostella. Hello Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81379?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Kconfig: Make GBD_STUB and long mode mutually exclusive ...................................................................... Kconfig: Make GBD_STUB and long mode mutually exclusive GDB debugging is not implemented with x86 long mode. Change-Id: Icaf7d0763829d5badf73d38bb8fc3d36cfe18964 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/c_start.S M src/arch/x86/exception.c 3 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/81379/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81379?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaf7d0763829d5badf73d38bb8fc3d36cfe18964 Gerrit-Change-Number: 81379 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/lenovo/s230u: Fix compiling for 64bit mode
by Patrick Rudolph (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Alexander Couzens, Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81381?usp=email ) Change subject: mb/lenovo/s230u: Fix compiling for 64bit mode ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81381?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide2827ec1b86dcbd804be9f3269c6c968cb4257b Gerrit-Change-Number: 81381 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Thu, 21 Mar 2024 13:25:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/butterfly: Fix compiling for 64bit mode
by Patrick Rudolph (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81380?usp=email ) Change subject: mb/google/butterfly: Fix compiling for 64bit mode ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81380?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieaaba5b36796d97449896b8475744a21f01e93d1 Gerrit-Change-Number: 81380 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 21 Mar 2024 13:25:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: cpu/x86/Kconfig: Mark 64bit support as stable
by Patrick Rudolph (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Jérémy Compostella, Martin L Roth, Matt DeVillier. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80338?usp=email ) Change subject: cpu/x86/Kconfig: Mark 64bit support as stable ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcf0a1a5097a2d7c064bb709ec0b09ebee13a47d Gerrit-Change-Number: 80338 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 21 Mar 2024 13:24:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/dptf: Add DCFG support
by Felix Held (Code Review) 21 Mar '24

21 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78386?usp=email ) Change subject: drivers/intel/dptf: Add DCFG support ...................................................................... drivers/intel/dptf: Add DCFG support After final production, it's possible by setting particular bit using DCFG the OEM/ODM locks down thermal tuning beyond what is usually done on the given platform. In that case user space calibration tools should not try to adjust the thermal configuration of the system. By adding new DCFG (Device Configuration) it allows the OEM/ODM to control this thermal tuning mechanism. They can configure it by adding dcfg config under overridetree.cb file. The default value for all bits is 0 to ensure default behavior and backwards compatibility. For an example if Bit 0 being set represents Generic DTT UI access control is disabled and Bit 2 being set represents DTT shell access control is disabled. Each bit represents different configuration access control for DTT as per BIOS specification document #640237. It also gives the provision for user space to check the current mode. This mode value is based on BIOS specification document number #640237. BUG=b:272382080 TEST=Build, boot on rex board and dump SSDT to check DCFG value. Also, verified the newly added sysfs attribute "production_mode" present under /sys/bus/platform/devices/INTC1042:00 path. Change-Id: I507c4d6eee565d39b2f42950d888d110ab94de64 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78386 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/intel/dptf/chip.h M src/drivers/intel/dptf/dptf.c 2 files changed, 10 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/intel/dptf/chip.h b/src/drivers/intel/dptf/chip.h index 9bbf11f..7f93182 100644 --- a/src/drivers/intel/dptf/chip.h +++ b/src/drivers/intel/dptf/chip.h @@ -73,6 +73,9 @@ /* Rest of platform Power */ uint32_t prop; + /* Device Configuration */ + uint32_t dcfg; + bool dptf_multifan_support; }; diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index f313540..5bbbc1b 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -158,6 +158,12 @@ acpigen_emit_byte(ARG0_OP); acpigen_write_method_end(); } + +static void write_dcfg_variable(const struct drivers_intel_dptf_config *config) +{ + acpigen_write_name_integer("DCFG", config->dcfg); +} + /* \_SB.DPTF */ static void write_oem_variables(const struct drivers_intel_dptf_config *config) { @@ -520,6 +526,7 @@ } else write_fan(config, platform_info, DPTF_FAN); + write_dcfg_variable(config); write_oem_variables(config); write_imok(); write_generic_devices(config, platform_info); -- To view, visit https://review.coreboot.org/c/coreboot/+/78386?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I507c4d6eee565d39b2f42950d888d110ab94de64 Gerrit-Change-Number: 78386 Gerrit-PatchSet: 8 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit March 2024