coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_acpigen_write_OSC_pci_domain
by Shuo Liu (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81375?usp=email ) Change subject: soc/intel/xeon_sp: Add soc_acpigen_write_OSC_pci_domain ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/acpi.c: https://review.coreboot.org/c/coreboot/+/81375/comment/a30317b5_90344171 : PS3, Line 175: static void soc_acpigen_OSC_handle_pcie_request(const struct device *domain); > there's nothing soc specific on this code. […] I made an attempt but not succeed, because this code refers to is_cxl_domain/is_pcie_domain, which is xeon-sp specific. Maybe we could make it stay with xeon-sp as of now since only xeon-sp benefit from this feature, other platforms (client, embedded, et al) can still use static generation. -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 12:06:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Remove unlock_pam_regions
by Shuo Liu (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81349?usp=email ) Change subject: soc/intel/xeon_sp: Remove unlock_pam_regions ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81349/comment/cbc1eae8_9f9f76a6 : PS3, Line 9: unlock_pam_regions > Since this is ancient code, is it needed on older platforms like SKX or CPX? I'm not sure, since we are not test SKX/CPX. For SKX, we are okay to drop. Hence, the only open is CPX. Do you want me to move the codes into CPX's SoC dir? -- To view, visit https://review.coreboot.org/c/coreboot/+/81349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018 Gerrit-Change-Number: 81349 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 12:04:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation
by Shuo Liu (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81377?usp=email to look at the new patch set (#2). Change subject: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation ...................................................................... soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation Domain SSDT is dyanmically generated by soc_pci_domain_fill_ssdt. SPR has 2 SKUs, XCC and MCC. Dyanmic domain SSDT generation could better fit both. One possible side-effect might be the extra performance cost for generating these tables, which should not bring big impact on high performance server CPUs. TEST=intel/archercity CRB Linux ACPI host bridge parsing logs are kept the same before and after, with some minor issue fixed. Change-Id: Icc5843feadc840d87c49b2aa4259716264520dba Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h D src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl D src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl D src/soc/intel/xeon_sp/spr/acpi/iiostack.asl D src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl D src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl M src/soc/intel/xeon_sp/spr/acpi/uncore.asl M src/soc/intel/xeon_sp/spr/soc_acpi.c 9 files changed, 97 insertions(+), 322 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/81377/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81377?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc5843feadc840d87c49b2aa4259716264520dba Gerrit-Change-Number: 81377 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_acpigen_write_OSC_pci_domain
by Shuo Liu (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81375?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Patrick Rudolph, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add soc_acpigen_write_OSC_pci_domain ...................................................................... soc/intel/xeon_sp: Add soc_acpigen_write_OSC_pci_domain Add dynamic PCI domain _OSC ASL generation codes, supporting both PCIe and CXL domains. Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/gnr/soc_acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h 3 files changed, 330 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81375/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt
by Shuo Liu (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81374?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt ...................................................................... soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt Domain device objects are created with HID/CID/UID. GNR codes run with dynamic domain SSDT generation to fit for both GraniteRapids and SierraForest SoCs. Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/gnr/soc_acpi.c 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/81374/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81374?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c Gerrit-Change-Number: 81374 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: acpi: Add soc_pci_domain_fill_ssdt
by Shuo Liu (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Cliff Huang, Jincheng Li, Lance Zhao, Shuo Liu, Tim Wawrzynczak. Hello Cliff Huang, Jincheng Li, Lance Zhao, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81373?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: acpi: Add soc_pci_domain_fill_ssdt ...................................................................... acpi: Add soc_pci_domain_fill_ssdt soc_pci_domain_fill_ssdt does SoC layer domain SSDT generation, e.g. device object creation and some SoC specific methods. SoC specific generation is placed ahead of generic content generation, so that the device object could be created before being referenced in the generic contents. A default null weak implementation is provided. For platforms with static domain SoC SSDT generation, just use the default weak implementation. For platforms with dyanmic domain SoC SSDT generation, the default method should be overridden. Dynamic domain SSDT generation is not a must. It would be helpful for some SoC codes to better fit mulitple SKUs and with strong CPU performance to run table generation logics. Change-Id: I893eb64c776e78f46737072b475acde5e32a796a Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/acpi/acpigen_pci_root_resource_producer.c M src/include/acpi/acpigen_pci.h 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/81373/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81373?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I893eb64c776e78f46737072b475acde5e32a796a Gerrit-Change-Number: 81373 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: vendorcode/cavium: Use unsigned integers in struct bitfields
by Felix Singer (Code Review) 21 Mar '24

21 Mar '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80638?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: vendorcode/cavium: Use unsigned integers in struct bitfields ...................................................................... vendorcode/cavium: Use unsigned integers in struct bitfields Bitfields with signed integers are not valid C code. This fixes compilation with clang v16.0.6. Change-Id: I0b2add2f1078a88347fea7dc65d422d0e5a210a1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80638 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/cavium/include/bdk/libbdk-hal/if/bdk-if.h 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/vendorcode/cavium/include/bdk/libbdk-hal/if/bdk-if.h b/src/vendorcode/cavium/include/bdk/libbdk-hal/if/bdk-if.h index b77aa2a..499a6a4 100644 --- a/src/vendorcode/cavium/include/bdk/libbdk-hal/if/bdk-if.h +++ b/src/vendorcode/cavium/include/bdk/libbdk-hal/if/bdk-if.h @@ -113,8 +113,8 @@ uint64_t reserved2 : 32; unsigned speed : 24; unsigned lanes : 6; - int full_duplex : 1; - int up : 1; + unsigned full_duplex : 1; + unsigned up : 1; } s; } bdk_if_link_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/80638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0b2add2f1078a88347fea7dc65d422d0e5a210a1 Gerrit-Change-Number: 80638 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: [WIP]arch/x86: Support x86_64 kernel entry
by Patrick Rudolph (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Jérémy Compostella. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81371?usp=email ) Change subject: [WIP]arch/x86: Support x86_64 kernel entry ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Probably a better approach would be to use https://review.coreboot.org/c/coreboot/+/63716 -- To view, visit https://review.coreboot.org/c/coreboot/+/81371?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5e28bc61e759d14140b44ca738a03d4fdff7fdc Gerrit-Change-Number: 81371 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 09:54:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: [NOTFORMERGE] build all x86 boards with 64bit
by Arthur Heymans (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Jérémy Compostella. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81378?usp=email ) Change subject: [NOTFORMERGE] build all x86 boards with 64bit ...................................................................... [NOTFORMERGE] build all x86 boards with 64bit Let's see if there is fallout? Change-Id: Iabdaf8867a0a9f147d06528f421a95babf2cbcf1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/81378/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index d2ae320..c720cd2 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -76,6 +76,7 @@ bool "Run coreboot in long (64-bit) mode" depends on HAVE_X86_64_SUPPORT select ARCH_ALL_STAGES_X86_64 + default y help When set, most of coreboot runs in long (64-bit) mode instead of the usual protected flat (32-bit) mode. 64-bit CPUs and OSes can be used -- To view, visit https://review.coreboot.org/c/coreboot/+/81378?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabdaf8867a0a9f147d06528f421a95babf2cbcf1 Gerrit-Change-Number: 81378 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: cpu/x86/Kconfig: Mark 64bit support as stable
by Arthur Heymans (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Jérémy Compostella, Martin L Roth, Matt DeVillier. Hello Angel Pons, Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Martin L Roth, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80338?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: cpu/x86/Kconfig: Mark 64bit support as stable ...................................................................... cpu/x86/Kconfig: Mark 64bit support as stable With SMM holding page tables itself, we can consider SMM support stable and safe enough for general use. Also update the respective documentation. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ifcf0a1a5097a2d7c064bb709ec0b09ebee13a47d --- M Documentation/arch/x86/index.md M configs/config.emulation_qemu_x86_i440fx_x86_64 M configs/config.foxconn_g41m M configs/config.google_vilboz.x86_64 M configs/config.hp_compaq_8200_elite_sff_pc.x86_64 M configs/config.lenovo_t400_vboot_and_debug M configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi M configs/config.prodrive_hermes.x86_64 M src/arch/x86/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/qemu-x86/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/genoa_poc/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/intel/cannonlake/Kconfig 17 files changed, 24 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/80338/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/80338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcf0a1a5097a2d7c064bb709ec0b09ebee13a47d Gerrit-Change-Number: 80338 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2024