coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: vc/wuffs: Fix compiling for 64bit and clang
by Arthur Heymans (Code Review) 21 Mar '24

21 Mar '24

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/81382?usp=email ) Change subject: vc/wuffs: Fix compiling for 64bit and clang ...................................................................... vc/wuffs: Fix compiling for 64bit and clang Disable a warning about always true comparison of integers. Change-Id: I23ef29010d60bd543e48af032795ec9fc2ff9ecb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/wuffs/wuffs-v0.4.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/81382/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I23ef29010d60bd543e48af032795ec9fc2ff9ecb Gerrit-Change-Number: 81382 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: vc/wffs: Fix compiling for 64bit and clang
by Arthur Heymans (Code Review) 21 Mar '24

21 Mar '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81382?usp=email ) Change subject: vc/wffs: Fix compiling for 64bit and clang ...................................................................... vc/wffs: Fix compiling for 64bit and clang Disable a warning about always true comparison of integers. Change-Id: I23ef29010d60bd543e48af032795ec9fc2ff9ecb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/wuffs/wuffs-v0.4.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/81382/1 diff --git a/src/vendorcode/wuffs/wuffs-v0.4.c b/src/vendorcode/wuffs/wuffs-v0.4.c index bce9eb9..32a8b08 100644 --- a/src/vendorcode/wuffs/wuffs-v0.4.c +++ b/src/vendorcode/wuffs/wuffs-v0.4.c @@ -20,6 +20,9 @@ #pragma GCC diagnostic ignored "-Wunreachable-code" #pragma GCC diagnostic ignored "-Wunused-function" #pragma GCC diagnostic ignored "-Wunused-parameter" +#if SIZE_MAX == 0xffffffffffffffff && defined(__clang__) +#pragma GCC diagnostic ignored "-Wtautological-type-limit-compare" +#endif #if defined(__cplusplus) #pragma GCC diagnostic ignored "-Wold-style-cast" #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/81382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I23ef29010d60bd543e48af032795ec9fc2ff9ecb Gerrit-Change-Number: 81382 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/lenovo/s230u: Fix compiling for 64bit mode
by Arthur Heymans (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Alexander Couzens. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81381?usp=email ) Change subject: mb/lenovo/s230u: Fix compiling for 64bit mode ...................................................................... mb/lenovo/s230u: Fix compiling for 64bit mode This fixes the warning when an integer is cast to a pointer of a different size. Change-Id: Ide2827ec1b86dcbd804be9f3269c6c968cb4257b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/s230u/ec.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/81381/1 diff --git a/src/mainboard/lenovo/s230u/ec.h b/src/mainboard/lenovo/s230u/ec.h index 273f58b..7ef06e2 100644 --- a/src/mainboard/lenovo/s230u/ec.h +++ b/src/mainboard/lenovo/s230u/ec.h @@ -5,7 +5,7 @@ void lenovo_s230u_ec_init(void); -#define ECMM(x) (*((volatile u8 *)(CONFIG_EC_BASE_ADDRESS + x))) +#define ECMM(x) (*((volatile u8 *)(uintptr_t)(CONFIG_EC_BASE_ADDRESS + x))) #define ec_mm_read(addr) (ECMM(0x100 + addr)) #define ec_mm_write(addr, data) (ECMM(0x100 + addr) = data) #define ec_mm_set_bit(addr, bit) (ECMM(0x100 + addr) |= 1 << bit) -- To view, visit https://review.coreboot.org/c/coreboot/+/81381?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide2827ec1b86dcbd804be9f3269c6c968cb4257b Gerrit-Change-Number: 81381 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/butterfly: Fix compiling for 64bit mode
by Arthur Heymans (Code Review) 21 Mar '24

21 Mar '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81380?usp=email ) Change subject: mb/google/butterfly: Fix compiling for 64bit mode ...................................................................... mb/google/butterfly: Fix compiling for 64bit mode Change-Id: Ieaaba5b36796d97449896b8475744a21f01e93d1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/butterfly/mainboard.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/81380/1 diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index ac0f57b..820889a 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -49,7 +49,7 @@ } static int get_mac_address(u32 *high_dword, u32 *low_dword, - u32 search_address, u32 search_length) + uintptr_t search_address, u32 search_length) { char key[] = "ethernet_mac"; unsigned int offset; @@ -118,7 +118,7 @@ } } -static void program_keyboard_type(u32 search_address, u32 search_length) +static void program_keyboard_type(uintptr_t search_address, u32 search_length) { char key[] = "keyboard_layout"; char kbd_jpn[] = "xkb:jp::jpn"; -- To view, visit https://review.coreboot.org/c/coreboot/+/81380?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieaaba5b36796d97449896b8475744a21f01e93d1 Gerrit-Change-Number: 81380 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: Kconfig: Make GBD_STUB and long mode mutually exclusive
by Arthur Heymans (Code Review) 21 Mar '24

21 Mar '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81379?usp=email ) Change subject: Kconfig: Make GBD_STUB and long mode mutually exclusive ...................................................................... Kconfig: Make GBD_STUB and long mode mutually exclusive The GDB setup does not compile and was never tested with long mode. Change-Id: Icaf7d0763829d5badf73d38bb8fc3d36cfe18964 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/c_start.S 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/81379/1 diff --git a/src/Kconfig b/src/Kconfig index 3a9a4e8..78ff0a8 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1015,7 +1015,8 @@ config GDB_STUB bool "GDB debugging support" default n - depends on DRIVERS_UART +# FIXME Not correctly implemented in long mode + depends on DRIVERS_UART && !USE_X86_64_SUPPORT help If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/x86/c_start.S for details. diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 6bea8db..266d8f0 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -129,6 +129,7 @@ gdb_stub_breakpoint: #if ENV_X86_64 pop %rax /* Return address */ + /* FIXME: instructions below are not valid in long mode */ pushfl push %cs push %rax /* Return address */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81379?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaf7d0763829d5badf73d38bb8fc3d36cfe18964 Gerrit-Change-Number: 81379 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp/spr: Drop unused defines
by Shuo Liu (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81369?usp=email ) Change subject: soc/intel/xeon_sp/spr: Drop unused defines ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: will test archercity as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/81369?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I507b08a62ebeae14a1e63f4340b0592605a32477 Gerrit-Change-Number: 81369 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 12:36:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder
by Shuo Liu (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81370?usp=email ) Change subject: soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Will test archercity as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/81370?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2206ec5426a0f922cfce0e2d968e6806d349a6b2 Gerrit-Change-Number: 81370 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 12:35:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt
by Shuo Liu (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81374?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81374/comment/29b717df_ad475bab : PS2, Line 9: Domain > What's the reason to no longer provide this as static DSDT? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81374?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c Gerrit-Change-Number: 81374 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 12:15:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt
by Shuo Liu (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81374?usp=email to look at the new patch set (#4). Change subject: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt ...................................................................... soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt Domain device objects are created with HID/CID/UID. Dynamic domain SSDT generation could benefit the support of SoCs with multiple SKUs, or the case where one set of codes supports multiple SoCs. One possible side-effect might be the extra performance cost for generating these tables, which should not bring big impact on high performance server CPUs. GNR codes run with dynamic domain SSDT generation to fit for both GraniteRapids and SierraForest SoCs. Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/gnr/soc_acpi.c 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/81374/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81374?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c Gerrit-Change-Number: 81374 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: acpi: Add soc_pci_domain_fill_ssdt
by Shuo Liu (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Cliff Huang, Jincheng Li, Lance Zhao, Tim Wawrzynczak. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81373?usp=email ) Change subject: acpi: Add soc_pci_domain_fill_ssdt ...................................................................... Patch Set 2: (1 comment) File src/acpi/acpigen_pci_root_resource_producer.c: https://review.coreboot.org/c/coreboot/+/81373/comment/6bcc5bea_c145370a : PS1, Line 49: /* SoC specific settings, device object creation could be placed here */ : soc_pci_domain_fill_ssdt(domain); > I don't think a soc specific way of creating objects is the way to go. […] We need this for GNR codes to cover GNR and SRF, and SPR will also benefit due to the reason of multiple SKU. I agree that this should not be a must, it is just an options. For clients, embedded, static generation should be the default way. -- To view, visit https://review.coreboot.org/c/coreboot/+/81373?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I893eb64c776e78f46737072b475acde5e32a796a Gerrit-Change-Number: 81373 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 12:11:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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coreboot-gerrit March 2024