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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80358?usp=email )
Change subject: arch/x86/ioapic: use uintptr_t for IOAPIC base address
......................................................................
Patch Set 3: Code-Review+2
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Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80549?usp=email )
Change subject: soc/intel/xeon_sp: Print device path when reporting resources
......................................................................
soc/intel/xeon_sp: Print device path when reporting resources
As there are multiple Vtd devices, print the path of each when reporting
resource registers.
Change-Id: I5d3a6484ed7c7b9760fce0f3a02a15ca26c2cbd2
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80549
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Shuo Liu: Looks good to me, but someone else must approve
Arthur Heymans: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index df2ffac..d43b209 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -110,8 +110,8 @@
if (!memory_map[i].description)
continue;
- printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
- memory_map[i].description, values[i]);
+ printk(BIOS_DEBUG, "%s: MC MAP: %s: 0x%llx\n",
+ dev_path(dev), memory_map[i].description, values[i]);
}
}
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Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80548?usp=email )
Change subject: soc/intel/xeon_sp: Align resources to 4K
......................................................................
soc/intel/xeon_sp: Align resources to 4K
The lower bit of the BAR might be used for something else,
like enable bits, so mask the lower 12 bits and align all
base address to 4K.
Confirmed that all BARs have a minimum alignment of 4K, so that
masking the lower bits doesn't change the reported address.
The alignment of the VTD BARs is:
- VTD_MMCFG_BASE_CSR 64 MiB
- VTD_MMIOL_CSR 1 MiB
- VTD_NCMEM_BASE_CSR 64 MiB
- VTD_TSEG_BASE_CSR 1 MiB
- VTD_BAR_CSR 4 KiB
Change-Id: I9a7b963c0074246616968dd15c147f4916297d59
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80548
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/xeon_sp/include/soc/iomap.h
M src/soc/intel/xeon_sp/uncore.c
2 files changed, 2 insertions(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h
index f348ab9..ccc7e44d 100644
--- a/src/soc/intel/xeon_sp/include/soc/iomap.h
+++ b/src/soc/intel/xeon_sp/include/soc/iomap.h
@@ -9,9 +9,9 @@
.mask_bits = mask_bits_, .description = desc_, \
}
-#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, 0, desc_)
+#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, 12, desc_)
#define MAP_ENTRY_LIMIT_64(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 1, 1, mask_bits_, desc_)
-#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, 0, desc_)
+#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, 12, desc_)
#define MAP_ENTRY_LIMIT_32(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 0, 1, mask_bits_, desc_)
// SPI BAR0 MMIO base address
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 96855ed..df2ffac 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -77,7 +77,6 @@
return;
}
- /* All registers are on a 1MiB granularity. */
mask = ((1ULL << entry->mask_bits) - 1);
mask = ~mask;
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Change subject: libpayload: Remove legacy CBFS API
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/xeon_sp: Add helper functions
......................................................................
Patch Set 14: Code-Review+2
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Change subject: soc/amd/glinda: Use gpp_clk_setup_common function
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80699/comment/174ed2c4_ae84289a :
PS2, Line 9: I7d7da4bfe07
this should be the 12 first digits of the commit hash (0452d0939e7d) and not of the change id
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Change subject: soc/intel/xeon_sp: Align resources to 4K
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/amd/glinda: Use gpp_clk_setup_common function
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/glinda/include/soc/southbridge.h:
https://review.coreboot.org/c/coreboot/+/80699/comment/674ab615_cb5e80a5 :
PS1, Line 90: #define GPP_CLK_OUTPUT_AVAILABLE 4
> this likely needs to be updated to match the silicon, but that's something for a separate patch, sin […]
sure,
will push a patch
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Change subject: soc/amd/glinda: Use gpp_clk_setup_common function
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80699/comment/99eb69da_84e8135b :
PS1, Line 9: CB:80285
> since this is already in upstream, it would be better to reference this in the commit 012345 ("commi […]
Done
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Hello Anand Vaikar, Felix Held, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80699?usp=email
to look at the new patch set (#2).
Change subject: soc/amd/glinda: Use gpp_clk_setup_common function
......................................................................
soc/amd/glinda: Use gpp_clk_setup_common function
In follow up to commit I7d7da4bfe07 ("soc/amd: Factor out gpp_clk_setup function") use gpp_clk_setup_common for glinda as well.
Change-Id: If0c1cda0d36de48c7f7315a1b8203b0e53f63f75
Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com>
---
M src/soc/amd/glinda/Kconfig
M src/soc/amd/glinda/fch.c
M src/soc/amd/glinda/include/soc/southbridge.h
3 files changed, 2 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/80699/2
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