Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Tarun, Tyler Wang.
Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun, Tyler Wang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/rex/var/karis: Refactor SSD power sequencing
......................................................................
mb/google/rex/var/karis: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
|
v
ramstage (A19/1, A20/1)
Ideally, we don't need SSD power sequencing at ramstage, but due to the
fact that Karis has RO locked, any change in the bootblock won't be
applicable for FSI'ed screebo devices. Therefore, we're keeping the
existing ramstage power sequencing flow as is
TEST=Able to build and boot google/karis using NVMe without any
problems. S0ix and read/write from/to SSD are also normal.
Change-Id: I79171a7830b75f5c20bbe30023f2814a62743a13
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/rex/variants/karis/gpio.c
1 file changed, 6 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/80663/3
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80664?usp=email
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Change subject: mb/google/rex/var/deku: Refactor SSD power sequencing
......................................................................
mb/google/rex/var/deku: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.
TEST=Able to build and boot google/deku using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.
Change-Id: Iedaff8a793f1ba5d2b97352b95c4dfdd2b818ebd
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/rex/variants/deku/gpio.c
1 file changed, 6 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/80664/2
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun, Tyler Wang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80663?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+2 by Kapil Porwal, Code-Review+2 by Tyler Wang, Verified+1 by build bot (Jenkins)
The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: mb/google/rex/var/karis: Refactor SSD power sequencing
......................................................................
mb/google/rex/var/karis: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
|
v
ramstage (A19/1, A20/1)
Ideally, we don't need SSD power sequencing at ramstage, but due to the
fact that Karis has RO locked, any change in the bootblock won't be
applicable for FSI'ed screebo devices. Therefore, we're keeping the
existing ramstage power sequencing flow as is
TEST=Able to build and boot google/karis using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.
Change-Id: I79171a7830b75f5c20bbe30023f2814a62743a13
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/rex/variants/karis/gpio.c
1 file changed, 6 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/80663/2
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80663?usp=email )
Change subject: mb/google/rex/var/karis: Refactor SSD power sequencing
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80663/comment/0b2c9e36_fcddc215 :
PS1, Line 8:
> It’d be great if you could start by describing the problem.
Acknowledged
https://review.coreboot.org/c/coreboot/+/80663/comment/64d46d23_27efd084 :
PS1, Line 21: hence,
> Should the comma be before *hence*?
Acknowledged
https://review.coreboot.org/c/coreboot/+/80663/comment/c70dbd3a_07e072c3 :
PS1, Line 21: removed
> remove
Acknowledged
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80642?usp=email
to look at the new patch set (#2).
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Change subject: mb/google/rex/var/ovis: Refactor SSD power sequencing
......................................................................
mb/google/rex/var/ovis: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.
TEST=Able to build and boot google/ovis using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.
Change-Id: I891b5a6d2c29f5d940793a4e90215265f2a4fcd8
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/rex/variants/ovis/gpio.c
1 file changed, 8 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/80642/2
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80641?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+2 by Kapil Porwal, Verified+1 by build bot (Jenkins)
The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: mb/google/rex/var/rex0: Refactor SSD power sequencing
......................................................................
mb/google/rex/var/rex0: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.
TEST=Able to build and boot google/rex0 using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.
Change-Id: Idde2f7693771f1d7e3171e51232d1bb899bfe33e
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/rex/variants/rex0/gpio.c
1 file changed, 6 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/80641/2
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80640?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
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Change subject: mb/google/rex/var/screebo: Refactor SSD power sequencing
......................................................................
mb/google/rex/var/screebo: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
|
v
ramstage (A19/1, A20/1)
Ideally, we don't need SSD power sequencing at ramstage, but due to the
fact that Screebo has RO locked, any change in the bootblock won't be
applicable for FSI'ed screebo devices. Therefore, we're keeping the
existing ramstage power sequencing flow as is.
TEST=Able to build and boot google/screebo using NVMe without any
problems. S0ix and read/write from/to SSD are also normal.
Change-Id: I0ee1fa4613178da8771c9e6b5ee871e50ea6324c
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/rex/variants/screebo/gpio.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/80640/2
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Change subject: mb/google/rex/var/screebo: Refactor SSD power sequencing
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Same comments as in https://review.coreboot.org/c/coreboot/+/80663/1.
Acknowledged
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Hello Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74501?usp=email
to look at the new patch set (#23).
Change subject: arch/arm64: Add Clang as supported target
......................................................................
arch/arm64: Add Clang as supported target
QEMU aarch64 boots to payload when compiled with clang.
Change-Id: I940a1ccf5cc4ec7bed5b6c8be92fc47922e1e747
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/Kconfig
M src/arch/arm64/Kconfig
M src/soc/qualcomm/sc7180/Kconfig
3 files changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/74501/23
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Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Gerrit-Attention: Julius Werner <jwerner(a)chromium.org>
Gerrit-MessageType: newpatchset
Attention is currently required from: Arthur Heymans, Julius Werner, Paul Menzel.
Hello Julius Werner, Martin L Roth, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69747?usp=email
to look at the new patch set (#20).
Change subject: arch/arm: Build test all arm targets with clang
......................................................................
arch/arm: Build test all arm targets with clang
Some targets cannot be supported by clang as clang generates slightly
larger binaries which the hardware won't accept.
Change-Id: I88cf8ce16fb6c61c19d615e396f5871179b06fc8
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/Kconfig
M src/arch/arm/Kconfig
M src/soc/nvidia/tegra124/Kconfig
M src/soc/qualcomm/ipq40xx/Kconfig
M src/soc/qualcomm/ipq806x/Kconfig
M src/soc/rockchip/rk3288/Kconfig
6 files changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/69747/20
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I88cf8ce16fb6c61c19d615e396f5871179b06fc8
Gerrit-Change-Number: 69747
Gerrit-PatchSet: 20
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
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Gerrit-MessageType: newpatchset