Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80486?usp=email )
Change subject: soc/intel/alderlake: Sync UPD Usb4CmMode with Kconfig
......................................................................
soc/intel/alderlake: Sync UPD Usb4CmMode with Kconfig
The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set
the UPD to match this to avoid the connection type being mismatched.
If it's mismatched, the TBT port will time out.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I8a99db165301ce08caf55aac0e33ca1994559d62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80486
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 4 insertions(+), 0 deletions(-)
Approvals:
Matt DeVillier: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
Kapil Porwal: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index cb54598..d9c0f8e 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -679,6 +679,10 @@
if (is_dev_enabled(tcss_port_arr[i]))
s_cfg->UsbTcPortEn |= BIT(i);
}
+
+#if !CONFIG(SOC_INTEL_ALDERLAKE_PCH_M)
+ s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER);
+#endif
}
static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg,
--
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Gerrit-Change-Number: 80486
Gerrit-PatchSet: 6
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80686?usp=email )
Change subject: mb/google/nissa/var/glassway: Generate SPD ID for supported memory parts
......................................................................
mb/google/nissa/var/glassway: Generate SPD ID for supported memory parts
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name ID to assign
K3KL8L80CM-MGCT 0 (0000)
K3KL6L60GM-MGCT 1 (0001)
H58G56AK6BX069 2 (0010)
H9JCNNNBK3MLYR-N6E 3 (0011)
BUG=b:319071869
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
part_id_gen.go ADL lp5 \
src/mainboard/google/brya/variants/glassway/memory/ \
src/mainboard/google/brya/variants/glassway/memory/\
mem_parts_used.txt"
Change-Id: I00ae3efe8e554f44cee5a27ac88c5d65eb95f7fb
Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80686
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
M src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
3 files changed, 20 insertions(+), 2 deletions(-)
Approvals:
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
Daniel Peng: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk b/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
index eace2e4..b4d82e9 100644
--- a/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
@@ -1,5 +1,10 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
-# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+# Generated by:
+# /tmp/go-build472300524/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
-SPD_SOURCES = placeholder
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 1(0b0001) Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = H58G56AK6BX069
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 3(0b0011) Parts = H9JCNNNBK3MLYR-N6E
diff --git a/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
index fa24790..866132d3 100644
--- a/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
@@ -1 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# /tmp/go-build472300524/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
+
DRAM Part Name ID to assign
+K3KL8L80CM-MGCT 0 (0000)
+K3KL6L60GM-MGCT 1 (0001)
+H58G56AK6BX069 2 (0010)
+H9JCNNNBK3MLYR-N6E 3 (0011)
diff --git a/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
index 2499005..deeb000 100644
--- a/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
@@ -9,3 +9,7 @@
# See util/spd_tools/README.md for more details and instructions.
# Part Name
+K3KL8L80CM-MGCT
+K3KL6L60GM-MGCT
+H58G56AK6BX069
+H9JCNNNBK3MLYR-N6E
--
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80358?usp=email )
Change subject: arch/x86/ioapic: use uintptr_t for IOAPIC base address
......................................................................
Patch Set 3:
(1 comment)
File src/arch/x86/mpspec.c:
https://review.coreboot.org/c/coreboot/+/80358/comment/976bab35_33ae858a :
PS2, Line 14: #include <stdint.h>
> maybe remove this as you included <types. […]
Done
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Hello Alexander Couzens, Arthur Heymans, Christian Walter, Cliff Huang, Evgeny Zinoviev, Fred Reitberger, Jason Glenesk, Jeff Daly, Johnny Lin, Jérémy Compostella, Lance Zhao, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Shuo Liu, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80358?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Code-Review+2 by Matt DeVillier, Verified+1 by build bot (Jenkins)
Change subject: arch/x86/ioapic: use uintptr_t for IOAPIC base address
......................................................................
arch/x86/ioapic: use uintptr_t for IOAPIC base address
Use uintptr_t for the IOAPIC base parameter of the various IOAPIC-
related functions to avoid needing type casts in the callers. This also
allows dropping the VIO_APIC_VADDR define and consistently use the
IO_APIC_ADDR define instead.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I912943e923ff092708e90138caa5e1daf269a69f
---
M src/acpi/acpi_apic.c
M src/acpi/acpi_dmar.c
M src/arch/x86/include/arch/ioapic.h
M src/arch/x86/include/arch/smp/mpspec.h
M src/arch/x86/ioapic.c
M src/arch/x86/mpspec.c
M src/mainboard/apple/macbook21/mptable.c
M src/mainboard/asus/p2b/variants/p2b-d/mptable.c
M src/mainboard/asus/p2b/variants/p2b-ds/mptable.c
M src/mainboard/getac/p470/mptable.c
M src/mainboard/ibase/mb899/mptable.c
M src/mainboard/intel/d945gclf/mptable.c
M src/mainboard/kontron/986lcd-m/mptable.c
M src/mainboard/lenovo/t60/mptable.c
M src/mainboard/lenovo/x60/mptable.c
M src/mainboard/roda/rk886ex/mptable.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/soc/amd/common/block/acpi/ivrs.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/root_complex/ioapic.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/common/block/lpc/lpc_lib.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/xeon_sp/uncore_acpi.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/lynxpoint/lpc.c
35 files changed, 89 insertions(+), 86 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/80358/3
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Hello Nick Vaccaro, Subrata Banik, build bot (Jenkins),
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Change subject: vc/intel/fsp2/twinlake: Add FSP headers
......................................................................
vc/intel/fsp2/twinlake: Add FSP headers
Add FSP header files for Twin Lake. Currently these are just a copy of
ADL-N headers.
BUG=none
BRANCH=firmware-nissa-15217.B
TEST=Build and boot Google/Yaviks with Twin Lake kconfig enabled
Signed-off-by: Kapil Porwal <kapilporwal(a)google.com>
Change-Id: I37579335c784866ebbf978e28936abf046a85b48
---
A src/vendorcode/intel/fsp/fsp2_0/twinlake/FirmwareVersionInfoHob.h
A src/vendorcode/intel/fsp/fsp2_0/twinlake/FspUpd.h
A src/vendorcode/intel/fsp/fsp2_0/twinlake/FspmUpd.h
A src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h
A src/vendorcode/intel/fsp/fsp2_0/twinlake/MemInfoHob.h
5 files changed, 7,655 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/80698/2
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