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Change subject: soc/amd/glinda: Use gpp_clk_setup_common function
......................................................................
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Change subject: soc/amd/glinda: Use pcie_gpp_dxio_update_clk_req_config
......................................................................
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Change subject: soc/amd/common/acp: use clrsetbits32p to avoid need for casts
......................................................................
soc/amd/common/acp: use clrsetbits32p to avoid need for casts
Use clrsetbits32p instead of clrsetbits32 to not need to cast the
uintptr_t address to void * in the function call.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ic29bf04866a7e1d5c831422f31803a724a41069b
---
M src/soc/amd/common/block/acp/acp_gen1.c
M src/soc/amd/common/block/acp/acp_gen2.c
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/80700/1
diff --git a/src/soc/amd/common/block/acp/acp_gen1.c b/src/soc/amd/common/block/acp/acp_gen1.c
index 0fe37f3..4bfd711 100644
--- a/src/soc/amd/common/block/acp/acp_gen1.c
+++ b/src/soc/amd/common/block/acp/acp_gen1.c
@@ -17,7 +17,7 @@
static void acp_update32(uintptr_t bar, uint32_t reg, uint32_t clear, uint32_t set)
{
- clrsetbits32((void *)(bar + reg), clear, set);
+ clrsetbits32p(bar + reg, clear, set);
}
void acp_init(struct device *dev)
diff --git a/src/soc/amd/common/block/acp/acp_gen2.c b/src/soc/amd/common/block/acp/acp_gen2.c
index 50de4b0..be24ec9 100644
--- a/src/soc/amd/common/block/acp/acp_gen2.c
+++ b/src/soc/amd/common/block/acp/acp_gen2.c
@@ -17,7 +17,7 @@
static void acp_update32(uintptr_t bar, uint32_t reg, uint32_t clear, uint32_t set)
{
- clrsetbits32((void *)(bar + reg), clear, set);
+ clrsetbits32p(bar + reg, clear, set);
}
void acp_init(struct device *dev)
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Change subject: soc/intel/xeon_sp: Refactor IOAT compiler optimization outs
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Change subject: soc/amd/glinda: Use gpp_clk_setup_common function
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80699/comment/5156f2b5_dfefd066 :
PS1, Line 9: CB:80285
since this is already in upstream, it would be better to reference this in the commit 012345 ("commit subject line") form
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Change subject: soc/amd/glinda: Use gpp_clk_setup_common function
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File src/soc/amd/glinda/include/soc/southbridge.h:
https://review.coreboot.org/c/coreboot/+/80699/comment/90db7ef8_6c7860cf :
PS1, Line 90: #define GPP_CLK_OUTPUT_AVAILABLE 4
this likely needs to be updated to match the silicon, but that's something for a separate patch, since it's a different logical change
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Change subject: soc/amd/glinda: Use pcie_gpp_dxio_update_clk_req_config
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/amd/glinda: Use pcie_gpp_dxio_update_clk_req_config
......................................................................
Patch Set 3:
(1 comment)
This change is ready for review.
Patchset:
PS1:
> i'm not sure if we want to use this functionality for Glinda so if we should just drop it and just h […]
pushed the new version of patch to keep glinda in sync with other AMD SoC
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Change subject: soc/amd/glinda: Use gpp_clk_setup_common function
......................................................................
soc/amd/glinda: Use gpp_clk_setup_common function
In follow up to CB:80285 use gpp_clk_setup_common for glinda as well.
Change-Id: If0c1cda0d36de48c7f7315a1b8203b0e53f63f75
Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com>
---
M src/soc/amd/glinda/Kconfig
M src/soc/amd/glinda/fch.c
M src/soc/amd/glinda/include/soc/southbridge.h
3 files changed, 2 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/80699/1
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 8a6649a..d529002 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -46,6 +46,7 @@
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT
select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct
+ select SOC_AMD_COMMON_BLOCK_GPP_CLK
select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE # TODO: Check if this is still correct
diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c
index bb03ad4..2218ce3 100644
--- a/src/soc/amd/glinda/fch.c
+++ b/src/soc/amd/glinda/fch.c
@@ -132,46 +132,7 @@
static void gpp_clk_setup(void)
{
struct soc_amd_glinda_config *cfg = config_of_soc();
-
- /* look-up table to be able to iterate over the PCIe clock output settings */
- const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {
- GPP_CLK0_REQ_SHIFT,
- GPP_CLK1_REQ_SHIFT,
- GPP_CLK2_REQ_SHIFT,
- GPP_CLK3_REQ_SHIFT,
- GPP_CLK4_REQ_SHIFT,
- GPP_CLK5_REQ_SHIFT,
- GPP_CLK6_REQ_SHIFT,
- };
-
- uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
-
- pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0],
- ARRAY_SIZE(cfg->gpp_clk_config));
- for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
- gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);
- /*
- * The remapping of values is done so that the default of the enum used for the
- * devicetree settings is the clock being enabled, so that a missing devicetree
- * configuration for this will result in an always active clock and not an
- * inactive PCIe clock output. Only the configuration for the clock outputs
- * available on the package is provided via the devicetree; the rest is
- * switched off unconditionally.
- */
- switch (i < GPP_CLK_OUTPUT_AVAILABLE ? cfg->gpp_clk_config[i] : GPP_CLK_OFF) {
- case GPP_CLK_REQ:
- gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]);
- break;
- case GPP_CLK_OFF:
- gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]);
- break;
- case GPP_CLK_ON:
- default:
- gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]);
- }
- }
-
- misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl);
+ gpp_clk_setup_common(&cfg->gpp_clk_config[0], ARRAY_SIZE(cfg->gpp_clk_config));
}
static void cgpll_clock_gate_init(void)
diff --git a/src/soc/amd/glinda/include/soc/southbridge.h b/src/soc/amd/glinda/include/soc/southbridge.h
index 32945e8..9cd835b 100644
--- a/src/soc/amd/glinda/include/soc/southbridge.h
+++ b/src/soc/amd/glinda/include/soc/southbridge.h
@@ -87,20 +87,7 @@
#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
/* FCH MISC Registers 0xfed80e00 */
-#define GPP_CLK_CNTRL 0x00
-#define GPP_CLK0_REQ_SHIFT 0
-#define GPP_CLK1_REQ_SHIFT 2
-#define GPP_CLK4_REQ_SHIFT 4
-#define GPP_CLK2_REQ_SHIFT 6
-#define GPP_CLK3_REQ_SHIFT 8
-#define GPP_CLK5_REQ_SHIFT 10
-#define GPP_CLK6_REQ_SHIFT 12
-#define GPP_CLK_OUTPUT_COUNT 7
#define GPP_CLK_OUTPUT_AVAILABLE 4
-#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift))
-#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift))
-#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift))
-#define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift))
#define MISC_CLKGATEDCNTL 0x2c
#define ALINKCLK_GATEOFFEN BIT(16)
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