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Change subject: mb/google/brya: Create yavista variant
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80342/comment/6777d0a1_5ea7a4d3 :
PS2, Line 2: hsueh.rasheed
Please spell it Hsueh Rasheed:
$ git config --global user.name "Hsueh Rasheed"
$ git commit --amend --author="Hsueh Rasheed <hsueh.rasheed(a)inventec.corp-partner.google.com>" -s
https://review.coreboot.org/c/coreboot/+/80342/comment/a8c55926_2bcb2105 :
PS2, Line 12: (Auto-Generated by create_coreboot_variant.sh version 4.5.0).
Please put the . before the ).
Too bad the script still isn’t fixed after over five years.
https://review.coreboot.org/c/coreboot/+/80342/comment/4e18f926_82af07df :
PS2, Line 20: Signed-off-by: hsueh.rasheed <hsueh.rasheed(a)inventec.corp-partner.google.com>
Ditto.
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Change subject: soc/mediatek: Move `get_sdram_config` to common code
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Is there a way to avoid the weak function definition.
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Change subject: mb/google/brox: Disable Early EC Sync
......................................................................
mb/google/brox: Disable Early EC Sync
Early EC Sync does not need to be enabled in coreboot as EFS2 is being
enabled in the EC.
BUG=b:326152804
BRANCH=None
TEST=emerge-brox coreboot
To be tested with EC sync enabled
Change-Id: I08bdbe9f3dcea837b0b148adc137c03d3461877a
Signed-off-by: Shelley Chen <shchen(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80689
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---
M src/mainboard/google/brox/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index 0594732..1794d46 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -113,7 +113,6 @@
default "brox" if BOARD_GOOGLE_BROX
config VBOOT
- select VBOOT_EARLY_EC_SYNC
select VBOOT_LID_SWITCH
config DIMM_SPD_SIZE
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Change subject: mainboard/siemens/chili: Use enums from azalia_device.h
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Thanks Paul, but that's actually our port :)
Nicholas, you'll have to organize the patches differently so there are no
intermediate CI failures. If it's only two boards, I wouldn't mind if you
squash everything into one patch.
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Change subject: soc/amd/glinda: Update GPP_CLK_OUTPUT_AVAILABLE
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80701/comment/3b87d9b1_0a8e3c17 :
PS1, Line 7: Update GPP_CLK_OUTPUT_AVAILABLE
> Please be more specific: […]
i'd say that the 7 is the only relevant number here. the 4 is from mendocino and iirc glinda started as copy of mendocino
https://review.coreboot.org/c/coreboot/+/80701/comment/94b7481e_acbcd698 :
PS1, Line 10: Reference (PPR) (#57254), table 230.
> would be good to mention the revision of that document; in the revision i'm looking at, it's a diffe […]
or just refer to the table by its name "GPP ClkREQB Mapping"
Patchset:
PS1:
> Is that a copy and paste error, or was PPR updated?
i'd guess that in some version there were a few more tables added, so the numbers shifted
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Change subject: soc/amd/glinda: Update GPP_CLK_OUTPUT_AVAILABLE
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80701/comment/0a12c620_680812b1 :
PS1, Line 7: Update GPP_CLK_OUTPUT_AVAILABLE
Please be more specific:
> Increase GPP_CLK_OUTPUT_AVAILABLE from 4 to 7
> Update GPP_CLK_OUTPUT_AVAILABLE from 4 to 7
Patchset:
PS1:
Is that a copy and paste error, or was PPR updated?
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Change subject: soc/amd/glinda: Update GPP_CLK_OUTPUT_AVAILABLE
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80701/comment/25de0d84_68320a83 :
PS1, Line 10: Reference (PPR) (#57254), table 230.
would be good to mention the revision of that document; in the revision i'm looking at, it's a different table number
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