coreboot-gerrit February 2024

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Drop code to locate the UBOX bus
by Patrick Rudolph (Code Review) 05 Feb '24

05 Feb '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80102?usp=email ) Change subject: soc/intel/xeon_sp: Drop code to locate the UBOX bus ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/xeon_sp/spr/soc_util.c: https://review.coreboot.org/c/coreboot/+/80102/comment/1ea9bee4_d4a1910d : PS9, Line 142: uint32_t get_ubox_busno(uint32_t socket, uint8_t offset) > it is still needed to do per-socket uncore bus operations as a general case so it would make sense t […] It cannot be used on multi PCI segment groups since bus numbers are duplicated. Instead the device can be located by traversing the devicetree. -- To view, visit https://review.coreboot.org/c/coreboot/+/80102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b18f02f62b69ec7c73cd5665102cb6bfc6e64b5 Gerrit-Change-Number: 80102 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 05 Feb 2024 14:39:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/x86/bootblock.ld: Align the base of bootblock downwards
by Arthur Heymans (Code Review) 05 Feb '24

05 Feb '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80346?usp=email ) Change subject: arch/x86/bootblock.ld: Align the base of bootblock downwards ...................................................................... arch/x86/bootblock.ld: Align the base of bootblock downwards Instead of using some aritmetics that sometimes works, use the largest alignment necessary (page tables) and align downwards in the linker script. This fixes linking failing when linking in page tables inside the bootblock. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I78c6ba6e250ded3f04b12cd0c20b18cb653a1506 --- M src/arch/x86/bootblock.ld 1 file changed, 4 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/80346/1 diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index d59eb27..6547985 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -17,19 +17,16 @@ . = _ebootblock - CONFIG_C_ENV_BOOTBLOCK_SIZE; #else . = BOOTBLOCK_TOP - PROGRAM_SZ; - . = ALIGN(64); + /* Page tables need to be at a 4K boundary so align the bootblock downwards */ + . = ALIGN(4096); + . -= 4096; #endif _bootblock = .; INCLUDE "bootblock/lib/program.ld" - /* - * Allocation reserves extra space here. Alignment requirements - * may cause the total size of a section to change when the start - * address gets applied. - */ - PROGRAM_SZ = SIZEOF(.text) + 512; + PROGRAM_SZ = SIZEOF(.text); . = MIN(_ECFW_PTR, MIN(_ID_SECTION, _FIT_POINTER)) - EARLYASM_SZ; . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(16); -- To view, visit https://review.coreboot.org/c/coreboot/+/80346?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78c6ba6e250ded3f04b12cd0c20b18cb653a1506 Gerrit-Change-Number: 80346 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS
by Felix Held (Code Review) 05 Feb '24

05 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79882?usp=email ) Change subject: soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS ...................................................................... soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS Currently, SOC_INTEL_COMMON_BLOCK_TCSS will set MUX to disabled. The two related options to re-configure it for either USB devices or displays, are currently only supported by the ChromeEC. As such, any device without the ChromeEC will boot with attached USB-C devices in a non-functional state. Add TCSS_HAS_USBC_OPS to make this feature configurable, and set the default to enabled if the board features the ChromeEC. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ia848668ae9af4637fc7cffec9eb694f29d7deba9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79882 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/common/block/tcss/Kconfig M src/soc/intel/common/block/tcss/tcss.c 2 files changed, 23 insertions(+), 13 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig index 4af75fc..7a8f52c 100644 --- a/src/soc/intel/common/block/tcss/Kconfig +++ b/src/soc/intel/common/block/tcss/Kconfig @@ -2,17 +2,28 @@ def_bool n select FSPS_USE_MULTI_PHASE_INIT help - Sets up USB2/3 port mapping in TCSS MUX and sets MUX to disconnect state + Sets up USB2/3 port mapping in TCSS MUX + +config TCSS_HAS_USBC_OPS + bool "Enable USB-C MUX operations via the EC" + default y if EC_GOOGLE_CHROMEEC + depends on SOC_INTEL_COMMON_BLOCK_TCSS + help + Enable USB-C operations via the EC. Requires `usbc_get_ops` to control features + such as HPD and DP Mode entry. Currently, only the ChromeEC implements this, see + (ec/google/chromeec/usbc_mux.c). + + This results in the MUX being set to a disabled state. config ENABLE_TCSS_DISPLAY_DETECTION bool "Enable detection of displays over USB Type-C ports with TCSS" - depends on SOC_INTEL_COMMON_BLOCK_TCSS && RUN_FSP_GOP + depends on TCSS_HAS_USBC_OPS && RUN_FSP_GOP help Enable displays to be detected over Type-C ports during boot. config ENABLE_TCSS_USB_DETECTION bool "Enable detection of USB boot devices attached to USB Type-C ports with TCSS" - depends on SOC_INTEL_COMMON_BLOCK_TCSS + depends on TCSS_HAS_USBC_OPS help Enable USB-C attached storage devices to be detected at boot. This option is required for some payloads (eg, edk2), without which devices attached diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c index 7c58e3a..974aeb6 100644 --- a/src/soc/intel/common/block/tcss/tcss.c +++ b/src/soc/intel/common/block/tcss/tcss.c @@ -442,23 +442,22 @@ size_t i; port_map = tcss_get_port_info(&num_ports); - if (port_map == NULL) + if ((port_map == NULL) || platform_is_resuming()) return; - if (!platform_is_resuming()) { + if (CONFIG(TCSS_HAS_USBC_OPS)) for (i = 0; i < num_ports; i++) tcss_init_mux(i, &port_map[i]); - /* This should be performed before alternate modes are entered */ - if (tcss_ops.configure_aux_bias_pads) - tcss_ops.configure_aux_bias_pads(aux_bias_pads); + /* This should be performed before alternate modes are entered */ + if (tcss_ops.configure_aux_bias_pads) + tcss_ops.configure_aux_bias_pads(aux_bias_pads); - if (CONFIG(ENABLE_TCSS_DISPLAY_DETECTION)) - tcss_configure_dp_mode(port_map, num_ports); + if (CONFIG(ENABLE_TCSS_DISPLAY_DETECTION)) + tcss_configure_dp_mode(port_map, num_ports); - if (CONFIG(ENABLE_TCSS_USB_DETECTION)) - tcss_configure_usb_mode(port_map, num_ports); - } + if (CONFIG(ENABLE_TCSS_USB_DETECTION)) + tcss_configure_usb_mode(port_map, num_ports); } bool tcss_valid_tbt_auth(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/79882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia848668ae9af4637fc7cffec9eb694f29d7deba9 Gerrit-Change-Number: 79882 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Remove unused function fsp_write_line
by Felix Held (Code Review) 05 Feb '24

05 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80302?usp=email ) Change subject: drivers/intel/fsp2_0: Remove unused function fsp_write_line ...................................................................... drivers/intel/fsp2_0: Remove unused function fsp_write_line This is just a clean-up commit. Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec97 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80302 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/include/fsp/debug.h 2 files changed, 0 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 8c0d67d..4cd309e 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -7,12 +7,6 @@ #include <fsp/debug.h> #include <fsp/util.h> -asmlinkage size_t fsp_write_line(uint8_t *buffer, size_t number_of_bytes) -{ - console_write_line(buffer, number_of_bytes); - return number_of_bytes; -} - enum fsp_call_phase { BEFORE_FSP_CALL, AFTER_FSP_CALL, diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 044ce95..dc5557e 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -58,15 +58,6 @@ const char *fsp_get_guid_name(const uint8_t *guid); void fsp_print_guid_extension_hob(const struct hob_header *hob); -/* - * Writes number_of_bytes data bytes from buffer to the console. - * The number of bytes actually written to the console is returned. - * - * If number_of_bytes is zero, don't output any data but instead wait until - * the console has output all data, then return 0. - */ -asmlinkage size_t fsp_write_line(uint8_t *buffer, size_t number_of_bytes); - /* Callback to snapshot all GPIO configurations. */ void gpio_snapshot(void); /* Callback to verify that current GPIO configuration matches the saved snapshot */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80302?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec97 Gerrit-Change-Number: 80302 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/intel/xeon_sp/bootblock: Fix out of order header files
by Felix Held (Code Review) 05 Feb '24

05 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80301?usp=email ) Change subject: soc/intel/xeon_sp/bootblock: Fix out of order header files ...................................................................... soc/intel/xeon_sp/bootblock: Fix out of order header files Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec96 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80301 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/bootblock.c 1 file changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Shuo Liu: Looks good to me, but someone else must approve diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index cc839ef..62ca48f 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -1,18 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <bootblock_common.h> -#include <device/pci.h> -#include <FsptUpd.h> -#include <intelblocks/fast_spi.h> -#include <intelblocks/tco.h> -#include <soc/iomap.h> #include <console/console.h> #include <cpu/x86/mtrr.h> -#include <intelblocks/lpc_lib.h> -#include <security/intel/cbnt/cbnt.h> -#include <soc/pci_devs.h> -#include <soc/bootblock.h> +#include <device/pci.h> #include <fsp/util.h> +#include <FsptUpd.h> +#include <intelblocks/fast_spi.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/tco.h> +#include <security/intel/cbnt/cbnt.h> +#include <soc/bootblock.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { -- To view, visit https://review.coreboot.org/c/coreboot/+/80301?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec96 Gerrit-Change-Number: 80301 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brox: Fix the I2C configuration
by Felix Held (Code Review) 05 Feb '24

05 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80303?usp=email ) Change subject: mb/google/brox: Fix the I2C configuration ...................................................................... mb/google/brox: Fix the I2C configuration Update the I2C configuration to match the usage such that only required I2C controllers are enabled. BUG=b:319390850 TEST=Build Brox BIOS image and boot to OS. Ensure that only the required I2C controllers are enabled. Change-Id: I9f24beb9ef587163362cc6ded88efb05be1329b9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80303 Reviewed-by: Shelley Chen <shchen(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index e1c8134..3e0e7fb 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -48,9 +48,9 @@ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" register "serial_io_gspi_mode" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/80303?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f24beb9ef587163362cc6ded88efb05be1329b9 Gerrit-Change-Number: 80303 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: device/azalia: Separate codec checking and initialization
by Nico Huber (Code Review) 05 Feb '24

05 Feb '24

Attention is currently required from: Elyes Haouas, Nicholas Sudsgaard, Paul Menzel. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80332?usp=email ) Change subject: device/azalia: Separate codec checking and initialization ...................................................................... Patch Set 8: Code-Review+1 (1 comment) File src/device/azalia_device.c: https://review.coreboot.org/c/coreboot/+/80332/comment/5060d15d_8d8fa092 : PS6, Line 259: load_verb > I can see how the separation is a bit overdone with `get_verb()` and `load_verb()`. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/80332?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92b6d184abccdbe0e1bfce98a2c959a97a618a29 Gerrit-Change-Number: 80332 Gerrit-PatchSet: 8 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 05 Feb 2024 10:33:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: cpu/x86/64bit: Turn jumping to long mode into a macro
by Patrick Rudolph (Code Review) 05 Feb '24

05 Feb '24

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79261?usp=email ) Change subject: cpu/x86/64bit: Turn jumping to long mode into a macro ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Patchset: PS4: That might also allow to merge src/cpu/x86/64bit/mode_switch.S and src/cpu/x86/64bit/mode_switch2.S into a single file. -- To view, visit https://review.coreboot.org/c/coreboot/+/79261?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida861338004187e4e714be41e17c8447fa4cf935 Gerrit-Change-Number: 79261 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Feb 2024 10:08:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86: Link page tables in stage if possible
by Patrick Rudolph (Code Review) 05 Feb '24

05 Feb '24

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80337?usp=email ) Change subject: cpu/x86: Link page tables in stage if possible ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80337/comment/9ae8c0a8_e3c0a8be : PS1, Line 9: When switching back and forward from 32 to 64, for example to call a > > I don't understand this. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80337?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 Gerrit-Change-Number: 80337 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Feb 2024 10:07:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: smmstorev2: Load the communication buffer at SMM setup
by Patrick Rudolph (Code Review) 05 Feb '24

05 Feb '24

Attention is currently required from: Arthur Heymans, Benjamin Doron, Jérémy Compostella, Patrick Georgi. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79738?usp=email ) Change subject: smmstorev2: Load the communication buffer at SMM setup ...................................................................... Patch Set 6: Code-Review+2 (1 comment) Patchset: PS6: Tested on? -- To view, visit https://review.coreboot.org/c/coreboot/+/79738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94dce77711f37f87033530f5ae48cb850a39341b Gerrit-Change-Number: 79738 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 05 Feb 2024 10:04:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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