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[M] Change in coreboot[main]: WIP: superio/ite: Add IT8629E
by Nicholas Sudsgaard (Code Review) 05 Feb '24

05 Feb '24

Nicholas Sudsgaard has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80344?usp=email ) Change subject: WIP: superio/ite: Add IT8629E ...................................................................... WIP: superio/ite: Add IT8629E Change-Id: I44d0377da11f0e118017caa4357012df9373b322 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- A src/superio/ite/it8629e/Kconfig A src/superio/ite/it8629e/Makefile.mk A src/superio/ite/it8629e/chip.h A src/superio/ite/it8629e/it8629e.h A src/superio/ite/it8629e/superio.c 5 files changed, 117 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/80344/1 diff --git a/src/superio/ite/it8629e/Kconfig b/src/superio/ite/it8629e/Kconfig new file mode 100644 index 0000000..e652a6a --- /dev/null +++ b/src/superio/ite/it8629e/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# Unfortunately, the datasheet for IT8629E is not public . Therefore, we will +# use the functionally closest chip (i.e. IT8728F) as a reference and try to +# reverse-engineer where necessary. + +# IT8629E seems to be very similar to IT8628E (again, no public datasheets), as +# the chip id is 0x8628. + +config SUPERIO_ITE_IT8629E + bool + select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_5FANS # Seems to support up to FAN_TAC6/FAN_CTL6 + select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN diff --git a/src/superio/ite/it8629e/Makefile.mk b/src/superio/ite/it8629e/Makefile.mk new file mode 100644 index 0000000..c574158 --- /dev/null +++ b/src/superio/ite/it8629e/Makefile.mk @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SUPERIO_ITE_IT8629E) += superio.c diff --git a/src/superio/ite/it8629e/chip.h b/src/superio/ite/it8629e/chip.h new file mode 100644 index 0000000..bad0266 --- /dev/null +++ b/src/superio/ite/it8629e/chip.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8629E_CHIP_H +#define SUPERIO_ITE_IT8629E_CHIP_H + +#include <superio/ite/common/env_ctrl_chip.h> + +struct superio_ite_it8629e_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8629E_CHIP_H */ diff --git a/src/superio/ite/it8629e/it8629e.h b/src/superio/ite/it8629e/it8629e.h new file mode 100644 index 0000000..573ca28 --- /dev/null +++ b/src/superio/ite/it8629e/it8629e.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8629E_H +#define SUPERIO_ITE_IT8629E_H + +#define IT8629E_FDC 0x00 // FDC +#define IT8629E_SP1 0x01 // Serial Port 1 +#define IT8629E_SP2 0x02 // Serial Port 2 +#define IT8629E_PP 0x03 // Parallel Port +#define IT8629E_EC 0x04 // Environment Controller +#define IT8629E_KBCK 0x05 // PS/2 Keyboard +#define IT8629E_KBCM 0x06 // PS/2 Mouse +#define IT8629E_GPIO 0x07 // GPIO +#define IT8629E_UNKNOWN 0x08 +#define IT8629E_IR 0x0a // Consumer IR + +#endif /* SUPERIO_ITE_IT8629E_H */ diff --git a/src/superio/ite/it8629e/superio.c b/src/superio/ite/it8629e/superio.c new file mode 100644 index 0000000..51f7c22 --- /dev/null +++ b/src/superio/ite/it8629e/superio.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <pc80/keyboard.h> +#include <superio/ite/common/env_ctrl.h> + +#include "chip.h" +#include "it8629e.h" + +static void it8629e_init(struct device *dev) +{ + const struct superio_ite_it8629e_config *conf = dev->chip_info; + const struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for FDC etc. */ + case IT8629E_EC: + res = probe_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + ite_ec_init(res->base, &conf->ec); + break; + case IT8629E_KBCK: + set_kbc_ps2_mode(); + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8629e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8629E_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, }, + { NULL, IT8629E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8629E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8629E_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ffc, }, + { NULL, IT8629E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ff8, }, + { NULL, IT8629E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0fff, 0x0fff, }, + { NULL, IT8629E_KBCM, PNP_IRQ0, }, + { NULL, IT8629E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, + 0x0fff, 0x0ff8, 0x0ff8, }, + { NULL, IT8629E_UNKNOWN, PNP_IO0 | PNP_IRQ0, 0xff8, }, + { NULL, IT8629E_IR, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8629e_ops = { + .name = "ITE IT8629E Super I/O", + .enable_dev = enable_dev +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/80344?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44d0377da11f0e118017caa4357012df9373b322 Gerrit-Change-Number: 80344 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: WIP: mainboard/lenovo: Add ThinkCentre M710s
by Nicholas Sudsgaard (Code Review) 05 Feb '24

05 Feb '24

Nicholas Sudsgaard has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80343?usp=email ) Change subject: WIP: mainboard/lenovo: Add ThinkCentre M710s ...................................................................... WIP: mainboard/lenovo: Add ThinkCentre M710s Working: - Can boot Ubuntu using payloads: SeaBIOS, TianoCore EDK 2 - PCIe - M2 SSD - SATA - USB - LAN - CPU fan - VGA (DP bridge) - COM1 - TPM - Memory card reader (Technically just a USB) - Display ports - Audio (headphone jack, via display) - M2 WLAN (+ Bluetooth) Not Working / Not Tested: - Audio (internal, works when headphones are connected to the rear port??) - PCIe clock related things and AER issues (these issues only appear on the LiveCD) - SuperIO related things - SATA acpi error? - libgfxinit some drm issue when using EDK 2 - Internal flashing Won't Test: - COM2 header - LPT header - PS/2 keyboard and mouse Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- A src/mainboard/lenovo/thinkcentre_m710s/Kconfig A src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name A src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk A src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m710s/board_info.txt A src/mainboard/lenovo/thinkcentre_m710s/bootblock.c A src/mainboard/lenovo/thinkcentre_m710s/data.vbt A src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb A src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl A src/mainboard/lenovo/thinkcentre_m710s/early_init.c A src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m710s/gpio.h A src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c A src/mainboard/lenovo/thinkcentre_m710s/romstage.c 15 files changed, 620 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/80343/1 diff --git a/src/mainboard/lenovo/thinkcentre_m710s/Kconfig b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig new file mode 100644 index 0000000..9aecf24 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_LENOVO_THINKCENTRE_M710S + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select SUPERIO_ITE_IT8629E + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + +config MAINBOARD_DIR + default "lenovo/thinkcentre_m710s" + +config MAINBOARD_PART_NUMBER + default "ThinkCentre M710s" + +endif # BOARD_LENOVO_THINKCENTRE_M710S diff --git a/src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name new file mode 100644 index 0000000..5a78582 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config BOARD_LENOVO_THINKCENTRE_M710S + bool "ThinkCentre M710s" diff --git a/src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk b/src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk new file mode 100644 index 0000000..5224305 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += early_init.c +bootblock-y += bootblock.c + +ramstage-y += early_init.c +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl b/src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl b/src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/lenovo/thinkcentre_m710s/board_info.txt b/src/mainboard/lenovo/thinkcentre_m710s/board_info.txt new file mode 100644 index 0000000..8379586 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://psref.lenovo.com/syspool/Sys/PDF/ThinkCentre/ThinkCentre_M710_SFF/T… +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2017 diff --git a/src/mainboard/lenovo/thinkcentre_m710s/bootblock.c b/src/mainboard/lenovo/thinkcentre_m710s/bootblock.c new file mode 100644 index 0000000..77b0a96 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/bootblock.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> + +#include "gpio.h" + +void bootblock_mainboard_init(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/lenovo/thinkcentre_m710s/data.vbt b/src/mainboard/lenovo/thinkcentre_m710s/data.vbt new file mode 100644 index 0000000..4855687 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb new file mode 100644 index 0000000..ad3c8a5c2 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# Model: IB250MH +# Untested: +# - COM2 +# - LPT +# - PS/2 Keyboard and Mouse +# - F_USB1 +# - SYS_FAN, AUX1_FAN, AUX2_FAN + +chip soc/intel/skylake + # FSP Configuration + register "eist_enable" = "true" + + device cpu_cluster 0 on end + device domain 0 on + device ref system_agent on end + device ref peg0 on # PCIE16X + register "PcieRpClkReqSupport[0]" = "true" + register "PcieRpClkReqNumber[0]" = "2" + register "PcieRpClkSrcNumber[0]" = "0" + end + device ref igpu on end + device ref south_xhci on + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # USB30 A + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB30 B + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # F_USB30_1 A + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # F_USB30_1 B + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # F_USB30_2 A + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # F_USB30_2 B + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + register "usb2_ports[7]" = "USB2_PORT_MID(OC5)" # USB_LAN A + register "usb2_ports[8]" = "USB2_PORT_MID(OC5)" # USB_LAN B + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # F_USB1 (Pins 5, 7) + register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" # F_USB1 (Pins 6, 8) + # Used by the SD/MMC reader. + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # F_USB2 (Pins 5, 7) + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB30 A + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB30 B + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # F_USB30_1 A + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # F_USB30_1 B + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # F_USB30_2 A + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC3)" # F_USB30_2 B + end + device ref thermal on end + device ref heci1 on end + device ref sata on + register "SataMode" = "SATA_AHCI" + register "SataSalpSupport" = "true" + register "SataPortsEnable[0]" = "true" # SATA1 + register "SataPortsEnable[1]" = "true" # SATA2 + register "SataPortsEnable[2]" = "true" # SATA3 + end + device ref pcie_rp5 on # USB_LAN + register "PcieRpEnable[4]" = "true" + register "PcieRpLtrEnable[4]" = "true" + register "PcieRpClkReqSupport[4]" = "false" + register "PcieRpClkSrcNumber[4]" = "5" + register "PcieRpAdvancedErrorReporting[4]" = "true" + end + device ref pcie_rp7 on # PCIE1X_2 + register "PcieRpEnable[6]" = "true" + register "PcieRpLtrEnable[6]" = "true" + register "PcieRpClkReqSupport[6]" = "true" + register "PcieRpClkReqNumber[6]" = "7" + register "PcieRpClkSrcNumber[6]" = "7" + register "PcieRpAdvancedErrorReporting[6]" = "true" + end + device ref pcie_rp8 on # PCIE1X_1 + register "PcieRpEnable[7]" = "true" + register "PcieRpLtrEnable[7]" = "true" + register "PcieRpClkReqSupport[7]" = "true" + register "PcieRpClkReqNumber[7]" = "8" + register "PcieRpClkSrcNumber[7]" = "8" + register "PcieRpAdvancedErrorReporting[7]" = "true" + end + device ref pcie_rp11 on # M2_WIFI + register "PcieRpEnable[10]" = "true" + register "PcieRpLtrEnable[10]" = "true" + register "PcieRpClkReqSupport[10]" = "true" + register "PcieRpClkReqNumber[10]" = "1" + register "PcieRpClkSrcNumber[10]" = "1" + register "PcieRpAdvancedErrorReporting[10]" = "true" + end + device ref pcie_rp21 on # M2_SSD + register "PcieRpEnable[20]" = "true" + register "PcieRpLtrEnable[20]" = "true" + register "PcieRpClkReqSupport[20]" = "true" + register "PcieRpClkReqNumber[20]" = "6" + register "PcieRpClkSrcNumber[20]" = "2" + register "PcieRpAdvancedErrorReporting[20]" = "true" + end + device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + chip superio/ite/it8629e + # CPU_FAN + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "1" + register "FAN1.smart.tmp_off" = "35" + register "FAN1.smart.tmp_start" = "60" + register "FAN1.smart.tmp_full" = "85" + register "FAN1.smart.tmp_delta" = "2" + register "FAN1.smart.pwm_start" = "20" + register "FAN1.smart.slope" = "24" + + register "FAN2.mode" = "FAN_MODE_OFF" # SYS_FAN + register "FAN3.mode" = "FAN_MODE_OFF" # AUX1_FAN + # FIXME: Add support for 6 fans. + #register "FAN6.mode" = "FAN_MODE_OFF" # AUX2_FAN + + register "ec.vin_mask" = "VIN_ALL" + + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_MODE_DISABLED" + register "TMPIN3.mode" = "THERMAL_DIODE" + + # Vendor values dumped using util/superiotool. + device pnp 2e.0 off end + device pnp 2e.1 on # COM1 + io 0x60 = 0x03f8 + irq 0x70 = 0x04 + irq 0xf1 = 0x50 + end + device pnp 2e.2 off end + device pnp 2e.3 off end + device pnp 2e.4 on + io 0x60 = 0x0a30 + io 0x62 = 0x0230 + irq 0x70 = 0x09 + irq 0xf0 = 0x40 + end + device pnp 2e.5 on # KB_MS (PS/2 Keyboard) + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 0x01 + irq 0x71 = 0x02 + irq 0xf0 = 0x48 + end + device pnp 2e.6 on # KB_MS (PS/2 Mouse) + irq 0x70 = 0x0c + irq 0x71 = 0x02 + end + device pnp 2e.7 on + irq 0x25 = 0x11 + irq 0x26 = 0x04 + irq 0x28 = 0x81 + irq 0x2a = 0x0d + irq 0x2c = 0x01 + io 0x60 = 0x0000 + io 0x62 = 0x0a00 + io 0x64 = 0x0000 + irq 0x70 = 0x00 + irq 0x71 = 0x09 + irq 0x72 = 0x20 + irq 0x73 = 0x38 + irq 0xb8 = 0x11 + irq 0xbc = 0xc0 + irq 0xbd = 0x03 + irq 0xc0 = 0x01 + irq 0xc1 = 0x04 + irq 0xc3 = 0x41 + irq 0xc8 = 0x01 + irq 0xc9 = 0x04 + irq 0xcb = 0x01 + irq 0xe9 = 0x07 + irq 0xf0 = 0x10 + irq 0xf4 = 0x0c + irq 0xf6 = 0x0e + irq 0xf8 = 0x08 + irq 0xf9 = 0x02 + irq 0xfc = 0x7c + end + device pnp 2e.8 on + io 0x60 = 0x0270 + irq 0x70 = 0x08 + end + device pnp 2e.a off end + end + chip drivers/pc80/tpm + device pnp c31.0 on end + end + end + device ref pmc on end + device ref hda on end + device ref smbus on end + device ref gbe on end # USB_LAN (Maps to PCIe Root Port 5) + end +end diff --git a/src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl b/src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl new file mode 100644 index 0000000..184fee0 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/lenovo/thinkcentre_m710s/early_init.c b/src/mainboard/lenovo/thinkcentre_m710s/early_init.c new file mode 100644 index 0000000..3c81c80 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/early_init.c @@ -0,0 +1,14 @@ + +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) + +void bootblock_mainboard_early_init(void) +{ + ite_reg_write(GPIO_DEV, 0x23, 0x49); + ite_reg_write(GPIO_DEV, 0x71, 0x09); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads b/src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads new file mode 100644 index 0000000..36094f5 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- TODO + ports : constant Port_List := + (DP1, + DP2, + DP3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/thinkcentre_m710s/gpio.h b/src/mainboard/lenovo/thinkcentre_m710s/gpio.h new file mode 100644 index 0000000..1cd7d25 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/gpio.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_A12, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A18, NONE), + PAD_NC(GPP_A19, NONE), + PAD_CFG_GPO(GPP_A20, 1, PLTRST), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_CFG_GPO(GPP_A23, 1, PLTRST), + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_B1, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_B3, NONE), + _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_B11, 0, DEEP), + PAD_CFG_GPO(GPP_B12, 1, DEEP), + _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_NC(GPP_B19, NONE), + _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_CFG_GPO(GPP_C12, 1, PLTRST), + PAD_CFG_GPO(GPP_C13, 0, PLTRST), + _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_D4, NONE), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_CFG_GPO(GPP_D14, 0, PLTRST), + PAD_NC(GPP_D15, NONE), + _PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_NC(GPP_E7, NONE), + _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_E12, 1, DEEP), + + /* ------- GPIO Group GPP_F ------- */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_NC(GPP_F7, NONE), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP), + _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_CFG_GPO(GPP_F22, 1, PLTRST), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + _PAD_CFG_STRUCT(GPP_G8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_G9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_G10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_G11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_NC(GPP_G12, NONE), + PAD_NC(GPP_G13, NONE), + PAD_NC(GPP_G14, NONE), + PAD_NC(GPP_G15, NONE), + PAD_NC(GPP_G16, NONE), + PAD_NC(GPP_G17, NONE), + PAD_NC(GPP_G18, NONE), + PAD_NC(GPP_G19, NONE), + PAD_CFG_GPO(GPP_G20, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_G21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_G22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_G23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* ------- GPIO Group GPP_H ------- */ + _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPO(GPP_H4, 1, PLTRST), + PAD_NC(GPP_H5, NONE), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_CFG_GPO(GPP_H10, 1, PLTRST), + PAD_CFG_GPO(GPP_H11, 1, PLTRST), + PAD_CFG_GPO(GPP_H12, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_H13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + PAD_NC(GPP_H18, NONE), + PAD_NC(GPP_H19, NONE), + _PAD_CFG_STRUCT(GPP_H20, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_H23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ + _PAD_CFG_STRUCT(GPD0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + PAD_CFG_GPO(GPD7, 1, PWROK), + _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + PAD_CFG_GPO(GPD11, 1, PWROK), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPO(GPP_I5, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c b/src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c new file mode 100644 index 0000000..dc009fb --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0662, // Vendor/Device ID: Realtek ACL662 + 0x17aa3102, // Subsystem ID + 12, + AZALIA_SUBVENDOR(0, 0x17aa3102), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x90170120), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19030), + AZALIA_PIN_CFG(0, 0x19, 0x02a11040), + AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), + AZALIA_PIN_CFG(0, 0x1b, 0x0221101f), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4047c62b), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x8086280b, // Vendor/Device ID: Intel HDMI + 0x80860101, // Subsystem ID + 4, + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x58560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/thinkcentre_m710s/romstage.c b/src/mainboard/lenovo/thinkcentre_m710s/romstage.c new file mode 100644 index 0000000..65cd625 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m710s/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <stdint.h> +#include <string.h> + +#include <soc/romstage.h> +#include <spd_bin.h> + +const u16 rcomp_resistors[] = {121, 75, 100}; +const u16 rcomp_targets[] = {50, 26, 20, 20, 26}; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; + + assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); + + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; + + struct spd_block blk = { + .addr_map = {0x50, 0x51, 0x52, 0x53}, + }; + + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + mem_cfg->MemorySpdPtr01 = (uintptr_t) blk.spd_array[1]; + mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[2]; + mem_cfg->MemorySpdPtr11 = (uintptr_t) blk.spd_array[3]; + dump_spd_info(&blk); + + memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/80343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc Gerrit-Change-Number: 80343 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: mb/google/brya: Create yavista variant
by Rasheed Hsueh (Code Review) 04 Feb '24

04 Feb '24

Rasheed Hsueh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80342?usp=email ) Change subject: mb/google/brya: Create yavista variant ...................................................................... mb/google/brya: Create yavista variant Create the yavista variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:321583226 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_YAVISTA Change-Id: I6fa464a4dcd9551a42e8746e64c724b3582dbe02 Signed-off-by: hsueh.rasheed <hsueh.rasheed(a)inventec.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/yavista/include/variant/ec.h A src/mainboard/google/brya/variants/yavista/include/variant/gpio.h A src/mainboard/google/brya/variants/yavista/memory/Makefile.mk A src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/yavista/overridetree.cb 8 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/80342/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index dae3f16..cd2d0ed 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -666,6 +666,7 @@ default "Dochi" if BOARD_GOOGLE_DOCHI default "Anraggar" if BOARD_GOOGLE_ANRAGGAR default "Xol" if BOARD_GOOGLE_XOL + default "Yavista" if BOARD_GOOGLE_YAVISTA config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -720,6 +721,7 @@ default "dochi" if BOARD_GOOGLE_DOCHI default "anraggar" if BOARD_GOOGLE_ANRAGGAR default "xol" if BOARD_GOOGLE_XOL + default "yavista" if BOARD_GOOGLE_YAVISTA config VBOOT select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index dcdf3c7..07dadce 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -155,3 +155,7 @@ config BOARD_GOOGLE_XOL bool "-> Xol" + +config BOARD_GOOGLE_YAVISTA + bool "-> Yavista" + select BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/variants/yavista/include/variant/ec.h b/src/mainboard/google/brya/variants/yavista/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/yavista/include/variant/gpio.h b/src/mainboard/google/brya/variants/yavista/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/yavista/memory/Makefile.mk b/src/mainboard/google/brya/variants/yavista/memory/Makefile.mk new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/memory/Makefile.mk @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt new file mode 100644 index 0000000..2499005 --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/yavista/overridetree.cb b/src/mainboard/google/brya/variants/yavista/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/yavista/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/80342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fa464a4dcd9551a42e8746e64c724b3582dbe02 Gerrit-Change-Number: 80342 Gerrit-PatchSet: 1 Gerrit-Owner: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: util/kconfig: Uprev to Linux 6.7's kconfig
by Patrick Georgi (Code Review) 04 Feb '24

04 Feb '24

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80263?usp=email ) Change subject: util/kconfig: Uprev to Linux 6.7's kconfig ...................................................................... util/kconfig: Uprev to Linux 6.7's kconfig Just a memory leak fix in Linux 6.7. Change-Id: I1ff302dafa01e78429a30ff18e21ffe0b45ce46e Signed-off-by: Patrick Georgi <patrick(a)coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80263 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M util/kconfig/patches/0007-kconfig-Allow-KCONFIG_STRICT-outside-of-confdata.c.patch M util/kconfig/patches/0008-kconfig-Add-wildcard-support-for-source.patch M util/kconfig/symbol.c 3 files changed, 21 insertions(+), 23 deletions(-) Approvals: Nico Huber: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/kconfig/patches/0007-kconfig-Allow-KCONFIG_STRICT-outside-of-confdata.c.patch b/util/kconfig/patches/0007-kconfig-Allow-KCONFIG_STRICT-outside-of-confdata.c.patch index f98729e..a9f3218 100644 --- a/util/kconfig/patches/0007-kconfig-Allow-KCONFIG_STRICT-outside-of-confdata.c.patch +++ b/util/kconfig/patches/0007-kconfig-Allow-KCONFIG_STRICT-outside-of-confdata.c.patch @@ -26,43 +26,43 @@ --- kconfig.orig/symbol.c +++ kconfig/symbol.c @@ -37,6 +37,7 @@ static struct symbol symbol_empty = { - + struct symbol *modules_sym; static tristate modules_val; +static int sym_warnings; - + enum symbol_type sym_get_type(struct symbol *sym) { -@@ -319,12 +320,14 @@ static void sym_warn_unmet_dep(struct sy +@@ -317,12 +318,14 @@ static void sym_warn_unmet_dep(struct sy " Selected by [m]:\n"); - + fputs(str_get(&gs), stderr); + sym_warnings++; } - + void sym_calc_value(struct symbol *sym) { struct symbol_value newval, oldval; struct property *prop; + const char *werror; struct expr *e; - + if (!sym) -@@ -340,8 +343,9 @@ void sym_calc_value(struct symbol *sym) +@@ -338,8 +341,9 @@ void sym_calc_value(struct symbol *sym) sym_calc_value(prop_get_symbol(prop)); } - + + werror = getenv("KCONFIG_WERROR"); + sym_warnings = 0; sym->flags |= SYMBOL_VALID; - oldval = sym->curr; - + switch (sym->type) { -@@ -432,6 +436,9 @@ void sym_calc_value(struct symbol *sym) +@@ -430,6 +434,9 @@ void sym_calc_value(struct symbol *sym) ; } - + + if (sym_warnings && werror) + exit(1); + diff --git a/util/kconfig/patches/0008-kconfig-Add-wildcard-support-for-source.patch b/util/kconfig/patches/0008-kconfig-Add-wildcard-support-for-source.patch index b476bc1..2e6a24f 100644 --- a/util/kconfig/patches/0008-kconfig-Add-wildcard-support-for-source.patch +++ b/util/kconfig/patches/0008-kconfig-Add-wildcard-support-for-source.patch @@ -28,7 +28,7 @@ +++ kconfig/lexer.l @@ -8,6 +8,7 @@ %{ - + #include <assert.h> +#include <glob.h> #include <limits.h> @@ -37,7 +37,7 @@ @@ -439,6 +440,32 @@ void zconf_nextfile(const char *name) current_file = file; } - + +void zconf_nextfiles(const char *wildcard) +{ + glob_t g; @@ -78,7 +78,7 @@ +void zconf_nextfiles(const char *name); int zconf_lineno(void); const char *zconf_curname(void); - + Index: kconfig/parser.y =================================================================== --- kconfig.orig/parser.y @@ -91,4 +91,4 @@ + zconf_nextfiles($2); free($2); }; - + diff --git a/util/kconfig/symbol.c b/util/kconfig/symbol.c index a50f131..34fc66e 100644 --- a/util/kconfig/symbol.c +++ b/util/kconfig/symbol.c @@ -123,9 +123,9 @@ static void sym_validate_range(struct symbol *sym) { struct property *prop; + struct symbol *range_sym; int base; long long val, val2; - char str[64]; switch (sym->type) { case S_INT: @@ -141,17 +141,15 @@ if (!prop) return; val = strtoll(sym->curr.val, NULL, base); - val2 = sym_get_range_val(prop->expr->left.sym, base); + range_sym = prop->expr->left.sym; + val2 = sym_get_range_val(range_sym, base); if (val >= val2) { - val2 = sym_get_range_val(prop->expr->right.sym, base); + range_sym = prop->expr->right.sym; + val2 = sym_get_range_val(range_sym, base); if (val <= val2) return; } - if (sym->type == S_INT) - sprintf(str, "%lld", val2); - else - sprintf(str, "0x%llx", val2); - sym->curr.val = xstrdup(str); + sym->curr.val = range_sym->curr.val; } static void sym_set_changed(struct symbol *sym) -- To view, visit https://review.coreboot.org/c/coreboot/+/80263?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ff302dafa01e78429a30ff18e21ffe0b45ce46e Gerrit-Change-Number: 80263 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
by Weimin Wu (Code Review) 04 Feb '24

04 Feb '24

Attention is currently required from: Dolan Liu, Jianeng Ceng, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Weimin Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80259?usp=email ) Change subject: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config ...................................................................... Patch Set 10: (1 comment) File src/mainboard/google/brya/variants/anraggar/variant.c: https://review.coreboot.org/c/coreboot/+/80259/comment/e2770129_e6acd476 : PS10, Line 32: 0 > Is it for C0? Yes, for Anraggar project, TCP0(C0) is connected to DB, TCP1(C1) is connected to MB. -- To view, visit https://review.coreboot.org/c/coreboot/+/80259?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53974ec7444912a63d0fe0a9303c9e5d6941f68d Gerrit-Change-Number: 80259 Gerrit-PatchSet: 10 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 05 Feb 2024 06:17:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: WIP: mainboard/lenovo: Add ThinkCentre M710s
by Nicholas Sudsgaard (Code Review) 04 Feb '24

04 Feb '24

Attention is currently required from: Alexander Couzens. Hello Alexander Couzens, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80279?usp=email to look at the new patch set (#3). Change subject: WIP: mainboard/lenovo: Add ThinkCentre M710s ...................................................................... WIP: mainboard/lenovo: Add ThinkCentre M710s Working: - Can boot Ubuntu using payloads: SeaBIOS, TianoCore EDK 2 - PCIe - M2 SSD - SATA - USB - LAN - CPU fan - VGA (DP bridge) - COM1 - TPM - Memory card reader (Technically just a USB) - Display ports - Audio (headphone jack, via display) - M2 WLAN (+ Bluetooth) Not Working / Not Tested: - Audio (internal, works when headphones are connected to the rear port??) - PCIe clock related things and AER issues (these issues only appear on the LiveCD) - SuperIO related things - SATA acpi error? - libgfxinit some drm issue when using EDK 2 - Internal flashing Won't Test: - COM2 header - LPT header - PS/2 keyboard and mouse Change-Id: Ic75164af96b05c2a15d7feaa71f231d2b3b0d922 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- A src/mainboard/lenovo/thinkcentre_m710s/Kconfig A src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name A src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk A src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m710s/board_info.txt A src/mainboard/lenovo/thinkcentre_m710s/bootblock.c A src/mainboard/lenovo/thinkcentre_m710s/data.vbt A src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb A src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl A src/mainboard/lenovo/thinkcentre_m710s/early_init.c A src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m710s/gpio.h A src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c A src/mainboard/lenovo/thinkcentre_m710s/romstage.c 15 files changed, 620 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/80279/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80279?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic75164af96b05c2a15d7feaa71f231d2b3b0d922 Gerrit-Change-Number: 80279 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: WIP: superio/ite: Add IT8629E
by Nicholas Sudsgaard (Code Review) 04 Feb '24

04 Feb '24

Nicholas Sudsgaard has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80341?usp=email ) Change subject: WIP: superio/ite: Add IT8629E ...................................................................... WIP: superio/ite: Add IT8629E Change-Id: I32a1d0473b1feab4cfbeb08b98b24734e60dea68 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/superio/ite/Makefile.mk A src/superio/ite/it8629e/Kconfig A src/superio/ite/it8629e/Makefile.mk A src/superio/ite/it8629e/chip.h A src/superio/ite/it8629e/it8629e.h A src/superio/ite/it8629e/superio.c 6 files changed, 118 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/80341/1 diff --git a/src/superio/ite/Makefile.mk b/src/superio/ite/Makefile.mk index 23d86da..b6d0199 100644 --- a/src/superio/ite/Makefile.mk +++ b/src/superio/ite/Makefile.mk @@ -10,6 +10,7 @@ subdirs-y += it8528e subdirs-y += it8613e subdirs-y += it8623e +subdirs-y += it8629e subdirs-y += it8712f subdirs-y += it8718f subdirs-y += it8720f diff --git a/src/superio/ite/it8629e/Kconfig b/src/superio/ite/it8629e/Kconfig new file mode 100644 index 0000000..e652a6a --- /dev/null +++ b/src/superio/ite/it8629e/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# Unfortunately, the datasheet for IT8629E is not public . Therefore, we will +# use the functionally closest chip (i.e. IT8728F) as a reference and try to +# reverse-engineer where necessary. + +# IT8629E seems to be very similar to IT8628E (again, no public datasheets), as +# the chip id is 0x8628. + +config SUPERIO_ITE_IT8629E + bool + select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_5FANS # Seems to support up to FAN_TAC6/FAN_CTL6 + select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN diff --git a/src/superio/ite/it8629e/Makefile.mk b/src/superio/ite/it8629e/Makefile.mk new file mode 100644 index 0000000..c574158 --- /dev/null +++ b/src/superio/ite/it8629e/Makefile.mk @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SUPERIO_ITE_IT8629E) += superio.c diff --git a/src/superio/ite/it8629e/chip.h b/src/superio/ite/it8629e/chip.h new file mode 100644 index 0000000..bad0266 --- /dev/null +++ b/src/superio/ite/it8629e/chip.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8629E_CHIP_H +#define SUPERIO_ITE_IT8629E_CHIP_H + +#include <superio/ite/common/env_ctrl_chip.h> + +struct superio_ite_it8629e_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8629E_CHIP_H */ diff --git a/src/superio/ite/it8629e/it8629e.h b/src/superio/ite/it8629e/it8629e.h new file mode 100644 index 0000000..573ca28 --- /dev/null +++ b/src/superio/ite/it8629e/it8629e.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8629E_H +#define SUPERIO_ITE_IT8629E_H + +#define IT8629E_FDC 0x00 // FDC +#define IT8629E_SP1 0x01 // Serial Port 1 +#define IT8629E_SP2 0x02 // Serial Port 2 +#define IT8629E_PP 0x03 // Parallel Port +#define IT8629E_EC 0x04 // Environment Controller +#define IT8629E_KBCK 0x05 // PS/2 Keyboard +#define IT8629E_KBCM 0x06 // PS/2 Mouse +#define IT8629E_GPIO 0x07 // GPIO +#define IT8629E_UNKNOWN 0x08 +#define IT8629E_IR 0x0a // Consumer IR + +#endif /* SUPERIO_ITE_IT8629E_H */ diff --git a/src/superio/ite/it8629e/superio.c b/src/superio/ite/it8629e/superio.c new file mode 100644 index 0000000..51f7c22 --- /dev/null +++ b/src/superio/ite/it8629e/superio.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <pc80/keyboard.h> +#include <superio/ite/common/env_ctrl.h> + +#include "chip.h" +#include "it8629e.h" + +static void it8629e_init(struct device *dev) +{ + const struct superio_ite_it8629e_config *conf = dev->chip_info; + const struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for FDC etc. */ + case IT8629E_EC: + res = probe_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + ite_ec_init(res->base, &conf->ec); + break; + case IT8629E_KBCK: + set_kbc_ps2_mode(); + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8629e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8629E_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, }, + { NULL, IT8629E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8629E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8629E_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ffc, }, + { NULL, IT8629E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ff8, }, + { NULL, IT8629E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0fff, 0x0fff, }, + { NULL, IT8629E_KBCM, PNP_IRQ0, }, + { NULL, IT8629E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, + 0x0fff, 0x0ff8, 0x0ff8, }, + { NULL, IT8629E_UNKNOWN, PNP_IO0 | PNP_IRQ0, 0xff8, }, + { NULL, IT8629E_IR, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8629e_ops = { + .name = "ITE IT8629E Super I/O", + .enable_dev = enable_dev +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/80341?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32a1d0473b1feab4cfbeb08b98b24734e60dea68 Gerrit-Change-Number: 80341 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: WIP: mainboard/lenovo: Add ThinkCentre M710s
by Nicholas Sudsgaard (Code Review) 04 Feb '24

04 Feb '24

Attention is currently required from: Alexander Couzens. Hello Alexander Couzens, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80279?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: WIP: mainboard/lenovo: Add ThinkCentre M710s ...................................................................... WIP: mainboard/lenovo: Add ThinkCentre M710s Working: - Can boot Ubuntu using payloads: SeaBIOS, TianoCore EDK 2 - PCIe - M2 SSD - SATA - USB - LAN - CPU fan - VGA (DP bridge) - COM1 - TPM - Memory card reader (Technically just a USB) - Display ports - Audio (headphone jack, via display) - M2 WLAN (+ Bluetooth) Not Working / Not Tested: - Audio (internal, works when headphones are connected to the rear port??) - PCIe clock related things and AER issues - SuperIO related things - SATA acpi error? - libgfxinit some drm issue when using EDK 2 - Internal flashing Won't Test: - COM2 header - LPT header - PS/2 keyboard and mouse Change-Id: Ic75164af96b05c2a15d7feaa71f231d2b3b0d922 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- A src/mainboard/lenovo/thinkcentre_m710s/Kconfig A src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name A src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk A src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m710s/board_info.txt A src/mainboard/lenovo/thinkcentre_m710s/bootblock.c A src/mainboard/lenovo/thinkcentre_m710s/data.vbt A src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb A src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl A src/mainboard/lenovo/thinkcentre_m710s/early_init.c A src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m710s/gpio.h A src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c A src/mainboard/lenovo/thinkcentre_m710s/romstage.c 15 files changed, 564 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/80279/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80279?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic75164af96b05c2a15d7feaa71f231d2b3b0d922 Gerrit-Change-Number: 80279 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
by Kapil Porwal (Code Review) 04 Feb '24

04 Feb '24

Attention is currently required from: Dolan Liu, Jianeng Ceng, Nick Vaccaro, Paul Menzel, Subrata Banik, Weimin Wu. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80259?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config ...................................................................... Patch Set 10: (1 comment) File src/mainboard/google/brya/variants/anraggar/variant.c: https://review.coreboot.org/c/coreboot/+/80259/comment/ce9bf99c_6397c557 : PS10, Line 32: 0 Is it for C0? -- To view, visit https://review.coreboot.org/c/coreboot/+/80259?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53974ec7444912a63d0fe0a9303c9e5d6941f68d Gerrit-Change-Number: 80259 Gerrit-PatchSet: 10 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 05 Feb 2024 04:27:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: brox: Handle GPI_INT pin value lower to GPI_WAKE
by Ashish Kumar Mishra (Code Review) 04 Feb '24

04 Feb '24

Attention is currently required from: Bora Guvendik, Karthik Ramasubramanian, Shelley Chen. Hello Bora Guvendik, Shelley Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80334?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: brox: Handle GPI_INT pin value lower to GPI_WAKE ...................................................................... brox: Handle GPI_INT pin value lower to GPI_WAKE In case where PAD_CFG_GPI_INT() is initialized with a pin value lower to PAD_CFG_GPI_IRQ_WAKE() for same GPIO community the set_ioapic_used() is only called for the PAD_CFG_GPI_IRQ_WAKE() pin. Due to this the IRQ associated with PAD_CFG_GPI_INT() is found free by find_free_unique_irq() during IRQ assignment and assigned to other pins which causes IRQ conflicts BUG=b:322984217 BRANCH=None TEST=Boot test on brox, check if correct IRQ assigned to EC Change-Id: I8c3d557e888b8d0ceac203f49b702910fba26d6d Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 3 files changed, 24 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/80334/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80334?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c3d557e888b8d0ceac203f49b702910fba26d6d Gerrit-Change-Number: 80334 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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