coreboot-gerrit February 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: smmstorev2: Load the communication buffer at SMM setup
by Arthur Heymans (Code Review) 05 Feb '24

05 Feb '24

Attention is currently required from: Benjamin Doron, Jérémy Compostella, Patrick Georgi, Patrick Rudolph. Hello Benjamin Doron, Jérémy Compostella, Patrick Georgi, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79738?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: smmstorev2: Load the communication buffer at SMM setup ...................................................................... smmstorev2: Load the communication buffer at SMM setup This removes the runtime SMI call to set up the communication buffer for SMMSTORE in favor of setting this buffer up during the installation of the smihandler. The reason is that it's less code in the handler and a time costly SMI is also avoided in ramstage. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I94dce77711f37f87033530f5ae48cb850a39341b --- M Documentation/drivers/smmstorev2.md M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c M src/drivers/smmstore/ramstage.c M src/drivers/smmstore/smi.c M src/drivers/smmstore/store.c M src/include/cpu/x86/smm.h M src/include/smmstore.h 8 files changed, 46 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/79738/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/79738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94dce77711f37f87033530f5ae48cb850a39341b Gerrit-Change-Number: 79738 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: smmstorev2: Load the communication buffer at SMM setup
by Arthur Heymans (Code Review) 05 Feb '24

05 Feb '24

Attention is currently required from: Jérémy Compostella, Patrick Georgi, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79738?usp=email ) Change subject: smmstorev2: Load the communication buffer at SMM setup ...................................................................... Patch Set 5: (1 comment) File src/include/cpu/x86/smm.h: https://review.coreboot.org/c/coreboot/+/79738/comment/bbb16ae7_e579429d : PS2, Line 94: SMMSTORE_V2 > > can we get rid of preprocessor guards by using a 0-sized variable when the condition isn't true? > > I don't think so. Only the last element can be such an array. Maybe it's worth leaving those in, unconditionally? What's 8 or 16 bytes after all? -- To view, visit https://review.coreboot.org/c/coreboot/+/79738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94dce77711f37f87033530f5ae48cb850a39341b Gerrit-Change-Number: 79738 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 05 Feb 2024 09:19:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86: Link page tables in stage if possible
by Arthur Heymans (Code Review) 05 Feb '24

05 Feb '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier, Patrick Rudolph. Hello Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80337?usp=email to look at the new patch set (#2). Change subject: cpu/x86: Link page tables in stage if possible ...................................................................... cpu/x86: Link page tables in stage if possible When switching back and forward from 32 to 64, for example to call a 32bit FSP or toe call the payload, a new page tables in the respective stage will be linked. The advantages of this approach are: - No need to determine a good place for page tables in cbfs that does not overlap. - Works with non memory mapped flash (however all coreboot targets currently do support this) - If later stages can use their own page tables which fits better with the vboot RO/RW flow A disadvantage is that it increases the stage size. This could be improved upon by used 1G pages and generating the pages at runtime. TESTED on google/vilbox and qemu/q35: boots to payload Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 --- M src/arch/x86/Kconfig M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/x86/64bit/Makefile.mk M src/cpu/x86/64bit/entry64.inc M src/cpu/x86/64bit/mode_switch.S M src/cpu/x86/64bit/mode_switch2.S M src/cpu/x86/64bit/pt.S M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/soc/amd/common/block/cpu/noncar/pre_c.S M src/soc/amd/picasso/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S 14 files changed, 26 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/80337/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80337?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 Gerrit-Change-Number: 80337 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: cpu/x86/64bit: Turn jumping to long mode into a macro
by Arthur Heymans (Code Review) 05 Feb '24

05 Feb '24

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier. Hello Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79261?usp=email to look at the new patch set (#4). Change subject: cpu/x86/64bit: Turn jumping to long mode into a macro ...................................................................... cpu/x86/64bit: Turn jumping to long mode into a macro This makes it easier to reuse, e.g. if you want to do it twice in one assembly file. Change-Id: Ida861338004187e4e714be41e17c8447fa4cf935 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/64bit/entry64.inc M src/cpu/x86/64bit/mode_switch.S M src/cpu/x86/64bit/mode_switch2.S M src/cpu/x86/sipi_vector.S M src/cpu/x86/smm/smm_stub.S M src/soc/amd/common/block/cpu/noncar/pre_c.S M src/soc/intel/common/block/cpu/car/cache_as_ram.S 11 files changed, 31 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/79261/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79261?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida861338004187e4e714be41e17c8447fa4cf935 Gerrit-Change-Number: 79261 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: cpu/x86: Link page tables in stage if possible
by Arthur Heymans (Code Review) 05 Feb '24

05 Feb '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80337?usp=email ) Change subject: cpu/x86: Link page tables in stage if possible ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80337/comment/0a17bc66_da849438 : PS1, Line 9: When switching back and forward from 32 to 64, for example to call a > I don't understand this. Where's the relation between protected mode calls and linking page tables into the stage? > > Doesn't this increase the stage size and thus occupies more flash in the end? That should be mentioned here as well. > What's the benefit of linking instead over having it in CBFS? Your right it should be mentioned why. With a VBOOT setup you don't want to rely on the RO path for things on the RW path. It does increase the size. Most targets since 2010 should have gigabyte pages so a follow-up could reduce the size increase a lot. Also with your patches to set up pages at runtime it could not end up in a flash size increase. -- To view, visit https://review.coreboot.org/c/coreboot/+/80337?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 Gerrit-Change-Number: 80337 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Feb 2024 08:41:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: security/tpm: resolve conflicts in TSS implementations
by Frans Hendriks (Code Review) 05 Feb '24

05 Feb '24

Attention is currently required from: Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Krystian Hebel, Matt DeVillier, Michał Żygowski, Raul Rangel, Sergii Dmytruk, Yu-Ping Wu. Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69160?usp=email ) Change subject: security/tpm: resolve conflicts in TSS implementations ...................................................................... Patch Set 29: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69160?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a Gerrit-Change-Number: 69160 Gerrit-PatchSet: 29 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Feb 2024 08:13:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: treewide: Change I2C/SMBUS master/slave to controller/target
by Martin L Roth (Code Review) 05 Feb '24

05 Feb '24

Attention is currently required from: Arthur Heymans, Caveh Jalali, Cliff Huang, Julius Werner. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77098?usp=email ) Change subject: treewide: Change I2C/SMBUS master/slave to controller/target ...................................................................... Patch Set 3: (2 comments) Patchset: PS1: > I think register names need to stay as they are. […] Done. PS1: > edit: That was supposed to say `__func__` without markdown getting in the way. The binaries are only mostly identical. https://review.coreboot.org/c/coreboot/+/77098/3/src/northbridge/intel/i945… -- To view, visit https://review.coreboot.org/c/coreboot/+/77098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c141fa4322de9e9ed208589f591560fed609825 Gerrit-Change-Number: 77098 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 05 Feb 2024 08:07:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: security/tpm: resolve conflicts in TSS implementations
by Erik van den Bogaert (Code Review) 05 Feb '24

05 Feb '24

Attention is currently required from: Christian Walter, Felix Held, Frans Hendriks, Fred Reitberger, Jason Glenesk, Krystian Hebel, Matt DeVillier, Michał Żygowski, Raul Rangel, Sergii Dmytruk, Yu-Ping Wu. Erik van den Bogaert has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69160?usp=email ) Change subject: security/tpm: resolve conflicts in TSS implementations ...................................................................... Patch Set 29: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69160?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a Gerrit-Change-Number: 69160 Gerrit-PatchSet: 29 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Feb 2024 07:50:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel: Use write{64,32,16,8}p and read{64,32,16,8}p
by Martin L Roth (Code Review) 05 Feb '24

05 Feb '24

Attention is currently required from: Arthur Heymans, Christian Walter, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Jeff Daly, Johnny Lin, Julius Werner, Kapil Porwal, Subrata Banik, Tarun, Tim Chu, Vanessa Eusebio. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80193?usp=email ) Change subject: soc/intel: Use write{64,32,16,8}p and read{64,32,16,8}p ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Is this really a good idea? I think we intentionally made the `write32()` function take a `void *` ( […] I'm with Julius on this. I think having just the write[8|16|32]() functions is preferable to having one that does the cast automatically. Let's get rid of the p versions. -- To view, visit https://review.coreboot.org/c/coreboot/+/80193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4022e3bbfacf35d0529e46dc82cf303dae9438e4 Gerrit-Change-Number: 80193 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 05 Feb 2024 07:36:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: WIP: superio/ite: Add IT8629E
by Nicholas Sudsgaard (Code Review) 05 Feb '24

05 Feb '24

Nicholas Sudsgaard has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80344?usp=email ) Change subject: WIP: superio/ite: Add IT8629E ...................................................................... WIP: superio/ite: Add IT8629E Change-Id: I44d0377da11f0e118017caa4357012df9373b322 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- A src/superio/ite/it8629e/Kconfig A src/superio/ite/it8629e/Makefile.mk A src/superio/ite/it8629e/chip.h A src/superio/ite/it8629e/it8629e.h A src/superio/ite/it8629e/superio.c 5 files changed, 117 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/80344/1 diff --git a/src/superio/ite/it8629e/Kconfig b/src/superio/ite/it8629e/Kconfig new file mode 100644 index 0000000..e652a6a --- /dev/null +++ b/src/superio/ite/it8629e/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# Unfortunately, the datasheet for IT8629E is not public . Therefore, we will +# use the functionally closest chip (i.e. IT8728F) as a reference and try to +# reverse-engineer where necessary. + +# IT8629E seems to be very similar to IT8628E (again, no public datasheets), as +# the chip id is 0x8628. + +config SUPERIO_ITE_IT8629E + bool + select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_5FANS # Seems to support up to FAN_TAC6/FAN_CTL6 + select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN diff --git a/src/superio/ite/it8629e/Makefile.mk b/src/superio/ite/it8629e/Makefile.mk new file mode 100644 index 0000000..c574158 --- /dev/null +++ b/src/superio/ite/it8629e/Makefile.mk @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SUPERIO_ITE_IT8629E) += superio.c diff --git a/src/superio/ite/it8629e/chip.h b/src/superio/ite/it8629e/chip.h new file mode 100644 index 0000000..bad0266 --- /dev/null +++ b/src/superio/ite/it8629e/chip.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8629E_CHIP_H +#define SUPERIO_ITE_IT8629E_CHIP_H + +#include <superio/ite/common/env_ctrl_chip.h> + +struct superio_ite_it8629e_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8629E_CHIP_H */ diff --git a/src/superio/ite/it8629e/it8629e.h b/src/superio/ite/it8629e/it8629e.h new file mode 100644 index 0000000..573ca28 --- /dev/null +++ b/src/superio/ite/it8629e/it8629e.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8629E_H +#define SUPERIO_ITE_IT8629E_H + +#define IT8629E_FDC 0x00 // FDC +#define IT8629E_SP1 0x01 // Serial Port 1 +#define IT8629E_SP2 0x02 // Serial Port 2 +#define IT8629E_PP 0x03 // Parallel Port +#define IT8629E_EC 0x04 // Environment Controller +#define IT8629E_KBCK 0x05 // PS/2 Keyboard +#define IT8629E_KBCM 0x06 // PS/2 Mouse +#define IT8629E_GPIO 0x07 // GPIO +#define IT8629E_UNKNOWN 0x08 +#define IT8629E_IR 0x0a // Consumer IR + +#endif /* SUPERIO_ITE_IT8629E_H */ diff --git a/src/superio/ite/it8629e/superio.c b/src/superio/ite/it8629e/superio.c new file mode 100644 index 0000000..51f7c22 --- /dev/null +++ b/src/superio/ite/it8629e/superio.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <pc80/keyboard.h> +#include <superio/ite/common/env_ctrl.h> + +#include "chip.h" +#include "it8629e.h" + +static void it8629e_init(struct device *dev) +{ + const struct superio_ite_it8629e_config *conf = dev->chip_info; + const struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for FDC etc. */ + case IT8629E_EC: + res = probe_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + ite_ec_init(res->base, &conf->ec); + break; + case IT8629E_KBCK: + set_kbc_ps2_mode(); + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8629e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8629E_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, }, + { NULL, IT8629E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8629E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8629E_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ffc, }, + { NULL, IT8629E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ff8, }, + { NULL, IT8629E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0fff, 0x0fff, }, + { NULL, IT8629E_KBCM, PNP_IRQ0, }, + { NULL, IT8629E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, + 0x0fff, 0x0ff8, 0x0ff8, }, + { NULL, IT8629E_UNKNOWN, PNP_IO0 | PNP_IRQ0, 0xff8, }, + { NULL, IT8629E_IR, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8629e_ops = { + .name = "ITE IT8629E Super I/O", + .enable_dev = enable_dev +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/80344?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44d0377da11f0e118017caa4357012df9373b322 Gerrit-Change-Number: 80344 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: newchange

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