coreboot-gerrit February 2024

coreboot-gerrit@coreboot.org

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3066 discussions

[XL] Change in coreboot[main]: mb/ocp: Drop tiogapass
by David Hendricks (Code Review) 19 Feb '24

19 Feb '24

Attention is currently required from: Felix Singer, Lean Sheng Tan, Morgan Jang, Nico Huber, Patrick Rudolph, Shuo Liu. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80171?usp=email ) Change subject: mb/ocp: Drop tiogapass ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Not sure if the deprecation process is necessary for something that was only added […] I think it's fair to remove Tioga Pass from the main branch at this point. Release notes would be nice - I can help write them to explain the ecosystem situation and where potential users might look. There is still a lot of Skylake-SP generation hardware in use and it can be supported by at least one of our coreboot vendors. Intel has not (and won't) authorize the public release of FSP binaries for it, so while the hardware has a few more years of life left software development basically can't progress beyond where it is in the current release anyway. -- To view, visit https://review.coreboot.org/c/coreboot/+/80171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I838b9ea3955d31ea393494c2e726845fe234ef3a Gerrit-Change-Number: 80171 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin Roth <coreboot.org(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Mon, 19 Feb 2024 18:49:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: device/pnp_device: Skip init on disabled functions
by Nico Huber (Code Review) 19 Feb '24

19 Feb '24

Attention is currently required from: Matt DeVillier. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80598?usp=email ) Change subject: device/pnp_device: Skip init on disabled functions ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80598/comment/129d43e4_747212e9 : PS1, Line 15: in the log / don't cause any errors. > [DEBUG] PNP: 002e.1 60 <- [0x00000000000003f8 - 0x00000000000003ff] size 0x00000008 gran 0x03 io […] So these 'decode base 0' prints are from `soc/intel/common/block/lpc`. And I think they are right. That code shouldn't be called for disabled devices. But that's an issue local to the Intel code which tries to re-implement resource things. Never really understood that code (it was ported from APL just because it was there, IIRC), but I'm sure a simple ``` if (!dev->enabled) return; ``` in pch_lpc_loop_resources() should be safe. File src/device/pnp_device.c: https://review.coreboot.org/c/coreboot/+/80598/comment/e80b0061_1f3a0656 : PS1, Line 403: dev->ops = ops; > where do we generate SSDT entries for disabled devices? Dunno. That was just an example from the top of my head. It's just that we virtually always have the ops assigned and it might take some thought to figure out if it's right not to have them. If it fixes something beside the Intel code (see other comment), I would prefer to move the new if/continue below the ops assignment. -- To view, visit https://review.coreboot.org/c/coreboot/+/80598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c9d5cf34947535bf249b91f78d6fabfb28729ea Gerrit-Change-Number: 80598 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 19 Feb 2024 18:45:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/cannonlake: select SOC_INTEL_COMMON_BLOCK_DTT
by Felix Singer (Code Review) 19 Feb '24

19 Feb '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80556?usp=email ) Change subject: soc/intel/cannonlake: select SOC_INTEL_COMMON_BLOCK_DTT ...................................................................... soc/intel/cannonlake: select SOC_INTEL_COMMON_BLOCK_DTT Select this at the SoC level (like other modern Intel SoCs), and drop it from individual boards which selected it. Change-Id: I838ada7dfe948c58a5bb9805ade289b07368aa63 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80556 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/puff/Kconfig M src/soc/intel/cannonlake/Kconfig 3 files changed, 1 insertion(+), 2 deletions(-) Approvals: Nico Huber: Looks good to me, but someone else must approve build bot (Jenkins): Verified Eric Lai: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 32ce7ed..493db33 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -26,7 +26,6 @@ select MAINBOARD_HAS_TPM2 select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SOC_INTEL_COMETLAKE_1 - select SOC_INTEL_COMMON_BLOCK_DTT select SPI_TPM select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig index 348aa1e..0abe53a 100644 --- a/src/mainboard/google/puff/Kconfig +++ b/src/mainboard/google/puff/Kconfig @@ -31,7 +31,6 @@ select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select SOC_INTEL_COMETLAKE_1 - select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_CSE_LITE_SKU select SPD_CACHE_IN_FMAP select SPD_READ_BY_WORD diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 0d1ad4d..ab2efc3 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -46,6 +46,7 @@ select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE + select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA -- To view, visit https://review.coreboot.org/c/coreboot/+/80556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I838ada7dfe948c58a5bb9805ade289b07368aa63 Gerrit-Change-Number: 80556 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/cannonlake: select SOC_INTEL_COMMON_BLOCK_DTT
by Felix Singer (Code Review) 19 Feb '24

19 Feb '24

Attention is currently required from: Matt DeVillier, Nick Vaccaro, Nico Huber, Subrata Banik. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80556?usp=email ) Change subject: soc/intel/cannonlake: select SOC_INTEL_COMMON_BLOCK_DTT ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > for boards which previously didn't select DTT *and* didn't select the Intel DPTF driver, they will n […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I838ada7dfe948c58a5bb9805ade289b07368aa63 Gerrit-Change-Number: 80556 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 19 Feb 2024 18:09:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/purism/librem_cnl: Drop selection of USE_LEGACY_8254_TIMER
by Felix Singer (Code Review) 19 Feb '24

19 Feb '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80602?usp=email ) Change subject: mb/purism/librem_cnl: Drop selection of USE_LEGACY_8254_TIMER ...................................................................... mb/purism/librem_cnl: Drop selection of USE_LEGACY_8254_TIMER It's not needed other than for booting w/SeaBIOS, where it is already selected by default, and enabling it with edk2 payload prevents Linux/ Windows from fully entering S0ix. TEST=build/boot purism/librem_cnl (Mini v2), verify Win11/Linux able to enter and exit S0ix properly. Change-Id: I974a82bedc4e06f48ce801f2bc0c29afbd80ffcf Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80602 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/purism/librem_cnl/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Martin L Roth: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig index 24413b2..ab6a67f 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -13,7 +13,6 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_CACHE_IN_FMAP select SPD_READ_BY_WORD - select USE_LEGACY_8254_TIMER config BOARD_PURISM_LIBREM_MINI select BOARD_PURISM_BASEBOARD_LIBREM_CNL -- To view, visit https://review.coreboot.org/c/coreboot/+/80602?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I974a82bedc4e06f48ce801f2bc0c29afbd80ffcf Gerrit-Change-Number: 80602 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/hp/snb_ivb_desktops: Make baseboard more generic
by Nicholas Chin (Code Review) 19 Feb '24

19 Feb '24

Attention is currently required from: Felix Singer, Riku Viitanen. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79543?usp=email ) Change subject: mb/hp/snb_ivb_desktops: Make baseboard more generic ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icce22efb8d353359781db3f03c67058d8fbe11b8 Gerrit-Change-Number: 79543 Gerrit-PatchSet: 10 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Mon, 19 Feb 2024 18:05:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/starlabs/starbook: Always include the tcss.asl
by Felix Held (Code Review) 19 Feb '24

19 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80485?usp=email ) Change subject: mb/starlabs/starbook: Always include the tcss.asl ...................................................................... mb/starlabs/starbook: Always include the tcss.asl The tcss.asl doesn't just relate to tcss, it is required for core scheduling, so include it for all platforms. Change-Id: I781ba8756e06133799e8d6d91302968cc3ea0a56 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80485 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/dsdt.asl 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/dsdt.asl b/src/mainboard/starlabs/starbook/dsdt.asl index 93a1ac5..be817e3 100644 --- a/src/mainboard/starlabs/starbook/dsdt.asl +++ b/src/mainboard/starlabs/starbook/dsdt.asl @@ -33,10 +33,8 @@ #elif CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE) #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/alderlake/acpi/southbridge.asl> -#if CONFIG(DRIVERS_INTEL_USB4_RETIMER) #include <soc/intel/alderlake/acpi/tcss.asl> #endif -#endif #include <soc/intel/common/block/acpi/acpi/gna.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/80485?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I781ba8756e06133799e8d6d91302968cc3ea0a56 Gerrit-Change-Number: 80485 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: i2c/drivers/generic: Add support for including a rotation matrix
by Felix Held (Code Review) 19 Feb '24

19 Feb '24

Attention is currently required from: Paul Menzel, Sean Rhodes. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80179?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: i2c/drivers/generic: Add support for including a rotation matrix ...................................................................... Patch Set 4: (1 comment) File src/drivers/i2c/generic/chip.h: https://review.coreboot.org/c/coreboot/+/80179/comment/7c3e581b_fa1f03eb : PS4, Line 81: int using bool would make it more obvious that this is a boolean option and not an integer -- To view, visit https://review.coreboot.org/c/coreboot/+/80179?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id4a940d999a0e300a6fe21269f18bab6e3c0523c Gerrit-Change-Number: 80179 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 19 Feb 2024 17:45:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/alderlake: Include ADL-N ID 5 0x4618
by Felix Held (Code Review) 19 Feb '24

19 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80488?usp=email ) Change subject: soc/intel/alderlake: Include ADL-N ID 5 0x4618 ...................................................................... soc/intel/alderlake: Include ADL-N ID 5 0x4618 This patch adds support for using ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80488 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/intel/adlrvp/ramstage.c M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/vr_config.c 6 files changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c index 3ffc35b..7a6bb5d 100644 --- a/src/mainboard/intel/adlrvp/ramstage.c +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -25,6 +25,7 @@ { PCI_DID_INTEL_ADL_N_ID_2, 6, 3000, 6000, 25000, 25000, 78000 }, { PCI_DID_INTEL_ADL_N_ID_3, 6, 3000, 6000, 25000, 25000, 78000 }, { PCI_DID_INTEL_ADL_N_ID_4, 6, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, 3000, 6000, 25000, 25000, 78000 }, }; WEAK_DEV_PTR(dptf_policy); diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index c4863b9..2a4f31a 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -61,6 +61,7 @@ { PCI_DID_INTEL_ADL_N_ID_2, "Alderlake-N" }, { PCI_DID_INTEL_ADL_N_ID_3, "Alderlake-N" }, { PCI_DID_INTEL_ADL_N_ID_4, "Alderlake-N" }, + { PCI_DID_INTEL_ADL_N_ID_5, "Alderlake-N" }, { PCI_DID_INTEL_ADL_S_ID_1, "Alderlake-S (8+8)" }, { PCI_DID_INTEL_ADL_S_ID_2, "Alderlake-S" }, { PCI_DID_INTEL_ADL_S_ID_3, "Alderlake-S (8+4)" }, diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 2f94db6..437d675 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -153,6 +153,7 @@ { PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_N_ID_4, ADL_N_021_6W_CORE, TDP_6W }, + { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_35W_CORE, TDP_35W }, { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_65W_CORE, TDP_65W }, { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_125W_CORE, TDP_125W }, diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index fafd54d..2d25bb6 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -240,6 +240,7 @@ PCI_DID_INTEL_ADL_N_ID_2, PCI_DID_INTEL_ADL_N_ID_3, PCI_DID_INTEL_ADL_N_ID_4, + PCI_DID_INTEL_ADL_N_ID_5, }; const uint16_t rpl_hx_mch_ids[] = { diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 5edfbcc..cb54598 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -539,6 +539,7 @@ case PCI_DID_INTEL_ADL_N_ID_2: case PCI_DID_INTEL_ADL_N_ID_3: case PCI_DID_INTEL_ADL_N_ID_4: + case PCI_DID_INTEL_ADL_N_ID_5: return ICC_MAX_ID_ADL_N_MA; case PCI_DID_INTEL_ADL_S_ID_1: case PCI_DID_INTEL_ADL_S_ID_3: diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 3467bdd..911e1dd 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -127,6 +127,7 @@ { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, @@ -187,6 +188,7 @@ { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_ICC(37, 26) }, { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, -- To view, visit https://review.coreboot.org/c/coreboot/+/80488?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672 Gerrit-Change-Number: 80488 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/common: Add ADL_N ID 5 0x4618
by Felix Held (Code Review) 19 Feb '24

19 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80487?usp=email ) Change subject: soc/intel/common: Add ADL_N ID 5 0x4618 ...................................................................... soc/intel/common: Add ADL_N ID 5 0x4618 This patch adds ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I47bd8fa991a48d30be4975b7965f2c3c859836dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/80487 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c 2 files changed, 2 insertions(+), 0 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d2f429c..f980f4e 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4260,6 +4260,7 @@ #define PCI_DID_INTEL_ADL_N_ID_2 0x461B #define PCI_DID_INTEL_ADL_N_ID_3 0x461c #define PCI_DID_INTEL_ADL_N_ID_4 0x4614 +#define PCI_DID_INTEL_ADL_N_ID_5 0x4618 #define PCI_DID_INTEL_MTL_M_ID 0x7D00 #define PCI_DID_INTEL_MTL_P_ID_1 0x7D01 #define PCI_DID_INTEL_MTL_P_ID_2 0x7D02 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 5c79599..99c145d 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -516,6 +516,7 @@ PCI_DID_INTEL_ADL_N_ID_2, PCI_DID_INTEL_ADL_N_ID_3, PCI_DID_INTEL_ADL_N_ID_4, + PCI_DID_INTEL_ADL_N_ID_5, PCI_DID_INTEL_RPL_HX_ID_1, PCI_DID_INTEL_RPL_HX_ID_2, PCI_DID_INTEL_RPL_HX_ID_3, -- To view, visit https://review.coreboot.org/c/coreboot/+/80487?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47bd8fa991a48d30be4975b7965f2c3c859836dd Gerrit-Change-Number: 80487 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2024