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Change subject: Update fsp submodule to upstream master
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/brya: Create glassway variant
......................................................................
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Change subject: mb/google/brya: Create glassway variant
......................................................................
mb/google/brya: Create glassway variant
Create the glassway variant of the nivviks reference board by copying
the template files to a new directory named for the variant.
BUG=b:319071869
BRANCH=firmware-nissa-15217.B
TEST=None
Change-Id: I597666a5be6f71b82c7baddbe343da3d5117dd1c
Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/glassway/include/variant/ec.h
A src/mainboard/google/brya/variants/glassway/include/variant/gpio.h
A src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
A src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/glassway/overridetree.cb
8 files changed, 48 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/80636/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 4a38af5..eb937523 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -234,6 +234,9 @@
select INTEL_GMA_HAVE_VBT
select SOC_INTEL_RAPTORLAKE
+config BOARD_GOOGLE_GLASSWAY
+ select BOARD_GOOGLE_BASEBOARD_NISSA
+
config BOARD_GOOGLE_GOTHRAX
select BOARD_GOOGLE_BASEBOARD_NISSA
select DRIVERS_GENERIC_GPIO_KEYS
@@ -590,6 +593,7 @@
default 0x0 if BOARD_GOOGLE_QUANDISO
default 0x0 if BOARD_GOOGLE_ANRAGGAR
default 0x1 if BOARD_GOOGLE_XOL
+ default 0x0 if BOARD_GOOGLE_GLASSWAY
config DRIVER_TPM_I2C_ADDR
hex
@@ -673,6 +677,7 @@
default "Dochi" if BOARD_GOOGLE_DOCHI
default "Anraggar" if BOARD_GOOGLE_ANRAGGAR
default "Xol" if BOARD_GOOGLE_XOL
+ default "Glassway" if BOARD_GOOGLE_GLASSWAY
config VARIANT_DIR
default "brya0" if BOARD_GOOGLE_BRYA0
@@ -727,6 +732,7 @@
default "dochi" if BOARD_GOOGLE_DOCHI
default "anraggar" if BOARD_GOOGLE_ANRAGGAR
default "xol" if BOARD_GOOGLE_XOL
+ default "glassway" if BOARD_GOOGLE_GLASSWAY
config VBOOT
select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 4371597..bea92b6 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -56,6 +56,9 @@
config BOARD_GOOGLE_GLADIOS
bool "-> Gladios"
+config BOARD_GOOGLE_GLASSWAY
+ bool "-> Glassway"
+
config BOARD_GOOGLE_GOTHRAX
bool "-> Gothrax"
diff --git a/src/mainboard/google/brya/variants/glassway/include/variant/ec.h b/src/mainboard/google/brya/variants/glassway/include/variant/ec.h
new file mode 100644
index 0000000..7a2a6ff
--- /dev/null
+++ b/src/mainboard/google/brya/variants/glassway/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h b/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h
new file mode 100644
index 0000000..c4fe342
--- /dev/null
+++ b/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk b/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
new file mode 100644
index 0000000..eace2e4
--- /dev/null
+++ b/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder
diff --git a/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
new file mode 100644
index 0000000..fa24790
--- /dev/null
+++ b/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
@@ -0,0 +1 @@
+DRAM Part Name ID to assign
diff --git a/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
new file mode 100644
index 0000000..2499005
--- /dev/null
+++ b/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb
new file mode 100644
index 0000000..4f2c04a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+ device domain 0 on
+ end
+
+end
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Change subject: lib/hardwaremain: align '\' in multi-line macro
......................................................................
Patch Set 1: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80573?usp=email )
Change subject: mb/google/dedede/var/beadrix: Disable un-used C1 port by daughterboard
......................................................................
mb/google/dedede/var/beadrix: Disable un-used C1 port by daughterboard
Probe usb ports by FW_CONFIG setting to disable C1 port on
beadrix poin2 new daughterboard without C1 port.
BUG=b:316365055
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot
Change-Id: I494a922d2b04dcf7bd35680f5d95f8463e225f2d
Signed-off-by: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80573
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Derek Huang <derekhuang(a)google.com>
---
M src/mainboard/google/dedede/variants/beadrix/overridetree.cb
1 file changed, 18 insertions(+), 0 deletions(-)
Approvals:
Kevin Yang: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Derek Huang: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
index 7145ecf..0554baf 100644
--- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
@@ -109,6 +109,24 @@
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
+ register "desc" = ""Right Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(2, 1)"
+ device usb 2.1 on
+ probe DB_PORTS DB_PORTS_1C_LTE
+ probe DB_PORTS DB_PORTS_1C
+ end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(2, 1)"
+ device usb 3.1 on
+ probe DB_PORTS DB_PORTS_1C_LTE
+ probe DB_PORTS DB_PORTS_1C
+ end
+ end
+ chip drivers/usb/acpi
register "desc" = ""UFCamera""
register "type" = "UPC_TYPE_INTERNAL"
device usb 2.5 on end
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79887?usp=email )
Change subject: mb/google/dedede/var/beadrix: Generate SPD ID for supported memory part
......................................................................
mb/google/dedede/var/beadrix: Generate SPD ID for supported memory part
Add beadrix supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. CXMT CXDB4CBAM-ML-A
BUG=b:321830738
TEST=Use part_id_gen to generate related settings
Change-Id: I3a6925395b52dc7aa5c0f93b8820099369db4dbf
Signed-off-by: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79887
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Derek Huang <derekhuang(a)google.com>
---
M src/mainboard/google/dedede/variants/beadrix/memory/Makefile.mk
M src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt
3 files changed, 5 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Derek Huang: Looks good to me, approved
Kevin Yang: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.mk b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.mk
index f77c501..d260b55 100644
--- a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.mk
+++ b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.mk
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
-# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt
+# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory/ src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt
SPD_SOURCES =
SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, K4U6E3S4AA-MGCR, H54G46CYRBX267
+SPD_SOURCES += spd/lp4x/set-1/spd-11.hex # ID = 1(0b0001) Parts = CXDB4CBAM-ML-A
diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt
index 36ca69b..ddbed1a 100644
--- a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt
@@ -1,9 +1,10 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
-# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt
+# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory/ src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt
DRAM Part Name ID to assign
MT53E512M32D1NP-046 WT:B 0 (0000)
K4U6E3S4AA-MGCR 0 (0000)
H54G46CYRBX267 0 (0000)
+CXDB4CBAM-ML-A 1 (0001)
diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt
index 7fd0305..56e9d6e 100644
--- a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt
@@ -12,3 +12,4 @@
MT53E512M32D1NP-046 WT:B
K4U6E3S4AA-MGCR
H54G46CYRBX267
+CXDB4CBAM-ML-A
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Change subject: mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)
......................................................................
Patch Set 5:
(9 comments)
Patchset:
PS5:
Looks nice, just a few small things. 👍
File src/mainboard/lenovo/m900_tiny/Kconfig:
PS5:
Add SPDX license here.
File src/mainboard/lenovo/m900_tiny/Kconfig.name:
PS5:
Add SPDX license here.
File src/mainboard/lenovo/m900_tiny/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/80610/comment/20119dae_f72b32bd :
PS5, Line 1: GPL-2.0-or-later
Empty files should use the CC-PDDC license (refer to CB:66497)
File src/mainboard/lenovo/m900_tiny/cmos.default:
PS5:
Add SPDX license here (refer to CB:80597)
File src/mainboard/lenovo/m900_tiny/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80610/comment/1c2ec95a_12aa271e :
PS5, Line 133: register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Front Port 1
I would suggest this format for bulk definitions.
```
register "usb2_ports" = "{
[0] = ..., // comment
}"
```
The stuff inside the quotations is just C (hence the '//' style comment).
https://review.coreboot.org/c/coreboot/+/80610/comment/c8ef70d1_d44f4d5f :
PS5, Line 142: register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Front Port 1
Here too.
https://review.coreboot.org/c/coreboot/+/80610/comment/fa081caf_9756be5b :
PS5, Line 154: register "SataPortsEnable" = "{ \
'\' is not necessary.
https://review.coreboot.org/c/coreboot/+/80610/comment/0b11711b_97c13cd1 :
PS5, Line 162: register "SataPortsHotPlug" = "{ \
Here too.
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