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Change subject: soc/intel/xeon_sp: Add support for is_ioat_iio_stack_res
......................................................................
soc/intel/xeon_sp: Add support for is_ioat_iio_stack_res
IOAT is the term for the on-chip accelerator technology of
Xeon-SP. In CPX and SPR, IOAT stack is also named as DINO stack.
Different SoC has different check criteria for IOAT stacks,
this patch introduces an util function to abstract these differences
as well as cleaning up the usage of names.
TEST=intel/archercity CRB
Change-Id: I376928ad89b68b294734000678dad6f070d3c97d
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/spr/ioat.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/uncore_acpi.c
5 files changed, 25 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/80578/6
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Change subject: soc/intel/alderlake: Sync UPD Usb4CmMode with Kconfig
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/80486/comment/13e01751_12887fe6 :
PS4, Line 682: SOC_INTEL_ALDERLAKE_PCH_M
> > No, it's Alderlake too - FSP in the repo has it […]
P, N and S have it
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Change subject: soc/intel/alderlake: Sync UPD Usb4CmMode with Kconfig
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/80486/comment/c189100a_92416bd4 :
PS4, Line 682: SOC_INTEL_ALDERLAKE_PCH_M
> No, it's Alderlake too - FSP in the repo has it
do you mean ADL-P or ADL-N?
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Change subject: soc/intel/xeon_sp: Align resources to 4K
......................................................................
Patch Set 2: Code-Review+1
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Change subject: drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug
......................................................................
drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug
Starting with Intel CPX there is a bug in the reference code during
the Pipe init. This code synchronises the CAR between sockets in FSP-M.
This code implicitly assumes that the top of FSP heap is FspStackBase +
FspStackSize and the bottom is the bottom of CAR.
Work around this issue by making that implicit assumption done in FSP
explicit in the coreboot linker script and allocation.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4
---
M src/arch/x86/car.ld
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/memory_init.c
M src/soc/intel/xeon_sp/cpx/Kconfig
M src/soc/intel/xeon_sp/spr/Kconfig
5 files changed, 33 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/80579/4
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Change subject: drivers/intel/fsp: Add a workaround for multi socket xeon-sp
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80579/comment/d8063d3d_aa31c28e :
PS3, Line 7: Add a workaround for multi socket xeon-sp
> Maybe: […]
Done
https://review.coreboot.org/c/coreboot/+/80579/comment/efbd064f_b0dc3f8d :
PS3, Line 9: there
> their?
Done
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Change subject: mb/lenovo/m900_tiny: add board
......................................................................
Patch Set 4: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80610/comment/bdd05f47_dfe99fc3 :
PS4, Line 9: Add Lenovo ThinkCentre M700 / M900 Tiny mainboard.
I’d use this for the commit message summary:
> mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)
(Or the name of the PCH or so.)
Patchset:
PS4:
Nice work.
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Change subject: mb/google/volteer: Fix S0i3 regression
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80612/comment/97974f46_f522bffc :
PS1, Line 7: Fix S0i3 regression
Maybe:
> Disable PM ACPI timer to fix S0i3 regression
https://review.coreboot.org/c/coreboot/+/80612/comment/14d25a8c_0a81c3e6 :
PS1, Line 18: Linx
Linux
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Change subject: soc/intel/alderlake: Sync UPD Usb4CmMode with Kconfig
......................................................................
Patch Set 5:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80486/comment/94ecea4e_10f37175 :
PS4, Line 7: Correctly set Usb4CmMode
> Maybe more specific: […]
Done
https://review.coreboot.org/c/coreboot/+/80486/comment/46fe1c36_b9ad6b5d :
PS4, Line 11: mismatched.
> Should fit on the line above in 75 characters per line.
Done
https://review.coreboot.org/c/coreboot/+/80486/comment/765901c4_d366ac8e :
PS4, Line 13: timeout
> time out
Done
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/80486/comment/3b16972a_ea4e1f4c :
PS4, Line 682: SOC_INTEL_ALDERLAKE_PCH_M
> I thought `Usb4CmMode` existed for `SOC_INTEL_RAPTORLAKE` header alone. […]
No, it's Alderlake too - FSP in the repo has it
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