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Change subject: mb/google/volteer: Fix S0i3 regression
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Weird, why TGL have issue now. I believe TGL doesn't have this issue before.
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Change subject: mb/lenovo/m920q: add board
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80609/comment/46b38f91_d985e5fc :
PS3, Line 7: mb/lenovo/m920q: add board
Maybe also put the PCH/socket in it too:
> mb/lenovo: Add ThinkCentre M920q (Cannon Lake)
https://review.coreboot.org/c/coreboot/+/80609/comment/7a1944e5_a69b90c6 :
PS3, Line 30: PCIex8
Maybe: PCIe x8
Patchset:
PS3:
Very nice work. Thank you!
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Change subject: soc/intel/common/block/fast_spi: probe for 2nd flash component
......................................................................
Patch Set 2: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80608/comment/cf1d6768_0f58ff89 :
PS2, Line 10: used
Was the driver replaced?
https://review.coreboot.org/c/coreboot/+/80608/comment/6d0b97d9_5b05b081 :
PS2, Line 12: Some boards
Please give one example.
File src/soc/intel/common/block/fast_spi/fast_spi_flash.c:
https://review.coreboot.org/c/coreboot/+/80608/comment/a83d8548_a3933937 :
PS2, Line 58: hord
HORD?
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Change subject: soc/intel/xeon_sp: Add support for is_ioat_iio_stack_res
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/xeon_sp/uncore_acpi.c:
https://review.coreboot.org/c/coreboot/+/80578/comment/3183184d_51c47a5f :
PS5, Line 554: current = acpi_create_satc(current, hob);
Probably best to guard this with if CONFIG(HAVE_IOAT_DOMAINS). I'm not sure if it will behave properly with an empty satc?
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Change subject: soc/intel/xeon_sp: Align resources to 4K
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
> one more question is: what if we without this change? would there be any errors or confusing behavio […]
Yes, it would take the BAR enable bit as address and thus be of by one.
File src/soc/intel/xeon_sp/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/80548/comment/d4e46634_5a18a3d4 :
PS1, Line 14: #define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, 10, desc_)
> Mask bit 10 equals to 1K. I believe we would like to use 4K, right? […]
Good catch!
Updated to 12 bits and thus aligning to 4K.
The reason is not to align with the page size, but the minimal alignment used by all BARs. Here the VTBAR has the lowest alignment.
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Change subject: soc/intel/xeon_sp: Align resources to 4K
......................................................................
soc/intel/xeon_sp: Align resources to 4K
The lower bit of the BAR might be used for something else,
like enable bits, so mask the lower 12 bits and align all
base address to 4K.
Confirmed that all BARs have a minimum alignment of 4K, so that
masking the lower bits doesn't change the reported address.
The alignment of the VTD BARs is:
- VTD_MMCFG_BASE_CSR 64 MiB
- VTD_MMIOL_CSR 1 MiB
- VTD_NCMEM_BASE_CSR 64 MiB
- VTD_TSEG_BASE_CSR 1 MiB
- VTD_BAR_CSR 4 KiB
Change-Id: I9a7b963c0074246616968dd15c147f4916297d59
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/include/soc/iomap.h
M src/soc/intel/xeon_sp/uncore.c
2 files changed, 2 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/80548/2
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Change subject: soc/intel/xeon_sp: Put SRAT util macros into Xeon-SP ACPI header
......................................................................
Patch Set 6: Code-Review+2
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Change subject: soc/intel/xeon_sp: Add support for is_ioat_iio_stack_res
......................................................................
Patch Set 5: Code-Review+2
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Change subject: soc/intel/xeon_sp: Use ACPI common flags in SRAT generation
......................................................................
Patch Set 6: Code-Review+2
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Change subject: soc/intel/xeon_sp: Add support for is_ioat_iio_stack_res
......................................................................
soc/intel/xeon_sp: Add support for is_ioat_iio_stack_res
IOAT is the term for the on-chip accelerator technology of
Xeon-SP. In CPX and SPR, IOAT stack is also named as DINO stack.
Different SoC has different check criteria for IOAT stacks,
this patch introduces an util function to abstract these differences
as well as cleaning up the usage of names.
TEST=intel/archercity CRB
Change-Id: I376928ad89b68b294734000678dad6f070d3c97d
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/spr/ioat.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/uncore_acpi.c
5 files changed, 23 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/80578/5
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