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Change subject: soc/intel/alderlake: Correctly set Usb4CmMode
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/80486/comment/7c9da284_beeaab30 :
PS4, Line 682: SOC_INTEL_ALDERLAKE_PCH_M
I thought `Usb4CmMode` existed for `SOC_INTEL_RAPTORLAKE` header alone. Isn't it appropriate to use the Raptor Lake over !SOC_INTEL_ALDERLAKE_PCH_M
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Change subject: soc/intel/xeon_sp: Add support for is_ioat_iio_stack_res
......................................................................
soc/intel/xeon_sp: Add support for is_ioat_iio_stack_res
IOAT is the term for the on-chip accelerator technology of
Xeon-SP. In CPX and SPR, IOAT stack is also named as DINO stack.
Different SoC has different check criteria for IOAT stacks,
this patch introduces an util function to abstract these differences
as well as cleaning up the usage of names.
TEST=intel/archercity CRB
Change-Id: I376928ad89b68b294734000678dad6f070d3c97d
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/spr/ioat.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/uncore_acpi.c
5 files changed, 23 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/80578/4
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Change subject: soc/intel/xeon_sp: Add support for is_ioat_iio_stack_res
......................................................................
soc/intel/xeon_sp: Add support for is_ioat_iio_stack_res
IOAT is the term for the on-chip accelerator technology of
Xeon-SP. In CPX and SPR, IOAT stack is also named as DINO stack.
Different SoC has different check criteria for IOAT stacks,
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TEST=intel/archercity CRB
Change-Id: I376928ad89b68b294734000678dad6f070d3c97d
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/spr/ioat.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/uncore_acpi.c
6 files changed, 24 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/80578/3
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Change subject: soc/intel/xeon_sp: Add support for is_ioat_iio_stack_res
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/xeon_sp/include/soc/util.h:
https://review.coreboot.org/c/coreboot/+/80578/comment/00c52725_2261f4ce :
PS1, Line 28: bool is_ioat_iio_stack_res(const STACK_RES *res);
> Done
Thanks, good catch. The latest changes proves to work as expected.
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Change subject: soc/intel/xeon_sp: Put SRAT util macros into Xeon-SP ACPI header
......................................................................
soc/intel/xeon_sp: Put SRAT util macros into Xeon-SP ACPI header
Macros MAX_ACPI_MEMORY_AFFINITY_COUNT and MAX_SRAT_MEM_ENTRIES_PER_IMC
are ACPI table specific, and could be used across Xeon-SP SoCs.
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ACPI header.
TEST=intel/archercity CRB
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Change-Id: I6c3a84b04a452bc8d4217947a7d12f050c94b56b
---
M src/soc/intel/xeon_sp/include/soc/acpi.h
M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_memmap.h
M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h
4 files changed, 3 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/80629/3
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Change subject: soc/intel/xeon_sp: Use ACPI common flags in SRAT generation
......................................................................
soc/intel/xeon_sp: Use ACPI common flags in SRAT generation
Move the definition of SRAT memory flags (SRAT_ACPI_MEMORY_ENABLED
and SRAT_ACPI_MEMORY_NONVOLATILE) from FSP header to ACPI common
codes.
TEST=intel/archercity CRB
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Change-Id: I6aa5c20c9556fd5d680406518d19a83801b0852c
---
M src/include/acpi/acpi.h
M src/soc/intel/xeon_sp/uncore_acpi.c
M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h
M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h
5 files changed, 7 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/80630/3
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Change subject: drivers/intel/fsp2_0: Add FSP_ALLOCATES_TEMP_RAM
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
> I still think this is not the right approach. […]
Sure, https://review.coreboot.org/c/coreboot/+/80579 is a viable solution and we are okay to move ahead in that direction.
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Change subject: drivers/intel/fsp: Add a workaround for multi socket xeon-sp
......................................................................
Patch Set 3: Code-Review+1
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Change subject: soc/intel/xeon_sp: Put SRAT util macros into Xeon-SP ACPI header
......................................................................
soc/intel/xeon_sp: Put SRAT util macros into Xeon-SP ACPI header
Macros MAX_ACPI_MEMORY_AFFINITY_COUNT and MAX_SRAT_MEM_ENTRIES_PER_IMC
are ACPI table specific, and could be used across Xeon-SP SoCs.
This patch moves their definition from FSP header to Xeon-SP layer
ACPI header.
TEST=intel/archercity CRB
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Change-Id: I6c3a84b04a452bc8d4217947a7d12f050c94b56b
---
M src/soc/intel/xeon_sp/include/soc/acpi.h
M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_memmap.h
2 files changed, 3 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/80629/2
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Change subject: soc/intel/xeon_sp: Add support for is_ioat_iio_stack_res
......................................................................
Patch Set 1: Code-Review+1
(3 comments)
File src/soc/intel/xeon_sp/include/soc/util.h:
https://review.coreboot.org/c/coreboot/+/80578/comment/90e12569_a1859e1a :
PS1, Line 28: bool is_ioat_iio_stack_res(const STACK_RES *res);
> If you add a Kconfig and a static inline the compiler can likely optimize out the SKX code that does […]
Done
File src/soc/intel/xeon_sp/uncore_acpi.c:
https://review.coreboot.org/c/coreboot/+/80578/comment/143f9f53_b9bb1f30 :
PS1, Line 338: #if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP)
> drop
Done
https://review.coreboot.org/c/coreboot/+/80578/comment/8a7d0cbe_69160c37 :
PS1, Line 492: #if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP)
> drop
Done
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