Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80210?usp=email )
Change subject: device: Add a helper function to add a downstream bus
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Patch Set 4:
(1 comment)
Patchset:
PS4:
I am sorry, but this commit touches both ./src/device/ and ./src/soc/intel/xeon_sp/ - should have been split into two separate commits (inconvenient to merge/revert because of this spread)
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Change subject: soc/intel/xeon_sp: Allocate resources above 4G
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Patch Set 13:
(1 comment)
Patchset:
PS13:
> After this commit, now I always have this warning while doing a "make menuconfig" : […]
Unfortunately this has not been resolved yet...
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Change subject: mb/lenovo/m900_tiny: add board
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Patch Set 1:
(2 comments)
File src/mainboard/lenovo/m900_tiny/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/80610/comment/43f88cf6_8d3e2286 :
PS1, Line 9: st
I know it's a common pattern in other skylake boards, but can you move this to a .c file?
https://review.coreboot.org/c/coreboot/+/80610/comment/aeb96a7e_353ccc2f :
PS1, Line 17: static const struct pad_config gpio_table[] = {
Same
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Change subject: mainboard/qemu-riscv: Add PCI support
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Patch Set 1:
(1 comment)
File src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h:
https://review.coreboot.org/c/coreboot/+/80378/comment/703e2a04_c053e7d9 :
PS1, Line 15: #define QEMU_VIRT_PCIE_HIGH_MMIO_BASE 0x300000000ULL
this is correct for rv32, but not for rv64, the base depends on the selected amount of memory.
I think this would only work with memory size set to 10GB
#define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
/* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
#define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
also in virt_machine_init()
virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size;
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Change subject: Don't build a separate romstage by default on most x86 targets
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Patch Set 55:
(1 comment)
File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/63419/comment/df4c6c2a_3366215e :
PS55, Line 248: default y
> > Could you separate the patch that removes the default here? Then I can redefine that value inside […]
Thanks
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Change subject: cpu/x86/(sipi|smm): Pass on CR3 from ramstage
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Patch Set 5:
(1 comment)
File src/cpu/x86/mp_init.c:
https://review.coreboot.org/c/coreboot/+/80335/comment/d4e1156e_441451f5 :
PS4, Line 366: sp->cr3 = read_cr3();
> True, page tables can be used for other purposes, such as NX. […]
Done
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Hello Benjamin Doron, Jérémy Compostella, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80335?usp=email
to look at the new patch set (#5).
The following approvals got outdated and were removed:
Code-Review+2 by Benjamin Doron, Code-Review+2 by Patrick Rudolph, Verified+1 by build bot (Jenkins)
Change subject: cpu/x86/(sipi|smm): Pass on CR3 from ramstage
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cpu/x86/(sipi|smm): Pass on CR3 from ramstage
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I1250ea6f63c65228178ee66e06d988dadfcc2a37
---
M src/cpu/x86/mp_init.c
M src/cpu/x86/sipi_vector.S
M src/cpu/x86/smm/smm_stub.S
M src/include/cpu/x86/smm.h
4 files changed, 12 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/80335/5
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Change subject: cpu/x86/Kconfig: Mark 64bit support as stable
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Change subject: cpu/x86: Link page tables in stage if possible
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Change subject: soc/amd/noncar: Increase bootblock size
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