Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80577?usp=email )
Change subject: include/device/azalia.h: Add enum for misc field
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Maybe we should unify the enums in `azalia.h` and `azalia_device.h`?
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Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80609?usp=email )
Change subject: mb/lenovo/m920q: add board
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/lenovo/m920q/Kconfig:
https://review.coreboot.org/c/coreboot/+/80609/comment/de0562ac_3e033a15 :
PS3, Line 5: select SOC_INTEL_CANNONLAKE_PCH_H
You probably also need `SOC_INTEL_COMMON_BLOCK_HDA_VERB` here so that HDA verbs are applied.
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Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79952?usp=email )
Change subject: arch/riscv/Makefile.mk: Fix OpenSBI compilation
......................................................................
arch/riscv/Makefile.mk: Fix OpenSBI compilation
1. romstage.S should only be included if we have a separate romstage
2. FW_JUMP and FW_DYNAMIC are opposing options and we only support
FW_DYNAMIC
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: Ic14fa77d2f223664b9faba048b759e03efffcde8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79952
Reviewed-by: Philipp Hug <philipp(a)hug.cx>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/riscv/Makefile.mk
1 file changed, 2 insertions(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Philipp Hug: Looks good to me, approved
Arthur Heymans: Looks good to me, approved
diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk
index bbd3959..1267195 100644
--- a/src/arch/riscv/Makefile.mk
+++ b/src/arch/riscv/Makefile.mk
@@ -96,7 +96,7 @@
################################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)
-romstage-y += romstage.S
+romstage-$(CONFIG_SEPARATE_ROMSTAGE) += romstage.S
# Build the romstage
@@ -163,10 +163,9 @@
AR="$(AR_ramstage)" \
PLATFORM=$(CONFIG_OPENSBI_PLATFORM) \
O="$(OPENSBI_BUILD)" \
- FW_JUMP=y \
+ FW_JUMP=n \
FW_DYNAMIC=y \
FW_PAYLOAD=n \
- FW_PAYLOAD_OFFSET=0 \
FW_TEXT_START=$(CONFIG_OPENSBI_TEXT_START)
$(OPENSBI): $(OPENSBI_TARGET)
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Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80139?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: util/crossgcc/buildgcc: Compile RISC-V GCC with medany
......................................................................
util/crossgcc/buildgcc: Compile RISC-V GCC with medany
currently the HiFive Unmatched mainboard produces the following error:
```
util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/rv64imafdc/lp64d/libgcc.a
(_clzsi2.o): in function `__clzdi2':
util/crossgcc/gcc-13.2.0/libgcc/libgcc2.c:690:(.text+0x1e): relocation
truncated to fit: R_RISCV_HI20 against symbol `__clz_tab' defined in
.rodata section in util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/
rv64imafdc/lp64d/libgcc.a(_clz.o)
```
This is due to the fact that the libgcc.a library is compiled with the
medlow code model but the mainboards are compiled with the medany code
model.
Changing the code model of the GCC libraries to the medany code model
fixes the issue.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: If5f07ce034686dd7fec160ea76838507c0ba7fa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80139
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-by: ron minnich <rminnich(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M util/crossgcc/buildgcc
1 file changed, 6 insertions(+), 1 deletion(-)
Approvals:
Arthur Heymans: Looks good to me, but someone else must approve
ron minnich: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 2919376..26b4b05 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -774,6 +774,11 @@
[ -n "$CXX" ] && $CXX --version | grep clang >/dev/null 2>&1 && \
CLANGCXXFLAGS="-fbracket-depth=1024"
+ # standard code model is medlow but all mainboards are compiled with medany code model
+ if [ "${TARGETARCH}" = "riscv64-elf" ]; then
+ CFLAGS_FOR_TARGET_EXTRA="-mcmodel=medany"
+ fi
+
# GCC does not honor HOSTCFLAGS at all. CFLAGS are used for
# both target and host object files.
# There's a work-around called CFLAGS_FOR_BUILD and CFLAGS_FOR_TARGET
@@ -783,7 +788,7 @@
# using C++.
# shellcheck disable=SC2086
CC="$(hostcc target)" CXX="$(hostcxx target)" \
- CFLAGS_FOR_TARGET="-O2 -Dinhibit_libc" \
+ CFLAGS_FOR_TARGET="${CFLAGS_FOR_TARGET_EXTRA} -O2 -Dinhibit_libc" \
CFLAGS="$HOSTCFLAGS $CLANGFLAGS" \
CFLAGS_FOR_BUILD="$HOSTCFLAGS $CLANGFLAGS" \
CXXFLAGS="$HOSTCFLAGS $CLANGCXXFLAGS" \
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Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80547?usp=email )
Change subject: soc/intel/xeon_sp/spr: Don't leak memory
......................................................................
soc/intel/xeon_sp/spr: Don't leak memory
Only call fill_pds() once to prevent leaking memory. Previously it was
called for every active stack on every socket.
Only call dump_pds() once to prevent spamming the console with the same
information.
Drop the return value since it's always returning success.
Change-Id: Ifa9609e9da086dc9731556014ea9b320b270d776
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80547
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu(a)intel.com>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/xeon_sp/include/soc/numa.h
M src/soc/intel/xeon_sp/spr/numa.c
M src/soc/intel/xeon_sp/uncore.c
3 files changed, 10 insertions(+), 10 deletions(-)
Approvals:
Arthur Heymans: Looks good to me, approved
Shuo Liu: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
diff --git a/src/soc/intel/xeon_sp/include/soc/numa.h b/src/soc/intel/xeon_sp/include/soc/numa.h
index 6aaf172..aba3f09 100644
--- a/src/soc/intel/xeon_sp/include/soc/numa.h
+++ b/src/soc/intel/xeon_sp/include/soc/numa.h
@@ -54,7 +54,7 @@
extern struct proximity_domains pds;
void dump_pds(void);
-enum cb_err fill_pds(void);
+void fill_pds(void);
/*
* Return the total size of memory regions in generic initiator affinity
diff --git a/src/soc/intel/xeon_sp/spr/numa.c b/src/soc/intel/xeon_sp/spr/numa.c
index 169f4f8..23f52c6 100644
--- a/src/soc/intel/xeon_sp/spr/numa.c
+++ b/src/soc/intel/xeon_sp/spr/numa.c
@@ -25,7 +25,7 @@
}
}
-enum cb_err fill_pds(void)
+void fill_pds(void)
{
uint8_t num_sockets = soc_get_num_cpus();
uint8_t num_cxlnodes = get_cxl_node_count();
@@ -72,7 +72,7 @@
/* If there are no CXL nodes, we are done */
if (num_cxlnodes == 0)
- return CB_SUCCESS;
+ return;
/* There are CXL nodes, fill in generic initiator domain after the processors pds */
uint8_t skt_id, cxl_id;
@@ -98,8 +98,6 @@
}
}
}
-
- return CB_SUCCESS;
}
/*
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index de2d175..96855ed 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -329,11 +329,13 @@
int index = 0;
if (CONFIG(SOC_INTEL_HAS_CXL)) {
- /* Construct NUMA data structure. This is needed for CXL. */
- if (fill_pds() != CB_SUCCESS)
- pds.num_pds = 0;
-
- dump_pds();
+ static bool once;
+ if (!once) {
+ /* Construct NUMA data structure. This is needed for CXL. */
+ fill_pds();
+ dump_pds();
+ once = true;
+ }
}
/* Read standard PCI resources. */
--
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Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80546?usp=email )
Change subject: soc/intel/xeon_sp/uncore: Don't print uninitialized memory
......................................................................
soc/intel/xeon_sp/uncore: Don't print uninitialized memory
The struct map_entry has two zero'd entries due to the ifdef
being used. Do not read those entries and do not print those
entries.
Fixes a NULL string being printed along as the vendor and device
ID of the PCI device.
Change-Id: Id87ced76af552c0d064538f8140d1b78724fb833
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80546
Reviewed-by: Shuo Liu <shuo.liu(a)intel.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 8 insertions(+), 0 deletions(-)
Approvals:
Arthur Heymans: Looks good to me, approved
Shuo Liu: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index ddc6e82..de2d175 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -72,6 +72,11 @@
uint64_t value;
uint64_t mask;
+ if (!entry->reg) {
+ *result = 0;
+ return;
+ }
+
/* All registers are on a 1MiB granularity. */
mask = ((1ULL << entry->mask_bits) - 1);
mask = ~mask;
@@ -103,6 +108,9 @@
{
int i;
for (i = 0; i < NUM_MAP_ENTRIES; i++) {
+ if (!memory_map[i].description)
+ continue;
+
printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
memory_map[i].description, values[i]);
}
--
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