Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/80625?usp=email )
Change subject: arch/x86/bootblock.ld: Align the base of bootblock downwards
......................................................................
Abandoned
--
To view, visit https://review.coreboot.org/c/coreboot/+/80625?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I78c6ba6e250ded3f04b12cd0c20b18cb653a1506
Gerrit-Change-Number: 80625
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: abandon
Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/80624?usp=email )
Change subject: mb/fb/fbg1701: Move VBOOT key location
......................................................................
Abandoned
--
To view, visit https://review.coreboot.org/c/coreboot/+/80624?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib37846c0b039d89396839ffa6047b18bcc228e02
Gerrit-Change-Number: 80624
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com>
Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: abandon
Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/80623?usp=email )
Change subject: cpu/x86/smm: Set up page tables in safe SMRAM
......................................................................
Abandoned
--
To view, visit https://review.coreboot.org/c/coreboot/+/80623?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icb3086abd577b9abb9966dd910a264a873ace4ed
Gerrit-Change-Number: 80623
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: abandon
Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/80582?usp=email )
Change subject: cpu/x86/(sipi|smm): Pass on CR3 from ramstage
......................................................................
Abandoned
--
To view, visit https://review.coreboot.org/c/coreboot/+/80582?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1250ea6f63c65228178ee66e06d988dadfcc2a37
Gerrit-Change-Number: 80582
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: abandon
Attention is currently required from: Jérémy Compostella.
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80628?usp=email )
Change subject: cpu/x86/Kconfig: Mark 64bit support as stable
......................................................................
cpu/x86/Kconfig: Mark 64bit support as stable
With SMM holding page tables itself, we can consider SMM support stable
and safe enough for general use.
Also update the respective documentation.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Ifcf0a1a5097a2d7c064bb709ec0b09ebee13a47d
---
M Documentation/arch/x86/index.md
M src/arch/x86/Kconfig
2 files changed, 4 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/80628/1
diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md
index c7115b4..ea0ec61 100644
--- a/Documentation/arch/x86/index.md
+++ b/Documentation/arch/x86/index.md
@@ -5,9 +5,7 @@
* [x86 PAE support](pae.md)
## State of x86_64 support
-At the moment there's only experimental x86_64 support.
-The `emulation/qemu-i440fx` and `emulation/qemu-q35` boards do support
-*ARCH_RAMSTAGE_X86_64* , *ARCH_POSTCAR_X86_64* and *ARCH_ROMSTAGE_X86_64*.
+A few SOCs now support 64bit mode. Search for HAVE_EXP_X86_64_SUPPORT in Kconfig.
In order to add support for x86_64 the following assumptions were made:
* The CPU supports long mode
@@ -15,7 +13,6 @@
* All code that is to be run must be below 4GiB in physical memory
* The high dword of pointers is always zero
* The reference implementation is qemu
-* The CPU supports 1GiB hugepages
* x86 payloads are loaded below 4GiB in physical memory and are jumped
to in *protected mode*
@@ -54,7 +51,6 @@
1. Fine grained page tables for SMM:
* Must not have execute and write permissions for the same page.
* Must allow only that TSEG pages can be marked executable
- * Must reside in SMRAM
2. Support 64bit PCI BARs above 4GiB
3. Place and run code above 4GiB
@@ -62,13 +58,10 @@
* Fix compilation errors
* Test how well CAR works with x86_64 and paging
* Improve mode switches
-* Test libgfxinit / VGA Option ROMs / FSP
-## Known bugs on real hardware
+## Known problems on real hardware
-According to Intel x86_64 mode hasn't been validated in CAR environments.
-Until now it could be verified on various Intel platforms and no issues have
-been found.
+Running VGA rom directly fails. Yabel works fine though.
## Known bugs on KVM enabled qemu
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 1697ee7..c264130 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -74,7 +74,7 @@
to provide a config file for Jenkins to build-test the 64-bit option.
config USE_EXP_X86_64_SUPPORT
- bool "[EXPERIMENTAL] Run coreboot in long (64-bit) mode"
+ bool "Run coreboot in long (64-bit) mode"
depends on HAVE_EXP_X86_64_SUPPORT
select ARCH_ALL_STAGES_X86_64
help
--
To view, visit https://review.coreboot.org/c/coreboot/+/80628?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifcf0a1a5097a2d7c064bb709ec0b09ebee13a47d
Gerrit-Change-Number: 80628
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-MessageType: newchange
Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier.
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80627?usp=email )
Change subject: cpu/x86: Link page tables in stage if possible
......................................................................
cpu/x86: Link page tables in stage if possible
When switching back and forward from 32 to 64, for example to call a
32bit FSP or toe call the payload, a new page tables in the respective
stage will be linked.
The advantages of this approach are:
- No need to determine a good place for page tables in cbfs that does
not overlap.
- Works with non memory mapped flash (however all coreboot targets
currently do support this)
- If later stages can use their own page tables which fits better with
the vboot RO/RW flow
A disadvantage is that it increases the stage size. This could be
improved upon by used 1G pages and generating the pages at runtime.
TESTED on google/vilbox and qemu/q35: boots to payload
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562
---
M src/arch/x86/Kconfig
M src/cpu/intel/car/core2/cache_as_ram.S
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/x86/64bit/Makefile.mk
M src/cpu/x86/64bit/entry64.inc
M src/cpu/x86/64bit/mode_switch.S
M src/cpu/x86/64bit/mode_switch2.S
M src/cpu/x86/64bit/pt.S
M src/mainboard/emulation/qemu-i440fx/Kconfig
M src/mainboard/emulation/qemu-q35/Kconfig
M src/soc/amd/common/block/cpu/noncar/pre_c.S
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
13 files changed, 25 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/80627/1
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 0c11653..1697ee7 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -84,9 +84,13 @@
is an experimental option: do not enable unless one wants to test it
and has the means to recover a system when coreboot fails to boot.
+config PAGE_TABLES_IN_CBFS
+ bool
+ default n
+
config ARCH_X86_64_PGTBL_LOC
hex "x86_64 page table location in CBFS"
- depends on ARCH_BOOTBLOCK_X86_64
+ depends on ARCH_BOOTBLOCK_X86_64 && PAGE_TABLES_IN_CBFS
default 0xfffe9000
help
The position where to place pagetables. Needs to be known at
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index 2e4d9c8..227ddf4 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -163,7 +163,7 @@
subl $4, %esp
#if ENV_X86_64
- setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+ setup_longmode $PM4LE
movd %mm2, %rdi
shlq $32, %rdi
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 578bf03..9485cd4 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -214,7 +214,7 @@
andl $0xfffffff0, %esp
#if ENV_X86_64
- setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+ setup_longmode $PM4LE
movd %mm2, %rdi
shlq $32, %rdi
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 32fddd6..1cb422d 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -363,7 +363,7 @@
subl $4, %esp
#if ENV_X86_64
- setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+ setup_longmode $PM4LE
movd %mm2, %rdi
shlq $32, %rdi /* BIST */
diff --git a/src/cpu/x86/64bit/Makefile.mk b/src/cpu/x86/64bit/Makefile.mk
index 680ab2d..69561bc 100644
--- a/src/cpu/x86/64bit/Makefile.mk
+++ b/src/cpu/x86/64bit/Makefile.mk
@@ -2,6 +2,7 @@
all_x86-y += mode_switch.S
all_x86-y += mode_switch2.S
+all_x86-y += pt.S
ifeq ($(CONFIG_USE_1G_PAGETABLES),y)
PAGETABLE_SRC := pt1G.S
@@ -15,7 +16,7 @@
$(OBJCOPY_ramstage) -Obinary -j .rodata $@.tmp $@
rm $@.tmp
-cbfs-files-y += pagetables
+cbfs-files-$(CONFIG_PAGE_TABLES_IN_CBFS) += pagetables
pagetables-file := $(objcbfs)/pt
pagetables-type := raw
pagetables-compression := none
diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc
index 878f310..52da603 100644
--- a/src/cpu/x86/64bit/entry64.inc
+++ b/src/cpu/x86/64bit/entry64.inc
@@ -11,9 +11,11 @@
#if ENV_X86_64
.code32
+#if CONFIG(PAGE_TABLES_IN_CBFS)
#if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0
#error pagetables must be 4KiB aligned!
#endif
+#endif
#include <cpu/x86/msr.h>
#if defined(__RAMSTAGE__)
diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S
index 01fe003..9555cef 100644
--- a/src/cpu/x86/64bit/mode_switch.S
+++ b/src/cpu/x86/64bit/mode_switch.S
@@ -44,7 +44,7 @@
movl %eax, %ebx
/* Preserves ebx */
- setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+ setup_longmode $PM4LE
/* Place return value in rax */
movl %ebx, %eax
diff --git a/src/cpu/x86/64bit/mode_switch2.S b/src/cpu/x86/64bit/mode_switch2.S
index 1807d2e..18c6425 100644
--- a/src/cpu/x86/64bit/mode_switch2.S
+++ b/src/cpu/x86/64bit/mode_switch2.S
@@ -21,7 +21,7 @@
mov %esp, %ebp
/* Enter long mode, preserves ebx */
- setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+ setup_longmode $PM4LE
/* Align stack */
movabs $0xfffffffffffffff0, %rax
diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S
index b105528..67e4b1b 100644
--- a/src/cpu/x86/64bit/pt.S
+++ b/src/cpu/x86/64bit/pt.S
@@ -18,7 +18,7 @@
#define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a))
.global PM4LE
-.align 32
+.align 4096
PM4LE:
.quad _GEN_DIR(PDPE_table)
diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig
index cec6f97..dcc3dd6 100644
--- a/src/mainboard/emulation/qemu-i440fx/Kconfig
+++ b/src/mainboard/emulation/qemu-i440fx/Kconfig
@@ -30,6 +30,10 @@
select GBB_FLAG_DISABLE_FWMP
if ARCH_BOOTBLOCK_X86_64
+config PAGE_TABLES_IN_CBFS
+ bool
+ default y
+
# Need to install page tables in DRAM as the virtual MMU has problems translating paging
# request when the page table resides in emulated ROM. This causes undefined behaviour
# when handling data requests, as well as fetching and decoding instructions
diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig
index d68a546..fd2c89f 100644
--- a/src/mainboard/emulation/qemu-q35/Kconfig
+++ b/src/mainboard/emulation/qemu-q35/Kconfig
@@ -32,6 +32,10 @@
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab-16M.fmd" if VBOOT_SLOTS_RW_AB
if ARCH_BOOTBLOCK_X86_64
+config PAGE_TABLES_IN_CBFS
+ bool
+ default y
+
# Need to install page tables in DRAM as the virtual MMU has problems translating paging
# request when the page table resides in emulated ROM. This causes undefined behaviour
# when handling data requests, as well as fetching and decoding instructions
diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S
index bb2203b..0e0be52 100644
--- a/src/soc/amd/common/block/cpu/noncar/pre_c.S
+++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S
@@ -28,7 +28,7 @@
post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
#if ENV_X86_64
- setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+ setup_longmode $PM4LE
#endif
/* Clear .bss section */
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index c22e7d9..ba98f1b 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -280,7 +280,7 @@
andl $0xfffffff0, %esp
#if ENV_X86_64
- setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+ setup_longmode $PM4LE
movd %mm2, %rdi
shlq $32, %rdi
--
To view, visit https://review.coreboot.org/c/coreboot/+/80627?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562
Gerrit-Change-Number: 80627
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newchange
Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier.
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80626?usp=email )
Change subject: soc/amd/noncar: Increase bootblock size
......................................................................
soc/amd/noncar: Increase bootblock size
When linking in page tables or romstage code, more place is needed.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I23f176d63d3c303b13331a77ad5ac6c7a19073d3
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/genoa_poc/Kconfig
M src/soc/amd/glinda/Kconfig
M src/soc/amd/mendocino/Kconfig
M src/soc/amd/phoenix/Kconfig
M src/soc/amd/picasso/Kconfig
6 files changed, 18 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/80626/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 2ebf6bc..abeaece 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -175,7 +175,7 @@
config C_ENV_BOOTBLOCK_SIZE
hex
- default 0x10000
+ default 0x20000
help
Sets the size of the bootblock stage that should be loaded in DRAM.
This variable controls the DRAM allocation size in linker script
@@ -183,13 +183,13 @@
config ROMSTAGE_ADDR
hex
- default 0x2040000
+ default 0x2050000
help
Sets the address in DRAM where romstage should be loaded.
config ROMSTAGE_SIZE
hex
- default 0x80000
+ default 0x70000
help
Sets the size of DRAM allocation for romstage in linker script.
diff --git a/src/soc/amd/genoa_poc/Kconfig b/src/soc/amd/genoa_poc/Kconfig
index 2460323..05590f5 100644
--- a/src/soc/amd/genoa_poc/Kconfig
+++ b/src/soc/amd/genoa_poc/Kconfig
@@ -98,7 +98,7 @@
config C_ENV_BOOTBLOCK_SIZE
hex
- default 0x10000
+ default 0x20000
help
Sets the size of the bootblock stage that should be loaded in DRAM.
This variable controls the DRAM allocation size in linker script
@@ -106,13 +106,13 @@
config ROMSTAGE_ADDR
hex
- default 0x7040000
+ default 0x7050000
help
Sets the address in DRAM where romstage should be loaded.
config ROMSTAGE_SIZE
hex
- default 0x80000
+ default 0x70000
help
Sets the size of DRAM allocation for romstage in linker script.
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index a042ea2..61d1f0c 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -160,7 +160,7 @@
config C_ENV_BOOTBLOCK_SIZE
hex
- default 0x10000
+ default 0x20000
help
Sets the size of the bootblock stage that should be loaded in DRAM.
This variable controls the DRAM allocation size in linker script
@@ -168,13 +168,13 @@
config ROMSTAGE_ADDR
hex
- default 0x2040000
+ default 0x2050000
help
Sets the address in DRAM where romstage should be loaded.
config ROMSTAGE_SIZE
hex
- default 0x80000
+ default 0x70000
help
Sets the size of DRAM allocation for romstage in linker script.
diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig
index f6305ee..ee6c968 100644
--- a/src/soc/amd/mendocino/Kconfig
+++ b/src/soc/amd/mendocino/Kconfig
@@ -195,7 +195,7 @@
config C_ENV_BOOTBLOCK_SIZE
hex
- default 0x10000
+ default 0x20000
help
Sets the size of the bootblock stage that should be loaded in DRAM.
This variable controls the DRAM allocation size in linker script
@@ -203,13 +203,13 @@
config ROMSTAGE_ADDR
hex
- default 0x2040000
+ default 0x2050000
help
Sets the address in DRAM where romstage should be loaded.
config ROMSTAGE_SIZE
hex
- default 0x80000
+ default 0x70000
help
Sets the size of DRAM allocation for romstage in linker script.
diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index 9d45b76..d3dfc6a 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -176,7 +176,7 @@
config C_ENV_BOOTBLOCK_SIZE
hex
- default 0x10000
+ default 0x20000
help
Sets the size of the bootblock stage that should be loaded in DRAM.
This variable controls the DRAM allocation size in linker script
@@ -184,13 +184,13 @@
config ROMSTAGE_ADDR
hex
- default 0x2060000
+ default 0x2070000
help
Sets the address in DRAM where romstage should be loaded.
config ROMSTAGE_SIZE
hex
- default 0x80000
+ default 0x70000
help
Sets the size of DRAM allocation for romstage in linker script.
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 0bb6f40..864643f 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -165,7 +165,7 @@
config C_ENV_BOOTBLOCK_SIZE
hex
- default 0x10000
+ default 0x20000
help
Sets the size of the bootblock stage that should be loaded in DRAM.
This variable controls the DRAM allocation size in linker script
@@ -173,13 +173,13 @@
config ROMSTAGE_ADDR
hex
- default 0x2040000
+ default 0x2050000
help
Sets the address in DRAM where romstage should be loaded.
config ROMSTAGE_SIZE
hex
- default 0x80000
+ default 0x70000
help
Sets the size of DRAM allocation for romstage in linker script.
--
To view, visit https://review.coreboot.org/c/coreboot/+/80626?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I23f176d63d3c303b13331a77ad5ac6c7a19073d3
Gerrit-Change-Number: 80626
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newchange
Attention is currently required from: Jérémy Compostella.
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80625?usp=email )
Change subject: arch/x86/bootblock.ld: Align the base of bootblock downwards
......................................................................
arch/x86/bootblock.ld: Align the base of bootblock downwards
Instead of using some aritmetics that sometimes works, use the largest
alignment necessary (page tables) and align downwards in the linker
script.
This fixes linking failing when linking in page tables inside the
bootblock.
This can result in a slight increase in bootblock size of at most 4096 -
512 bytes.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I78c6ba6e250ded3f04b12cd0c20b18cb653a1506
---
M src/arch/x86/bootblock.ld
1 file changed, 4 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/80625/1
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
index d59eb27..6547985 100644
--- a/src/arch/x86/bootblock.ld
+++ b/src/arch/x86/bootblock.ld
@@ -17,19 +17,16 @@
. = _ebootblock - CONFIG_C_ENV_BOOTBLOCK_SIZE;
#else
. = BOOTBLOCK_TOP - PROGRAM_SZ;
- . = ALIGN(64);
+ /* Page tables need to be at a 4K boundary so align the bootblock downwards */
+ . = ALIGN(4096);
+ . -= 4096;
#endif
_bootblock = .;
INCLUDE "bootblock/lib/program.ld"
- /*
- * Allocation reserves extra space here. Alignment requirements
- * may cause the total size of a section to change when the start
- * address gets applied.
- */
- PROGRAM_SZ = SIZEOF(.text) + 512;
+ PROGRAM_SZ = SIZEOF(.text);
. = MIN(_ECFW_PTR, MIN(_ID_SECTION, _FIT_POINTER)) - EARLYASM_SZ;
. = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(16);
--
To view, visit https://review.coreboot.org/c/coreboot/+/80625?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I78c6ba6e250ded3f04b12cd0c20b18cb653a1506
Gerrit-Change-Number: 80625
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-MessageType: newchange
Attention is currently required from: Erik van den Bogaert, Frans Hendriks.
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80624?usp=email )
Change subject: mb/fb/fbg1701: Move VBOOT key location
......................................................................
mb/fb/fbg1701: Move VBOOT key location
Move it downwards allows for a larger bootblock, which comes in handy if
romstage or page tables are linked inside the bootblock.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Ib37846c0b039d89396839ffa6047b18bcc228e02
---
M src/mainboard/facebook/fbg1701/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/80624/1
diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig
index 1218102..1ea2ae6 100644
--- a/src/mainboard/facebook/fbg1701/Kconfig
+++ b/src/mainboard/facebook/fbg1701/Kconfig
@@ -90,7 +90,7 @@
config VENDORCODE_ELTAN_VBOOT_KEY_LOCATION
depends on VENDORCODE_ELTAN_VBOOT
hex
- default 0xFFFF9000
+ default 0xFFFEA000
config DRIVERS_INTEL_WIFI
bool
--
To view, visit https://review.coreboot.org/c/coreboot/+/80624?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib37846c0b039d89396839ffa6047b18bcc228e02
Gerrit-Change-Number: 80624
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com>
Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com>
Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-MessageType: newchange