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Change subject: soc/intel/alderlake: Sync UPD Usb4CmMode with Kconfig
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/80486/comment/93dac2ff_ca71d3df :
PS4, Line 682: SOC_INTEL_ALDERLAKE_PCH_M
> > I guess so! […]
Sure, will tidy the next patch after the tag
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Change subject: util: Add hda-decoder
......................................................................
Patch Set 4:
(1 comment)
File util/hda-decoder/go.mod:
https://review.coreboot.org/c/coreboot/+/80470/comment/6ecfc4d3_b12415e2 :
PS4, Line 1: module review.coreboot.org/coreboot.git/util/hda-decoder
> I'm really not into Go, but is it needed to hard-code that here?
Well, we are in the same camp. 😄
AFAIK this is how you do it. This file was generated automatically by `go mod init`. The URL is the usual way of naming modules (unique and can be pulled into other programs easily by downloading from the URL).
`intelp2m` also does the same thing.
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Change subject: soc/intel/xeon-sp: Hook up public FSP bin and headers
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
I've synced our FSP mirror and CB:80615 updates the submodule pointer. Maybe this helps.
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Change subject: mb/google/volteer: Fix S0i3 regression
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Patch Set 1: Code-Review+2
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Change subject: util: Add hda-decoder
......................................................................
Patch Set 4:
(2 comments)
File util/hda-decoder/go.mod:
https://review.coreboot.org/c/coreboot/+/80470/comment/376b11b5_20b0f2d8 :
PS4, Line 1: module review.coreboot.org/coreboot.git/util/hda-decoder
I'm really not into Go, but is it needed to hard-code that here?
File util/hda-decoder/main.go:
https://review.coreboot.org/c/coreboot/+/80470/comment/21f0e608_f2d2f43e :
PS4, Line 13: "review.coreboot.org/coreboot.git/util/hda-decoder/decoder"
Same here
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Change subject: soc/intel/alderlake: Sync UPD Usb4CmMode with Kconfig
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/80486/comment/38cf96d3_cd3ae749 :
PS4, Line 682: SOC_INTEL_ALDERLAKE_PCH_M
> I guess so!
>
> Not guarding it causes a build failure, or do you mean remove ADL-M from coreboot?
I don't mind landing this CL as is bt lets take few action items
1. land this CL as is
2. drop ADL-M
3. Drop this additional #if guarding.
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Change subject: soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SP
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/alderlake: Sync UPD Usb4CmMode with Kconfig
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/80486/comment/097f9b47_82638caf :
PS4, Line 682: SOC_INTEL_ALDERLAKE_PCH_M
> > P, N and S have it […]
I guess so!
Not guarding it causes a build failure, or do you mean remove ADL-M from coreboot?
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Change subject: treewide: Move list.h to commonlib
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Patch Set 9: Code-Review+1
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