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Change subject: mb/lenovo: Add ThinkCentre M920q (Cannon Lake)
......................................................................
mb/lenovo: Add ThinkCentre M920q (Cannon Lake)
It may come with 8th or 9th Gen CPUs.
i5-8500T has been tested here.
Works:
- Serial adapter from daughter board (COM1 connector)
- USB ports front and back
- USB-C port (charging, data)
- HDMI (in Linux and SeaBIOS)
- Ethernet
- SATA
- NVMe
- internal speaker
- TPM2.0
Does not work:
- front audio jacks
- HDMI (in edk2)
Not tested:
- PCIe x8 port
- Display Port
- WiFi slot
Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4
Signed-off-by: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com>
---
A src/mainboard/lenovo/m920q/Kconfig
A src/mainboard/lenovo/m920q/Kconfig.name
A src/mainboard/lenovo/m920q/Makefile.inc
A src/mainboard/lenovo/m920q/acpi/ec.asl
A src/mainboard/lenovo/m920q/acpi/mainboard.asl
A src/mainboard/lenovo/m920q/acpi/superio.asl
A src/mainboard/lenovo/m920q/board.fmd
A src/mainboard/lenovo/m920q/board_info.txt
A src/mainboard/lenovo/m920q/bootblock.c
A src/mainboard/lenovo/m920q/cmos.default
A src/mainboard/lenovo/m920q/cmos.layout
A src/mainboard/lenovo/m920q/data.vbt
A src/mainboard/lenovo/m920q/devicetree.cb
A src/mainboard/lenovo/m920q/dsdt.asl
A src/mainboard/lenovo/m920q/gma-mainboard.ads
A src/mainboard/lenovo/m920q/gpio.c
A src/mainboard/lenovo/m920q/hda_verb.c
A src/mainboard/lenovo/m920q/include/mainboard/gpio.h
A src/mainboard/lenovo/m920q/ramstage.c
A src/mainboard/lenovo/m920q/romstage.c
20 files changed, 1,413 insertions(+), 0 deletions(-)
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Change subject: Documentation: Release notes for the 24.02 release
......................................................................
Documentation: Release notes for the 24.02 release
These will be updated and finalized after the release to capture any
final changes, remove "upcoming release", and finalize all stats.
Change-Id: Idc224c43f2459faabf91a9ef282bb9eaeba42240
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
---
M Documentation/releases/coreboot-24.02-relnotes.md
1 file changed, 212 insertions(+), 29 deletions(-)
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Change subject: treewide: Change I2C/SMBUS master/slave to controller/target
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
File Documentation/tutorial/part3.md:
https://review.coreboot.org/c/coreboot/+/77098/comment/da6fd333_f31f9b57 :
PS4, Line 260: slave
That too?
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Change subject: Documentation: Release notes for the 24.02 release
......................................................................
Patch Set 2:
(1 comment)
File Documentation/releases/coreboot-24.02-relnotes.md:
https://review.coreboot.org/c/coreboot/+/80617/comment/4b51fa64_001a1a24 :
PS2, Line 120: * Updated devicetree files for modern Intel platforms to use chipset.cb
> `xeon_sp` uses the coreboot allocator now. […]
Added. You'll see it in the next update.
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Change subject: treewide: Change I2C/SMBUS master/slave to controller/target
......................................................................
Patch Set 4: Code-Review+1
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Change subject: soc/intel/common/block/fast_spi: probe for 2nd flash component
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80608/comment/eb9fd434_1e1ac213 :
PS2, Line 10: used
> Was the driver replaced?
Clarified on the old driver.
https://review.coreboot.org/c/coreboot/+/80608/comment/ff7cde3d_8dbe7847 :
PS2, Line 12: Some boards
> Please give one example.
Example given
File src/soc/intel/common/block/fast_spi/fast_spi_flash.c:
https://review.coreboot.org/c/coreboot/+/80608/comment/aa446ff1_dd0077fb :
PS2, Line 58: hord
> HORD?
Changed to HORD and added some more information
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Hello Michał Żygowski, Paul Menzel, build bot (Jenkins),
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Change subject: soc/intel/common/block/fast_spi: probe for 2nd flash component
......................................................................
soc/intel/common/block/fast_spi: probe for 2nd flash component
Fast SPI code assumes only one SPI flash is present. The SPI flash
driver for older southbridges is able to detect multichip. See the
spi_is_multichip() in src/southbridge/intel/common/spi.c.
Some boards (e.g. Lenovo ThinkCentre M920 Tiny) still come with two
chips populated instead of one. With this change, both chips are probed,
and the correct total size is calculated. Otherwise, only the first one
was probed, which resulted in an error such as:
SF size 0x1000000 does not correspond to CONFIG_ROM_SIZE 0x1800000!!
Change-Id: I8d7449f9e1470dc234fe5ba5217d3ce4c142b49c
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---
M src/soc/intel/common/block/fast_spi/fast_spi_def.h
M src/soc/intel/common/block/fast_spi/fast_spi_flash.c
2 files changed, 31 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/80608/3
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Change subject: Documentation: Release notes for the 24.02 release
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File Documentation/releases/coreboot-24.02-relnotes.md:
https://review.coreboot.org/c/coreboot/+/80617/comment/eaba3f5e_357116e3 :
PS2, Line 120: * Updated devicetree files for modern Intel platforms to use chipset.cb
`xeon_sp` uses the coreboot allocator now.
(not sure about the exact state now and if that's worth its own
section. the goal was that the kernel doesn't have to (re-)allocate
anything.)
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Change subject: Documentation: Release notes for the 24.02 release
......................................................................
Documentation: Release notes for the 24.02 release
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Change-Id: Idc224c43f2459faabf91a9ef282bb9eaeba42240
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M Documentation/releases/coreboot-24.02-relnotes.md
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Change subject: drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80579/comment/521ae5ac_d2e4d7ab :
PS4, Line 12: FspStackSize and the bottom is the bottom of CAR.
I'm still a bit puzzled. Is "FSP heap" here referring to the
total heap, i.e. RC heap plus the one set with StackBase+Size?
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Gerrit-Comment-Date: Mon, 19 Feb 2024 20:33:55 +0000
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