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Change subject: mb/google/brya/var/xol: Add support memory parts
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Change subject: mb/google/brya/var/xol: Update memory configuration
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Change subject: mb/google/brya/var/xol: Update thermal policy
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80410/comment/c502ef9f_5c319bff :
PS2, Line 9: Update initial DTT policy for Xol.
> What is the source for the initial policy?
Done
https://review.coreboot.org/c/coreboot/+/80410/comment/5cb495ec_69d67af8 :
PS2, Line 11: - Critical CPU temparature: 99
: - TCC offset: 94
> Could be two commits: […]
This is for initial thermal policy and to be ready the first firmware for Xol.
How about merge this commit. Spliting to 2 commits for same file will cause delay of the our first firmware.
It'll be updated in future after fine-tune work during development stage then I'll make commits for each category.
https://review.coreboot.org/c/coreboot/+/80410/comment/38449097_0baf27c8 :
PS2, Line 12: - TCC offset: 94
> What is the default?
Done
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Change subject: mb/google/brya/var/xol: Update thermal policy
......................................................................
mb/google/brya/var/xol: Update thermal policy
Update initial DTT policy and TCC setting for Xol. The setting values
are from internal power team.
- Critical CPU temparature: 105 -> 99
- TCC offset: 90 -> 94
BUG=b:323989520
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
Change-Id: I546b313a1e6af16029309174a5bed2d1e4aa4d11
Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/xol/overridetree.cb
1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/80410/3
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Change subject: mb/google/brya/var/xol: Update memory configuration
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80326/comment/69fd0d2c_34bc4f30 :
PS5, Line 12: - K3KL6L60GM-MGCT
: - K3KL8L80CM-MGCT
> Please add the vendor name. Maybe also do this in a separate commit, if possible.
Done.
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Change subject: mb/google/brya/var/xol: Add support memory parts
......................................................................
mb/google/brya/var/xol: Add support memory parts
Add support memory parts for Xol.
- Samsung K3KL6L60GM-MGCT
- Samsung K3KL8L80CM-MGCT
BUG=b:319506033
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
Proto board can boot to ChromeOS.
Change-Id: Ic6a36e40f0f93109f296c5cc67a368ace81bd217
Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com>
---
D src/mainboard/google/brya/variants/xol/memory/Makefile.inc
A src/mainboard/google/brya/variants/xol/memory/Makefile.mk
M src/mainboard/google/brya/variants/xol/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/xol/memory/mem_parts_used.txt
4 files changed, 17 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/80637/1
diff --git a/src/mainboard/google/brya/variants/xol/memory/Makefile.inc b/src/mainboard/google/brya/variants/xol/memory/Makefile.inc
deleted file mode 100644
index eace2e4..0000000
--- a/src/mainboard/google/brya/variants/xol/memory/Makefile.inc
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-# This is an auto-generated file. Do not edit!!
-# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
-
-SPD_SOURCES = placeholder
diff --git a/src/mainboard/google/brya/variants/xol/memory/Makefile.mk b/src/mainboard/google/brya/variants/xol/memory/Makefile.mk
new file mode 100644
index 0000000..f07fb67
--- /dev/null
+++ b/src/mainboard/google/brya/variants/xol/memory/Makefile.mk
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/xol/memory/ src/mainboard/google/brya/variants/xol/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 0(0b0000) Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 1(0b0001) Parts = K3KL8L80CM-MGCT
diff --git a/src/mainboard/google/brya/variants/xol/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/xol/memory/dram_id.generated.txt
index fa24790..e36906a 100644
--- a/src/mainboard/google/brya/variants/xol/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/xol/memory/dram_id.generated.txt
@@ -1 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/xol/memory/ src/mainboard/google/brya/variants/xol/memory/mem_parts_used.txt
+
DRAM Part Name ID to assign
+K3KL6L60GM-MGCT 0 (0000)
+K3KL8L80CM-MGCT 1 (0001)
diff --git a/src/mainboard/google/brya/variants/xol/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/xol/memory/mem_parts_used.txt
index 9621137..b5773cc 100644
--- a/src/mainboard/google/brya/variants/xol/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/xol/memory/mem_parts_used.txt
@@ -9,3 +9,5 @@
# See util/spd_tools/README.md for more details and instructions.
# Part Name
+K3KL6L60GM-MGCT
+K3KL8L80CM-MGCT
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Change subject: mb/google/brya/var/xol: Update memory configuration
......................................................................
mb/google/brya/var/xol: Update memory configuration
Update memory configuration following proto schematics.
BUG=b:319506033
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
Proto board can boot to ChromeOS.
Change-Id: I59aabe0870317092f59701bdf88b53bf9731377a
Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/xol/Makefile.mk
A src/mainboard/google/brya/variants/xol/memory.c
2 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/80326/7
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Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80579?usp=email )
Change subject: drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug
......................................................................
Patch Set 4:
(1 comment)
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/80579/comment/e68dc194_c6063a0d :
PS4, Line 229: This code implicitly assumes that the top of FSP heap is FspStackBase +
suggest to update here as well for clarity.
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