Attention is currently required from: Cliff Huang, Felix Held, Lance Zhao, Patrick Rudolph, Tim Wawrzynczak.
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80804?usp=email )
Change subject: acpi/acpigen_pci_root_resource_producer: zero-pad ranges
......................................................................
Patch Set 1: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/80804?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Iea45094a3988d57f8640a98fd7214d33ed1d7ccb
Gerrit-Change-Number: 80804
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com>
Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Comment-Date: Thu, 29 Feb 2024 17:17:45 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment
Attention is currently required from: Maximilian Brune, Philipp Hug, ron minnich.
Hello Philipp Hug, build bot (Jenkins), ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79954?usp=email
to look at the new patch set (#8).
The following approvals got outdated and were removed:
Code-Review+2 by ron minnich, Verified+1 by build bot (Jenkins)
The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: mb/sifive: Add Hifive Unmatched mainboard
......................................................................
mb/sifive: Add Hifive Unmatched mainboard
working:
Linux v6.3.5
poweroff via Linux PMIC driver
UART console output
SPI -> SDCARD
I2C -> PMIC
16 GB LPDDR4 memory
VSC8541XMV-02 (gigabit ethernet PHY)
PCIe x16 Slot
M.2 NVMe Slot
MSEL: only '1100' has been tested
untested:
M.2 WiFi/Bluetooth Slot
tested bootflow:
ZSBL -> coreboot --FDT-> Linuxboot -> uroot --kexec-> ubuntu
defconfig used:
CONFIG_VENDOR_SIFIVE=y
CONFIG_BOARD_SIFIVE_HIFIVE_UNMATCHED=y
CONFIG_PAYLOAD_NONE=n
CONFIG_PAYLOAD_ELF=y
CONFIG_PAYLOAD_FILE="[path-to-linux]/arch/riscv/boot/Image"
CONFIG_PAYLOAD_IS_FLAT_BINARY=y
CONFIG_PAYLOAD_OPTIONS="-l 0x82000000 -e 0x82000000"
CONFIG_COMPRESSED_PAYLOAD_LZMA=y
uroot kexec command:
kexec -d --cmdline "console=ttySIF0 root=/dev/mmcblk0p1 debug" \
--initrd /mnt/boot/initrd.img-6.5.0-9-generic \
/mnt/boot/vmlinuz-6.5.0-9-generic
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: Ife0afdce89d5a1a1b936c30c8027f1bc191b8c53
---
A src/mainboard/sifive/hifive-unmatched/Kconfig
A src/mainboard/sifive/hifive-unmatched/Kconfig.name
A src/mainboard/sifive/hifive-unmatched/Makefile.inc
A src/mainboard/sifive/hifive-unmatched/board_info.txt
A src/mainboard/sifive/hifive-unmatched/cbfs_spi.c
A src/mainboard/sifive/hifive-unmatched/devicetree.cb
A src/mainboard/sifive/hifive-unmatched/fixup_fdt.c
A src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi
A src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts
A src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts
A src/mainboard/sifive/hifive-unmatched/mainboard.c
A src/mainboard/sifive/hifive-unmatched/romstage.c
12 files changed, 1,189 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/79954/8
--
To view, visit https://review.coreboot.org/c/coreboot/+/79954?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ife0afdce89d5a1a1b936c30c8027f1bc191b8c53
Gerrit-Change-Number: 79954
Gerrit-PatchSet: 8
Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>
Gerrit-CC: Jan Samek <jan.samek(a)siemens.com>
Gerrit-Attention: Philipp Hug <philipp(a)hug.cx>
Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Attention: ron minnich <rminnich(a)gmail.com>
Gerrit-MessageType: newpatchset
Attention is currently required from: Jeremy Soller, Paul Menzel.
Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80756?usp=email )
Change subject: mb/system76/adl,rpl: Add FSP default timeout for PCIe 3.0 RPs
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80756/comment/4b3c79f0_0d75999b :
PS1, Line 7: Add timeouts for PCIe 3.0 RPs
:
> Maybe: […]
Leaving as-is and explaining it's the FSP default value in the body.
https://review.coreboot.org/c/coreboot/+/80756/comment/ad1e4a65_c8ac9af0 :
PS1, Line 14: Tested on lemp12 with Samsung 980 PRO and 990 PRO drives.
> What drive firmware versions?
Done
https://review.coreboot.org/c/coreboot/+/80756/comment/8cdc788a_08f426f6 :
PS1, Line 15:
> Is there a default time-out value? Why 50 ms and not another value?
Changed to use FSP default of 56ms.
File src/mainboard/system76/adl/variants/darp8/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/80756/comment/8ef4a3c2_f64b5c0a :
PS1, Line 155: .pcie_rp_detect_timeout_ms = 50,
> Is there a default timeout?
Done
--
To view, visit https://review.coreboot.org/c/coreboot/+/80756?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I4f44fc429c52e407b7566d6bb6dd31b2cf85c48d
Gerrit-Change-Number: 80756
Gerrit-PatchSet: 3
Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com>
Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Comment-Date: Thu, 29 Feb 2024 17:03:16 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: comment
Attention is currently required from: Jeremy Soller, Tim Crawford.
Hello Jeremy Soller, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80756?usp=email
to look at the new patch set (#3).
Change subject: mb/system76/adl,rpl: Add FSP default timeout for PCIe 3.0 RPs
......................................................................
mb/system76/adl,rpl: Add FSP default timeout for PCIe 3.0 RPs
The FSP may fail to detect PCIe 4.0 devices in PCIe 3.0 slots on S3
resume. This issue has only been experienced on lemp12, and only with
Samsung drives, but implies it could happen on other systems or with
other drives as well. Use the FSP default value of 56ms.
Tested on lemp12 with Samsung 980 PRO (FW: 3B2QGXA7, 5B2QGXA7) and 990
PRO (FW: 4B2QJXD7) drives.
Change-Id: I4f44fc429c52e407b7566d6bb6dd31b2cf85c48d
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
M src/mainboard/system76/adl/variants/darp8/overridetree.cb
M src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb
M src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb
M src/mainboard/system76/adl/variants/lemp11/overridetree.cb
M src/mainboard/system76/rpl/variants/gaze18/overridetree.cb
M src/mainboard/system76/rpl/variants/lemp12/overridetree.cb
6 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/80756/3
--
To view, visit https://review.coreboot.org/c/coreboot/+/80756?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I4f44fc429c52e407b7566d6bb6dd31b2cf85c48d
Gerrit-Change-Number: 80756
Gerrit-PatchSet: 3
Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com>
Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com>
Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com>
Gerrit-MessageType: newpatchset
Attention is currently required from: Maximilian Brune, Philipp Hug, ron minnich.
Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79954?usp=email )
Change subject: mb/sifive: Add Hifive Unmatched mainboard
......................................................................
Set Ready For Review
--
To view, visit https://review.coreboot.org/c/coreboot/+/79954?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ife0afdce89d5a1a1b936c30c8027f1bc191b8c53
Gerrit-Change-Number: 79954
Gerrit-PatchSet: 7
Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>
Gerrit-CC: Jan Samek <jan.samek(a)siemens.com>
Gerrit-Attention: Philipp Hug <philipp(a)hug.cx>
Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Attention: ron minnich <rminnich(a)gmail.com>
Gerrit-Comment-Date: Thu, 29 Feb 2024 16:58:02 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Attention is currently required from: Paul Menzel, Paz Zcharya, Subrata Banik.
Gwendal Grignou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80738?usp=email )
Change subject: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection
......................................................................
Patch Set 7:
(1 comment)
File src/vendorcode/google/chromeos/tpm_factory_config.c:
https://review.coreboot.org/c/coreboot/+/80738/comment/a4768747_d67239da :
PS7, Line 104: return strncmp(vpd_get_feature_device_info(), "CAI", 3) == 0;
> | Regular Chromebook device […]
As discussed in the meeting, in chromeos_device_branded_plus_soft() we can completely ignore GSC information and go by reading the VPD. Until protobuf decoding is added to coreboot, the device will be a regular chromebook when vpd_get_feature_device_info() is empty or indicates the feature_level is 0.
--
To view, visit https://review.coreboot.org/c/coreboot/+/80738?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I9bb1e868764738333977bd8c990bea4253c9d37b
Gerrit-Change-Number: 80738
Gerrit-PatchSet: 7
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com>
Gerrit-Reviewer: Shelley Chen <shchen(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Paz Zcharya <pazz(a)google.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Comment-Date: Thu, 29 Feb 2024 16:54:09 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>
Comment-In-Reply-To: Gwendal Grignou <gwendal(a)chromium.org>
Gerrit-MessageType: comment
Attention is currently required from: Jeremy Soller, Tim Crawford.
Hello Jeremy Soller, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80756?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/system76/adl,rpl: Add FSP default timeout for PCIe 3.0 RPs
......................................................................
mb/system76/adl,rpl: Add FSP default timeout for PCIe 3.0 RPs
The FSP may fail to detect PCIe 4.0 devices in PCIe 3.0 slots on S3
resume. This issue has only been experienced on lemp12, and only with
Samsung drives, but implies it could happen on other systems or with
other drives as well. Use the FSP default value of 56ms.
Tested on lemp12 with Samsung 980 PRO and 990 PRO drives.
Change-Id: I4f44fc429c52e407b7566d6bb6dd31b2cf85c48d
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
M src/mainboard/system76/adl/variants/darp8/overridetree.cb
M src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb
M src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb
M src/mainboard/system76/adl/variants/lemp11/overridetree.cb
M src/mainboard/system76/rpl/variants/gaze18/overridetree.cb
M src/mainboard/system76/rpl/variants/lemp12/overridetree.cb
6 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/80756/2
--
To view, visit https://review.coreboot.org/c/coreboot/+/80756?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I4f44fc429c52e407b7566d6bb6dd31b2cf85c48d
Gerrit-Change-Number: 80756
Gerrit-PatchSet: 2
Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com>
Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com>
Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com>
Gerrit-MessageType: newpatchset
Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80791?usp=email )
Change subject: mb/system76/rpl: Add TCSS ACPI for all boards
......................................................................
mb/system76/rpl: Add TCSS ACPI for all boards
Fixes ACPI errors about missing methods:
ACPI BIOS Error (bug): Could not resolve symbol [_SB.PCI0.TDM0], AE_NOT_FOUND (20230628/dswload2-162)
ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220)
ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x0010)
ACPI BIOS Error (bug): Could not resolve symbol [_SB.PCI0.TRP0], AE_NOT_FOUND (20230628/dswload2-162)
ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220)
Tested on lemp12: ACPI errors in dmesg are gone.
Change-Id: I9b79cb04f57a27af2a6c8f3118e573f7ac0041e5
Signed-off-by: Dan Campbell <dan(a)compiledworks.com>
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
M src/mainboard/system76/rpl/dsdt.asl
1 file changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/80791/1
diff --git a/src/mainboard/system76/rpl/dsdt.asl b/src/mainboard/system76/rpl/dsdt.asl
index addb4df..cbf9e6a 100644
--- a/src/mainboard/system76/rpl/dsdt.asl
+++ b/src/mainboard/system76/rpl/dsdt.asl
@@ -19,9 +19,7 @@
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/alderlake/acpi/southbridge.asl>
- #if CONFIG(BOARD_SYSTEM76_ORYP11)
- #include <soc/intel/alderlake/acpi/tcss.asl>
- #endif // CONFIG(BOARD_SYSTEM76_ORYP11)
+ #include <soc/intel/alderlake/acpi/tcss.asl>
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
--
To view, visit https://review.coreboot.org/c/coreboot/+/80791?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I9b79cb04f57a27af2a6c8f3118e573f7ac0041e5
Gerrit-Change-Number: 80791
Gerrit-PatchSet: 1
Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com>
Gerrit-MessageType: newchange
Attention is currently required from: Arthur Heymans, Philipp Hug.
Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80746?usp=email )
Change subject: mb/emulation/qemu-riscv: Change to -bios option
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> what is the reason for using both -bios and -pflash? […]
If I only use -pflash QEMU will start OpenSBI and skip coreboot alltogether.
If I only use -bios than QEMU will place coreboot in DRAM, but will not give us a flash as backing storage (which we need to fetch CBFS stuff from).
If I use -pflash and `-bios none` than QEMU will jump to Flash with XIP. That is also something we could support, but it is a bit inconvenient and not done in coreboot yet for RISC-V and ARM I think.
If I use both -pflash and -bios coreboot.rom then QEMU will place coreboot in DRAM (like on current AMD platforms I think) and give us a backing storage to pull CBFS stages and stuff from.
It is a bit confusing.
--
To view, visit https://review.coreboot.org/c/coreboot/+/80746?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d
Gerrit-Change-Number: 80746
Gerrit-PatchSet: 5
Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>
Gerrit-Attention: Philipp Hug <philipp(a)hug.cx>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Comment-Date: Thu, 29 Feb 2024 16:32:21 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Philipp Hug <philipp(a)hug.cx>
Gerrit-MessageType: comment