coreboot-gerrit February 2024

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[M] Change in coreboot[main]: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection
by Gwendal Grignou (Code Review) 29 Feb '24

29 Feb '24

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[M] Change in coreboot[main]: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection
by Gwendal Grignou (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Paul Menzel, Paz Zcharya, Subrata Banik. Gwendal Grignou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80738?usp=email ) Change subject: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection ...................................................................... Patch Set 7: (2 comments) File src/vendorcode/google/chromeos/tpm_factory_config.c: https://review.coreboot.org/c/coreboot/+/80738/comment/d206f026_13b60297 : PS7, Line 74: * requirement. > > I assume the design doc is at `go/cros-tiering-dd`. […] Requested comment access to the doc. If there are corner cases, then line 97 is incorrect. https://review.coreboot.org/c/coreboot/+/80738/comment/9d828eaa_a179bf86 : PS7, Line 104: return strncmp(vpd_get_feature_device_info(), "CAI", 3) == 0; > > The previous comment states "all older devices will have legacy config", so we don't need the non- […] | Regular Chromebook device Assuming this change applies to devices built after 2/23 (as documented in comment for line 97), all hardware compliant chromebook will have the proper bit set in GSC, so the VPD logic is not needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/80738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bb1e868764738333977bd8c990bea4253c9d37b Gerrit-Change-Number: 80738 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 29 Feb 2024 15:36:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS
by Nico Huber (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Felix Held, Jason Nien, Martin Roth, Matt DeVillier, Paul Menzel. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80711?usp=email ) Change subject: mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80711/comment/d9ed3ec0_1fd6995a : PS1, Line 9: is needed > Windows could work with drivers signed by an entity (vs individual), MS is more strict with drivers […] For ACPI, hiding only means hiding from the UI anyway, cf. definition of `ACPI_STATUS_DEVICE_HIDDEN_ON`. -- To view, visit https://review.coreboot.org/c/coreboot/+/80711?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia700aa4ccd478bc734db012e1419e566a5dcf493 Gerrit-Change-Number: 80711 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Feb 2024 15:22:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/emulation/qemu-riscv: Change to -bios option
by ron minnich (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80746?usp=email ) Change subject: mb/emulation/qemu-riscv: Change to -bios option ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Further tests today with the sidecore command show it works. rminnich@t510:~$ sidecore 192.168.0.240 date Thu Jan 1 00:03:33 UTC 1970 long story short, this shows an ssh connection, NFS 3 mounts, bind mounts, etc. etc. working. This port is solid. -- To view, visit https://review.coreboot.org/c/coreboot/+/80746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Gerrit-Change-Number: 80746 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 29 Feb 2024 15:14:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS
by Matt DeVillier (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Felix Held, Jason Nien, Martin Roth, Paul Menzel. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80711?usp=email ) Change subject: mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80711/comment/1719054c_2d44a5de : PS1, Line 9: is needed > Oh, I didn’t know. […] Windows could work with drivers signed by an entity (vs individual), MS is more strict with drivers for security functions. Linux just doesn't have driver/userspace support for the device, but if it did I'd expect it to ignore the ACPI status like it does for most other things, so the hidden setting wouldn't affect it. -- To view, visit https://review.coreboot.org/c/coreboot/+/80711?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia700aa4ccd478bc734db012e1419e566a5dcf493 Gerrit-Change-Number: 80711 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Feb 2024 15:13:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in libgfxinit[main]: gma: Update transcoder setup for TGL
by Nico Huber (Code Review) 29 Feb '24

29 Feb '24

Nico Huber has submitted this change. ( https://review.coreboot.org/c/libgfxinit/+/67493?usp=email ) Change subject: gma: Update transcoder setup for TGL ...................................................................... gma: Update transcoder setup for TGL Tiger Lake requires configuration (but not enablement) of the transcoder during the modeset sequence itself, so this patch adds a new Config option to accommodate that and refactors the transcoder setup into two new procedures. There should be no functional differences for other generations. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Change-Id: I4d7e2a24c54fcd9994f44bb0b10924dce48068e5 Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/67493 Tested-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-transcoder.adb M common/hw-gfx-gma-transcoder.ads 3 files changed, 132 insertions(+), 32 deletions(-) Approvals: Nico Huber: Verified; Looks good to me, approved diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 0bc7d80..dd6c2f8 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -196,7 +196,7 @@ Has_Tertiary_Pipe : <ilkbool> := Ivybridge_On; Disable_Trickle_Feed : <genbool> := not Gen_Haswell; Pipe_Enabled_Workaround : <hswbool> := CPU_Broadwell; - Has_EDP_Transcoder : <genbool> := Haswell_On; + Has_EDP_Transcoder : <genbool> := Haswell_On and not Tigerlake_On; Use_PDW_For_EDP_Scaling : <hswbool> := CPU_Haswell; Has_Pipe_DDI_Func : <genbool> := Haswell_On; Has_Trans_Clk_Sel : <genbool> := Haswell_On; @@ -212,6 +212,9 @@ Has_GMCH_VGACNTRL : <genbool> := Gen_G45; Has_GMCH_PFIT_CONTROL : <genbool> := Gen_G45; + ----------- Transcoder ------- + Need_Early_Transcoder_Setup : <genbool> := Tigerlake_On; + --------- Panel power: ------- Has_PP_Write_Protection : <genbool> := Up_To_Ironlake; Has_PP_Port_Select : <genbool> := Up_To_Ironlake; @@ -263,6 +266,8 @@ -- might be disabled by x4 eDP: Has_DDI_E : <hswsklbool> := Has_DDI_D; + Has_TGL_DDI_Select : <genbool> := Tigerlake_On; + Has_DDI_Buffer_Trans : <genbool> := Haswell_On and not Has_DDI_PHYs; Has_Low_Voltage_Swing : <genbool> := Broxton_On; Has_Iboost_Config : <genbool> := Skylake_On; diff --git a/common/hw-gfx-gma-transcoder.adb b/common/hw-gfx-gma-transcoder.adb index e74d769..9e85b75 100644 --- a/common/hw-gfx-gma-transcoder.adb +++ b/common/hw-gfx-gma-transcoder.adb @@ -15,6 +15,7 @@ with HW.Debug; with GNAT.Source_Info; +with HW.GFX.GMA.Config_Helpers; with HW.GFX.GMA.DP_Info; package body HW.GFX.GMA.Transcoder is @@ -38,6 +39,7 @@ ---------------------------------------------------------------------------- TRANS_CLK_SEL_PORT_NONE : constant := 0 * 2 ** 29; + TRANS_CLK_SEL_MASK : constant := 16#f000_0000#; type TRANS_CLK_SEL_PORT_Array is array (Digital_Port) of Word32; @@ -48,6 +50,19 @@ DIGI_D => 4 * 2 ** 29, DIGI_E => 5 * 2 ** 29); + function TGL_TRANS_CLK_SEL_PORT (Port : TGL_Digital_Port) return Word32 is + (case Port is + when DIGI_A => 1 * 2 ** 28, + when DIGI_B => 2 * 2 ** 28, + when DIGI_C => 3 * 2 ** 28, + when DDI_TC1 => 4 * 2 ** 28, + when DDI_TC2 => 5 * 2 ** 28, + when DDI_TC3 => 6 * 2 ** 28, + when DDI_TC4 => 7 * 2 ** 28, + when DDI_TC5 => 8 * 2 ** 28, + when DDI_TC6 => 9 * 2 ** 28, + when others => 0); + TRANS_CONF_ENABLE : constant := 1 * 2 ** 31; TRANS_CONF_ENABLED_STATUS : constant := 1 * 2 ** 30; TRANS_CONF_ENABLE_DITHER : constant := 1 * 2 ** 4; @@ -85,6 +100,21 @@ DIGI_D => 3 * 2 ** 28, DIGI_E => 4 * 2 ** 28); + function TGL_DDI_FUNC_CTL_DDI_SELECT (Port : TGL_Digital_Port) + return Word32 + is + (case Port is + when DIGI_A => 1 * 2 ** 27, + when DIGI_B => 2 * 2 ** 27, + when DIGI_C => 3 * 2 ** 27, + when DDI_TC1 => 4 * 2 ** 27, + when DDI_TC2 => 5 * 2 ** 27, + when DDI_TC3 => 6 * 2 ** 27, + when DDI_TC4 => 7 * 2 ** 27, + when DDI_TC5 => 8 * 2 ** 27, + when DDI_TC6 => 9 * 2 ** 27, + when others => 0); + type DDI_Mode_Array is array (Display_Type) of Word32; DDI_FUNC_CTL_MODE_SELECT : constant DDI_Mode_Array := (VGA => DDI_FUNC_CTL_MODE_SELECT_FDI, @@ -204,6 +234,7 @@ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); if Config.Has_Trans_Clk_Sel and then + not Config.Need_Early_Transcoder_Setup and then Trans.CLK_SEL /= Registers.Invalid_Register and then Port_Cfg.Port in Digital_Port then @@ -228,6 +259,69 @@ ---------------------------------------------------------------------------- + procedure Enable_Pipe_Clock (Pipe : Pipe_Index; Port_Cfg : Port_Config) + is + use type HW.GFX.GMA.Registers.Registers_Invalid_Index; + + Trans : Transcoder_Regs renames + Transcoders (Get_Idx (Pipe, Port_Cfg.Port)); + begin + if Config.Need_Early_Transcoder_Setup and then + Trans.CLK_SEL /= Registers.Invalid_Register and then + Port_Cfg.Port in TGL_Digital_Port + then + Registers.Unset_And_Set_Mask + (Register => Trans.CLK_SEL, + Mask_Unset => TRANS_CLK_SEL_MASK, + Mask_Set => TGL_TRANS_CLK_SEL_PORT (Port_Cfg.Port)); + end if; + end Enable_Pipe_Clock; + + ---------------------------------------------------------------------------- + + procedure Configure (Pipe : Pipe_Index; Port_Cfg : Port_Config; Scale : Boolean) + is + Trans : Transcoder_Regs renames + Transcoders (Get_Idx (Pipe, Port_Cfg.Port)); + Lane_Count : constant DP_Lane_Count := + (if Port_Cfg.Is_FDI then Port_Cfg.FDI.Lane_Count else Port_Cfg.DP.Lane_Count); + EDP_Select : constant Word32 := + (if Config.Has_TGL_DDI_Select + then 0 + else + (if Pipe = Primary and + (not Config.Use_PDW_For_EDP_Scaling or else not Scale) + then + DDI_FUNC_CTL_EDP_SELECT_ALWAYS_ON + else + DDI_FUNC_CTL_EDP_SELECT (Pipe))); + DDI_Select : constant Word32 := + (if Config.Has_TGL_DDI_Select and Port_Cfg.Port in TGL_Digital_Port then + TGL_DDI_FUNC_CTL_DDI_SELECT (Port_Cfg.Port) + else + (if Port_Cfg.Port in Digital_Port + then + DDI_FUNC_CTL_DDI_SELECT (Port_Cfg.Port) + else 0)); + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + if Config.Has_Pipe_DDI_Func then + if Is_Digital_Port (Port_Cfg.Port) then + Registers.Write + (Register => Trans.DDI_FUNC_CTL, + Value => DDI_Select or + DDI_FUNC_CTL_MODE_SELECT (Port_Cfg.Display) or + DDI_FUNC_CTL_BPC (Port_Cfg.Mode.BPC) or + DDI_FUNC_CTL_VSYNC (Port_Cfg.Mode.V_Sync_Active_High) or + DDI_FUNC_CTL_HSYNC (Port_Cfg.Mode.H_Sync_Active_High) or + EDP_Select or + DDI_FUNC_CTL_PORT_WIDTH (Lane_Count)); + end if; + end if; + end Configure; + + ---------------------------------------------------------------------------- + procedure On (Pipe : Pipe_Index; Port_Cfg : Port_Config; @@ -236,27 +330,16 @@ is Trans : Transcoder_Regs renames Transcoders (Get_Idx (Pipe, Port_Cfg.Port)); - Lane_Count : constant DP_Lane_Count := - (if Port_Cfg.Is_FDI then Port_Cfg.FDI.Lane_Count else Port_Cfg.DP.Lane_Count); - EDP_Select : constant Word32 := - (if Pipe = Primary and - (not Config.Use_PDW_For_EDP_Scaling or else not Scale) - then - DDI_FUNC_CTL_EDP_SELECT_ALWAYS_ON - else - DDI_FUNC_CTL_EDP_SELECT (Pipe)); begin - if Config.Has_Pipe_DDI_Func and Port_Cfg.Port in Digital_Port then - Registers.Write + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + if not Config.Need_Early_Transcoder_Setup then + Configure (Pipe, Port_Cfg, Scale); + end if; + + if Config.Has_Pipe_DDI_Func and Is_Digital_Port (Port_Cfg.Port) then + Registers.Set_Mask (Register => Trans.DDI_FUNC_CTL, - Value => DDI_FUNC_CTL_ENABLE or - DDI_FUNC_CTL_DDI_SELECT (Port_Cfg.Port) or - DDI_FUNC_CTL_MODE_SELECT (Port_Cfg.Display) or - DDI_FUNC_CTL_BPC (Port_Cfg.Mode.BPC) or - DDI_FUNC_CTL_VSYNC (Port_Cfg.Mode.V_Sync_Active_High) or - DDI_FUNC_CTL_HSYNC (Port_Cfg.Mode.H_Sync_Active_High) or - EDP_Select or - DDI_FUNC_CTL_PORT_WIDTH (Lane_Count)); + Mask => DDI_FUNC_CTL_ENABLE); end if; Registers.Write @@ -360,15 +443,20 @@ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); if Config.Has_Per_Pipe_SRD then - for P in Transcoder_Index loop - Registers.Is_Set_Mask (SRD (P).CTL, SRD_CTL_ENABLE, Enabled); - if Enabled then - Registers.Unset_Mask (SRD (P).CTL, SRD_CTL_ENABLE); - Registers.Wait_Unset_Mask (SRD (P).STATUS, SRD_STATUS_STATE_MASK); + declare + First_Transcoder : constant Transcoder_Index := + (if Config.Has_EDP_Transcoder then Trans_EDP else Trans_A); + begin + for P in Transcoder_Index range First_Transcoder .. Transcoder_Index'Last loop + Registers.Is_Set_Mask (SRD (P).CTL, SRD_CTL_ENABLE, Enabled); + if Enabled then + Registers.Unset_Mask (SRD (P).CTL, SRD_CTL_ENABLE); + Registers.Wait_Unset_Mask (SRD (P).STATUS, SRD_STATUS_STATE_MASK); - pragma Debug (Debug.Put_Line ("Disabled PSR.")); - end if; - end loop; + pragma Debug (Debug.Put_Line ("Disabled PSR.")); + end if; + end loop; + end; else Registers.Is_Set_Mask (Registers.SRD_CTL, SRD_CTL_ENABLE, Enabled); if Enabled then diff --git a/common/hw-gfx-gma-transcoder.ads b/common/hw-gfx-gma-transcoder.ads index 4a24996..c89ee57 100644 --- a/common/hw-gfx-gma-transcoder.ads +++ b/common/hw-gfx-gma-transcoder.ads @@ -18,6 +18,8 @@ private package HW.GFX.GMA.Transcoder is + procedure Enable_Pipe_Clock (Pipe : Pipe_Index; Port_Cfg : Port_Config); + procedure Configure (Pipe : Pipe_Index; Port_Cfg : Port_Config; Scale : Boolean); procedure Setup (Pipe : Pipe_Index; Port_Cfg : Port_Config); procedure On (Pipe : Pipe_Index; @@ -52,6 +54,7 @@ DDI_FUNC_CTL : Registers.Registers_Index; MSA_MISC : Registers.Registers_Index; CLK_SEL : Registers.Registers_Invalid_Index; + PIPE_ARB_CTL : Registers.Registers_Invalid_Index; end record; type Transcoder_Array is array (Transcoder_Index) of Transcoder_Regs; @@ -100,7 +103,8 @@ LINK_N1 => Registers.PIPE_EDP_LINK_N1, DDI_FUNC_CTL => Registers.PIPE_EDP_DDI_FUNC_CTL, MSA_MISC => Registers.PIPE_EDP_MSA_MISC, - CLK_SEL => Registers.Invalid_Register), + CLK_SEL => Registers.Invalid_Register, + PIPE_ARB_CTL => Registers.Invalid_Register), Trans_A => (HTOTAL => Registers.HTOTAL_A, HBLANK => Registers.HBLANK_A, @@ -115,7 +119,8 @@ LINK_N1 => PIPE_LINK_N1 (0), DDI_FUNC_CTL => Registers.PIPEA_DDI_FUNC_CTL, MSA_MISC => Registers.PIPEA_MSA_MISC, - CLK_SEL => Registers.TRANSA_CLK_SEL), + CLK_SEL => Registers.TRANSA_CLK_SEL, + PIPE_ARB_CTL => Registers.PIPEA_ARB_CTL), Trans_B => (HTOTAL => Registers.HTOTAL_B, HBLANK => Registers.HBLANK_B, @@ -130,7 +135,8 @@ LINK_N1 => PIPE_LINK_N1 (1), DDI_FUNC_CTL => Registers.PIPEB_DDI_FUNC_CTL, MSA_MISC => Registers.PIPEB_MSA_MISC, - CLK_SEL => Registers.TRANSB_CLK_SEL), + CLK_SEL => Registers.TRANSB_CLK_SEL, + PIPE_ARB_CTL => Registers.PIPEB_ARB_CTL), Trans_C => (HTOTAL => Registers.HTOTAL_C, HBLANK => Registers.HBLANK_C, @@ -145,6 +151,7 @@ LINK_N1 => Registers.PIPEC_LINK_N1, DDI_FUNC_CTL => Registers.PIPEC_DDI_FUNC_CTL, MSA_MISC => Registers.PIPEC_MSA_MISC, - CLK_SEL => Registers.TRANSC_CLK_SEL)); + CLK_SEL => Registers.TRANSC_CLK_SEL, + PIPE_ARB_CTL => Registers.PIPEC_ARB_CTL)); end HW.GFX.GMA.Transcoder; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/67493?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: main Gerrit-Change-Id: I4d7e2a24c54fcd9994f44bb0b10924dce48068e5 Gerrit-Change-Number: 67493 Gerrit-PatchSet: 28 Gerrit-Owner: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in libgfxinit[main]: gma: Update DP training with new fields
by Nico Huber (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Angel Pons, Arthur Heymans, Jérémy Compostella, Nick Vaccaro, Shelley Chen, Tarun Tuli, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/67490?usp=email ) Change subject: gma: Update DP training with new fields ...................................................................... Patch Set 23: (1 comment) File common/ironlake/hw-gfx-gma-pch-dp.ads: https://review.coreboot.org/c/libgfxinit/+/67490/comment/8f08cedc_485567cf : PS19, Line 26: Reason => "Needed for a common interface" > Could you please also help with "Verified+1" vote? Sorry, I didn't have time to look into this the last week. AIUI the other comment thread, we agreed back then that this change isn't necessary. And CB:67499 should be re-worked instead. Generally, this patch train needs somebody to take over the uploader role and get all the commits on a single branch again (i.e. no "indirect relation" in the Relation chain on the top right). Right now, I can only merge the very next change (CB:67493) but then the next needs an update. I have a TGL board on the table now and could take the uploader role for TGL patches if nobody else will. -- To view, visit https://review.coreboot.org/c/libgfxinit/+/67490?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: main Gerrit-Change-Id: I3f7f8a93408a74cfa29d1493a48c88ce73dc690c Gerrit-Change-Number: 67490 Gerrit-PatchSet: 23 Gerrit-Owner: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 29 Feb 2024 15:04:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Add Dinesh Gehlot as ADL SOC and BRYA MB maintainer
by Kapil Porwal (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Dinesh Gehlot, Paul Menzel. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80778?usp=email ) Change subject: MAINTAINERS: Add Dinesh Gehlot as ADL SOC and BRYA MB maintainer ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80778?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ad9dbe3bd073f3c43878beec201491b87694fc3 Gerrit-Change-Number: 80778 Gerrit-PatchSet: 3 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Thu, 29 Feb 2024 14:31:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/mrc_cache: Deselect MRC_CACHE_USING_MRC_VERSION by default
by Kapil Porwal (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Arthur Heymans, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jincheng Li, Ronak Kanabar, Shuo Liu, Tarun. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80693?usp=email ) Change subject: drivers/mrc_cache: Deselect MRC_CACHE_USING_MRC_VERSION by default ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84fdcfbf3c833a7ccb259a1a1d4be0bcfe291dc3 Gerrit-Change-Number: 80693 Gerrit-PatchSet: 6 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Feb 2024 14:29:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/intel/gma: Allow SPARK function with side effects
by Thomas Heijligen (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Nico Huber. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80616?usp=email ) Change subject: drivers/intel/gma: Allow SPARK function with side effects ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80616?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1eb879f57437587dc11d879fcc4042a70d384786 Gerrit-Change-Number: 80616 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 29 Feb 2024 14:19:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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