coreboot-gerrit February 2024

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[XL] Change in coreboot[main]: soc/sifive/fu740: Add FU740 SOC
by Maximilian Brune (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Philipp Hug, ron minnich. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76689?usp=email ) Change subject: soc/sifive/fu740: Add FU740 SOC ...................................................................... Patch Set 10: (1 comment) This change is ready for review. File src/soc/sifive/fu740/sdram.c: https://review.coreboot.org/c/coreboot/+/76689/comment/2210178a_0734ba2f : PS10, Line 161: static void ux00ddr_phy_fixup(void *ahbregaddr) this has never actually been tested by me, but it is hard to test. -- To view, visit https://review.coreboot.org/c/coreboot/+/76689?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a8fe02ef0adcb939aa65377a35874715c5ee58a Gerrit-Change-Number: 76689 Gerrit-PatchSet: 10 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-CC: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Feb 2024 16:21:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS
by Felix Held (Code Review) 29 Feb '24

29 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80711?usp=email ) Change subject: mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS ...................................................................... mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS No Windows driver exists or is needed, so hide to prevent an unknown device from being listed in Windows Device Manager. Same change was made for frostflow variant previously. TEST=build/boot Win11 on skyrim, verify unknown device for the fingerprint reader no longer present. Change-Id: Ia700aa4ccd478bc734db012e1419e566a5dcf493 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80711 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/skyrim/variants/skyrim/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Nico Huber: Looks good to me, but someone else must approve Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb index eb16120..be498fc 100644 --- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb @@ -238,7 +238,7 @@ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_4)" register "enable_delay_ms" = "3" - device generic 0 alias fpmcu on + device generic 0 alias fpmcu hidden probe FP FP_PRESENT end end -- To view, visit https://review.coreboot.org/c/coreboot/+/80711?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia700aa4ccd478bc734db012e1419e566a5dcf493 Gerrit-Change-Number: 80711 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS
by Felix Held (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Jason Nien, Martin Roth, Matt DeVillier, Nico Huber, Paul Menzel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80711?usp=email ) Change subject: mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80711?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia700aa4ccd478bc734db012e1419e566a5dcf493 Gerrit-Change-Number: 80711 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 29 Feb 2024 16:17:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/emulation/qemu-riscv: Change to -bios option
by Philipp Hug (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Arthur Heymans, Maximilian Brune. Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80746?usp=email ) Change subject: mb/emulation/qemu-riscv: Change to -bios option ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: what is the reason for using both -bios and -pflash? qemu supports booting from flash only: see https://github.com/qemu/qemu/blob/master/hw/riscv/virt.c#L1305 -- To view, visit https://review.coreboot.org/c/coreboot/+/80746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Gerrit-Change-Number: 80746 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 29 Feb 2024 16:12:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/
by Felix Held (Code Review) 29 Feb '24

29 Feb '24

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80464?usp=email ) Change subject: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/ ...................................................................... Patch Set 4: (2 comments) File src/acpi/acpigen_pci_root_resource_producer.c: https://review.coreboot.org/c/coreboot/+/80464/comment/81a1f1c3_50672b0d : PS3, Line 14: IO > pad by two spaces to align with MMIO since the values after that have a substantially different length, i'm not sure if that's worth it https://review.coreboot.org/c/coreboot/+/80464/comment/17444622_64dfd8c2 : PS3, Line 57: -% > i'll push a follow-up to address those CB:80804 -- To view, visit https://review.coreboot.org/c/coreboot/+/80464?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99 Gerrit-Change-Number: 80464 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 29 Feb 2024 16:02:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: acpi/acpigen_pci_root_resource_producer: zero-pad ranges
by Felix Held (Code Review) 29 Feb '24

29 Feb '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80804?usp=email ) Change subject: acpi/acpigen_pci_root_resource_producer: zero-pad ranges ...................................................................... acpi/acpigen_pci_root_resource_producer: zero-pad ranges Print bus number, IO and MMIO ranges as fixed length zero-padded hexadecimal numbers. The bus numbers are 1 byte long, the IO range values are 2 bytes long and the MMIO range values can be up to 8 bytes long, so use '%02x', '%04llx' and '%016llx' in the corresponding parts of the format string. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: Iea45094a3988d57f8640a98fd7214d33ed1d7ccb --- M src/acpi/acpigen_pci_root_resource_producer.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/80804/1 diff --git a/src/acpi/acpigen_pci_root_resource_producer.c b/src/acpi/acpigen_pci_root_resource_producer.c index c9efe0e..78e1a89 100644 --- a/src/acpi/acpigen_pci_root_resource_producer.c +++ b/src/acpi/acpigen_pci_root_resource_producer.c @@ -11,7 +11,7 @@ static void write_ssdt_domain_io_producer_range_helper(const char *domain_name, resource_t base, resource_t limit) { - printk(BIOS_DEBUG, "%s _CRS: adding IO range [%llx-%llx]\n", domain_name, base, limit); + printk(BIOS_DEBUG, "%s _CRS: adding IO range [%04llx-%04llx]\n", domain_name, base, limit); acpigen_resource_producer_io(base, limit); } @@ -38,7 +38,7 @@ static void write_ssdt_domain_mmio_producer_range(const char *domain_name, resource_t base, resource_t limit) { - printk(BIOS_DEBUG, "%s _CRS: adding MMIO range [%llx-%llx]\n", + printk(BIOS_DEBUG, "%s _CRS: adding MMIO range [%016llx-%016llx]\n", domain_name, base, limit); acpigen_resource_producer_mmio(base, limit, MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_NON_CACHE); @@ -54,7 +54,7 @@ acpigen_write_resourcetemplate_header(); /* PCI bus number range in domain */ - printk(BIOS_DEBUG, "%s _CRS: adding busses [%x-%x] in segment group %x\n", + printk(BIOS_DEBUG, "%s _CRS: adding busses [%02x-%02x] in segment group %x\n", acpi_device_name(domain), domain->downstream->secondary, domain->downstream->max_subordinate, domain->downstream->segment_group); acpigen_resource_producer_bus_number(domain->downstream->secondary, -- To view, visit https://review.coreboot.org/c/coreboot/+/80804?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea45094a3988d57f8640a98fd7214d33ed1d7ccb Gerrit-Change-Number: 80804 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS
by Matt DeVillier (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Felix Held, Jason Nien, Martin Roth, Nico Huber, Paul Menzel. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80711?usp=email ) Change subject: mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80711/comment/5025f830_693678df : PS1, Line 9: is needed > For ACPI, hiding only means hiding from the UI anyway, […] correct, all this does is clean up Device Manager for Windows users, so they don't panic about an unknown device listed there -- To view, visit https://review.coreboot.org/c/coreboot/+/80711?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia700aa4ccd478bc734db012e1419e566a5dcf493 Gerrit-Change-Number: 80711 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Feb 2024 15:42:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/
by Felix Held (Code Review) 29 Feb '24

29 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80464?usp=email ) Change subject: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/ ...................................................................... soc/amd: move common pci_domain_fill_ssdt implementation to acpi/ Even though it has an 'amd_' prefix, the amd_pci_domain_fill_ssdt implementation doesn't contain any AMD-specific code and can also be used by other SoCs. So factor it out, move the implementation to src/acpi/acpigen_pci_root_resource_producer.c, and rename it to pci_domain_fill_ssdt. When a SoC now assigns pci_domain_fill_ssdt to its domain operation's acpi_fill_ssdt function pointer, the PCI domain resource producer information will be added to the SSDT. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80464 Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/Makefile.mk A src/acpi/acpigen_pci_root_resource_producer.c M src/include/acpi/acpigen_pci.h M src/soc/amd/cezanne/chip.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/include/amdblocks/data_fabric.h M src/soc/amd/genoa_poc/domain.c M src/soc/amd/glinda/chip.c M src/soc/amd/mendocino/chip.c M src/soc/amd/phoenix/chip.c M src/soc/amd/picasso/chip.c 11 files changed, 121 insertions(+), 107 deletions(-) Approvals: Matt DeVillier: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/acpi/Makefile.mk b/src/acpi/Makefile.mk index 6bb34cb..e9d5cb0 100644 --- a/src/acpi/Makefile.mk +++ b/src/acpi/Makefile.mk @@ -7,6 +7,7 @@ ramstage-y += acpi_apic.c ramstage-y += acpi_dmar.c ramstage-y += acpi_hpet.c +ramstage-y += acpigen_pci_root_resource_producer.c endif ramstage-$(CONFIG_ACPI_PPTT) += acpi_pptt.c ramstage-y += acpigen.c diff --git a/src/acpi/acpigen_pci_root_resource_producer.c b/src/acpi/acpigen_pci_root_resource_producer.c new file mode 100644 index 0000000..c9efe0e --- /dev/null +++ b/src/acpi/acpigen_pci_root_resource_producer.c @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> +#include <arch/pci_io_cfg.h> +#include <arch/vga.h> +#include <console/console.h> +#include <device/device.h> +#include <types.h> + +static void write_ssdt_domain_io_producer_range_helper(const char *domain_name, + resource_t base, resource_t limit) +{ + printk(BIOS_DEBUG, "%s _CRS: adding IO range [%llx-%llx]\n", domain_name, base, limit); + acpigen_resource_producer_io(base, limit); +} + +static void write_ssdt_domain_io_producer_range(const char *domain_name, + resource_t base, resource_t limit) +{ + /* + * Split the IO region at the PCI config IO ports so that the IO resource producer + * won't cover the same IO ports that the IO resource consumer for the PCI config IO + * ports in the same ACPI device already covers. + */ + if (base < PCI_IO_CONFIG_INDEX) { + write_ssdt_domain_io_producer_range_helper(domain_name, + base, + MIN(limit, PCI_IO_CONFIG_INDEX - 1)); + } + if (limit > PCI_IO_CONFIG_LAST_PORT) { + write_ssdt_domain_io_producer_range_helper(domain_name, + MAX(base, PCI_IO_CONFIG_LAST_PORT + 1), + limit); + } +} + +static void write_ssdt_domain_mmio_producer_range(const char *domain_name, + resource_t base, resource_t limit) +{ + printk(BIOS_DEBUG, "%s _CRS: adding MMIO range [%llx-%llx]\n", + domain_name, base, limit); + acpigen_resource_producer_mmio(base, limit, + MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_NON_CACHE); +} + +void pci_domain_fill_ssdt(const struct device *domain) +{ + const char *acpi_scope = acpi_device_path(domain); + printk(BIOS_DEBUG, "%s ACPI scope: '%s'\n", __func__, acpi_scope); + acpigen_write_scope(acpi_device_path(domain)); + + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + + /* PCI bus number range in domain */ + printk(BIOS_DEBUG, "%s _CRS: adding busses [%x-%x] in segment group %x\n", + acpi_device_name(domain), domain->downstream->secondary, + domain->downstream->max_subordinate, domain->downstream->segment_group); + acpigen_resource_producer_bus_number(domain->downstream->secondary, + domain->downstream->max_subordinate); + + if (domain->path.domain.domain == 0) { + /* ACPI 6.4.2.5 I/O Port Descriptor */ + acpigen_write_io16(PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_LAST_PORT, 1, + PCI_IO_CONFIG_PORT_COUNT, 1); + } + + struct resource *res; + for (res = domain->resource_list; res != NULL; res = res->next) { + if (!(res->flags & IORESOURCE_ASSIGNED)) + continue; + /* Don't add MMIO producer ranges for reserved MMIO regions from non-PCI + devices */ + if (res->flags & IORESOURCE_RESERVE) + continue; + /* Don't add MMIO producer ranges for DRAM regions */ + if (res->flags & IORESOURCE_STORED) + continue; + switch (res->flags & IORESOURCE_TYPE_MASK) { + case IORESOURCE_IO: + write_ssdt_domain_io_producer_range(acpi_device_name(domain), + res->base, res->limit); + break; + case IORESOURCE_MEM: + write_ssdt_domain_mmio_producer_range(acpi_device_name(domain), + res->base, res->limit); + break; + default: + break; + } + } + + if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_DEBUG, "%s _CRS: adding VGA resource\n", acpi_device_name(domain)); + acpigen_resource_producer_mmio(VGA_MMIO_BASE, VGA_MMIO_LIMIT, + MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_CACHE); + } + + acpigen_write_resourcetemplate_footer(); + + acpigen_write_SEG(domain->downstream->segment_group); + acpigen_write_BBN(domain->downstream->secondary); + /* Scope */ + acpigen_pop_len(); +} diff --git a/src/include/acpi/acpigen_pci.h b/src/include/acpi/acpigen_pci.h index 8a96eb3..69216ec 100644 --- a/src/include/acpi/acpigen_pci.h +++ b/src/include/acpi/acpigen_pci.h @@ -14,4 +14,6 @@ void acpigen_write_PRT_source_entry(unsigned int pci_dev, unsigned int acpi_pin, const char *source_path, unsigned int index); +void pci_domain_fill_ssdt(const struct device *domain); + #endif /* ACPIGEN_PCI_H */ diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index 83fd5c6..7463352 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpigen_pci.h> #include <amdblocks/acpi.h> #include <amdblocks/data_fabric.h> #include <amdblocks/fsp.h> @@ -32,7 +33,7 @@ .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, - .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, + .acpi_fill_ssdt = pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index ab85e2b5..b056d60 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpigen.h> #include <amdblocks/data_fabric.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> #include <console/console.h> #include <cpu/amd/mtrr.h> #include <cpu/cpu.h> @@ -214,100 +212,3 @@ read_soc_memmap_resources(domain, &idx); } } - -static void write_ssdt_domain_io_producer_range_helper(const char *domain_name, - resource_t base, resource_t limit) -{ - printk(BIOS_DEBUG, "%s _CRS: adding IO range [%llx-%llx]\n", domain_name, base, limit); - acpigen_resource_producer_io(base, limit); -} - -static void write_ssdt_domain_io_producer_range(const char *domain_name, - resource_t base, resource_t limit) -{ - /* - * Split the IO region at the PCI config IO ports so that the IO resource producer - * won't cover the same IO ports that the IO resource consumer for the PCI config IO - * ports in the same ACPI device already covers. - */ - if (base < PCI_IO_CONFIG_INDEX) { - write_ssdt_domain_io_producer_range_helper(domain_name, - base, - MIN(limit, PCI_IO_CONFIG_INDEX - 1)); - } - if (limit > PCI_IO_CONFIG_LAST_PORT) { - write_ssdt_domain_io_producer_range_helper(domain_name, - MAX(base, PCI_IO_CONFIG_LAST_PORT + 1), - limit); - } -} - -static void write_ssdt_domain_mmio_producer_range(const char *domain_name, - resource_t base, resource_t limit) -{ - printk(BIOS_DEBUG, "%s _CRS: adding MMIO range [%llx-%llx]\n", - domain_name, base, limit); - acpigen_resource_producer_mmio(base, limit, - MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_NON_CACHE); -} - -void amd_pci_domain_fill_ssdt(const struct device *domain) -{ - const char *acpi_scope = acpi_device_path(domain); - printk(BIOS_DEBUG, "%s ACPI scope: '%s'\n", __func__, acpi_scope); - acpigen_write_scope(acpi_device_path(domain)); - - acpigen_write_name("_CRS"); - acpigen_write_resourcetemplate_header(); - - /* PCI bus number range in domain */ - printk(BIOS_DEBUG, "%s _CRS: adding busses [%x-%x] in segment group %x\n", - acpi_device_name(domain), domain->downstream->secondary, - domain->downstream->max_subordinate, domain->downstream->segment_group); - acpigen_resource_producer_bus_number(domain->downstream->secondary, - domain->downstream->max_subordinate); - - if (domain->path.domain.domain == 0) { - /* ACPI 6.4.2.5 I/O Port Descriptor */ - acpigen_write_io16(PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_LAST_PORT, 1, - PCI_IO_CONFIG_PORT_COUNT, 1); - } - - struct resource *res; - for (res = domain->resource_list; res != NULL; res = res->next) { - if (!(res->flags & IORESOURCE_ASSIGNED)) - continue; - /* Don't add MMIO producer ranges for reserved MMIO regions from non-PCI - devices */ - if (res->flags & IORESOURCE_RESERVE) - continue; - /* Don't add MMIO producer ranges for DRAM regions */ - if (res->flags & IORESOURCE_STORED) - continue; - switch (res->flags & IORESOURCE_TYPE_MASK) { - case IORESOURCE_IO: - write_ssdt_domain_io_producer_range(acpi_device_name(domain), - res->base, res->limit); - break; - case IORESOURCE_MEM: - write_ssdt_domain_mmio_producer_range(acpi_device_name(domain), - res->base, res->limit); - break; - default: - break; - } - } - - if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_DEBUG, "%s _CRS: adding VGA resource\n", acpi_device_name(domain)); - acpigen_resource_producer_mmio(VGA_MMIO_BASE, VGA_MMIO_LIMIT, - MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_CACHE); - } - - acpigen_write_resourcetemplate_footer(); - - acpigen_write_SEG(domain->downstream->segment_group); - acpigen_write_BBN(domain->downstream->secondary); - /* Scope */ - acpigen_pop_len(); -} diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index f0073df..fbed0b2 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -55,6 +55,4 @@ void amd_pci_domain_read_resources(struct device *domain); void amd_pci_domain_scan_bus(struct device *domain); -void amd_pci_domain_fill_ssdt(const struct device *domain); - #endif /* AMD_BLOCK_DATA_FABRIC_H */ diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index 14248cd..5672f65 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpigen_pci.h> #include <amdblocks/ioapic.h> #include <amdblocks/data_fabric.h> #include <amdblocks/root_complex.h> @@ -63,5 +64,5 @@ .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = genoa_domain_acpi_name, - .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, + .acpi_fill_ssdt = pci_domain_fill_ssdt, }; diff --git a/src/soc/amd/glinda/chip.c b/src/soc/amd/glinda/chip.c index 515580d..e227f41 100644 --- a/src/soc/amd/glinda/chip.c +++ b/src/soc/amd/glinda/chip.c @@ -2,6 +2,7 @@ /* TODO: Update for Glinda */ +#include <acpi/acpigen_pci.h> #include <amdblocks/acpi.h> #include <amdblocks/data_fabric.h> #include <amdblocks/fsp.h> @@ -34,7 +35,7 @@ .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, - .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, + .acpi_fill_ssdt = pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/mendocino/chip.c b/src/soc/amd/mendocino/chip.c index 729f97a..fb61f585 100644 --- a/src/soc/amd/mendocino/chip.c +++ b/src/soc/amd/mendocino/chip.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpigen_pci.h> #include <amdblocks/acpi.h> #include <amdblocks/data_fabric.h> #include <amdblocks/fsp.h> @@ -32,7 +33,7 @@ .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, - .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, + .acpi_fill_ssdt = pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/phoenix/chip.c b/src/soc/amd/phoenix/chip.c index f45e7b8..a88468b 100644 --- a/src/soc/amd/phoenix/chip.c +++ b/src/soc/amd/phoenix/chip.c @@ -2,6 +2,7 @@ /* TODO: Update for Phoenix */ +#include <acpi/acpigen_pci.h> #include <amdblocks/acpi.h> #include <amdblocks/data_fabric.h> #include <amdblocks/fsp.h> @@ -35,7 +36,7 @@ .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, - .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, + .acpi_fill_ssdt = pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 7411948..e642060 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpigen_pci.h> #include <amdblocks/acpi.h> #include <amdblocks/data_fabric.h> #include <amdblocks/fsp.h> @@ -33,7 +34,7 @@ .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, - .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, + .acpi_fill_ssdt = pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) -- To view, visit https://review.coreboot.org/c/coreboot/+/80464?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99 Gerrit-Change-Number: 80464 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/
by Felix Held (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Arthur Heymans, Cliff Huang, Fred Reitberger, Jason Glenesk, Lance Zhao, Nico Huber, Tim Wawrzynczak. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80464?usp=email ) Change subject: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/ ...................................................................... Patch Set 3: (2 comments) Patchset: PS3: > Tested on IBM/SBP1. Boots to ubuntu 22. […] awesome :) File src/acpi/acpigen_pci_root_resource_producer.c: https://review.coreboot.org/c/coreboot/+/80464/comment/fbfe5fc6_bdf86784 : PS3, Line 57: -% > %02x would be great i'll push a follow-up to address those -- To view, visit https://review.coreboot.org/c/coreboot/+/80464?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99 Gerrit-Change-Number: 80464 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Feb 2024 15:39:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection
by Gwendal Grignou (Code Review) 29 Feb '24

29 Feb '24

Attention is currently required from: Paul Menzel, Paz Zcharya, Subrata Banik. Gwendal Grignou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80738?usp=email ) Change subject: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > @Gwendal, I can request you to take a look at my responses against the open comments from you? […] which one? -- To view, visit https://review.coreboot.org/c/coreboot/+/80738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bb1e868764738333977bd8c990bea4253c9d37b Gerrit-Change-Number: 80738 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 29 Feb 2024 15:36:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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