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Change subject: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection
......................................................................
Patch Set 7:
(1 comment)
File src/vendorcode/google/chromeos/tpm_factory_config.c:
https://review.coreboot.org/c/coreboot/+/80738/comment/a4768747_d67239da :
PS7, Line 104: return strncmp(vpd_get_feature_device_info(), "CAI", 3) == 0;
> | Regular Chromebook device […]
As discussed in the meeting, in chromeos_device_branded_plus_soft() we can completely ignore GSC information and go by reading the VPD. Until protobuf decoding is added to coreboot, the device will be a regular chromebook when vpd_get_feature_device_info() is empty or indicates the feature_level is 0.
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Hello Jeremy Soller, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80756?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/system76/adl,rpl: Add FSP default timeout for PCIe 3.0 RPs
......................................................................
mb/system76/adl,rpl: Add FSP default timeout for PCIe 3.0 RPs
The FSP may fail to detect PCIe 4.0 devices in PCIe 3.0 slots on S3
resume. This issue has only been experienced on lemp12, and only with
Samsung drives, but implies it could happen on other systems or with
other drives as well. Use the FSP default value of 56ms.
Tested on lemp12 with Samsung 980 PRO and 990 PRO drives.
Change-Id: I4f44fc429c52e407b7566d6bb6dd31b2cf85c48d
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
M src/mainboard/system76/adl/variants/darp8/overridetree.cb
M src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb
M src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb
M src/mainboard/system76/adl/variants/lemp11/overridetree.cb
M src/mainboard/system76/rpl/variants/gaze18/overridetree.cb
M src/mainboard/system76/rpl/variants/lemp12/overridetree.cb
6 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/80756/2
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Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80791?usp=email )
Change subject: mb/system76/rpl: Add TCSS ACPI for all boards
......................................................................
mb/system76/rpl: Add TCSS ACPI for all boards
Fixes ACPI errors about missing methods:
ACPI BIOS Error (bug): Could not resolve symbol [_SB.PCI0.TDM0], AE_NOT_FOUND (20230628/dswload2-162)
ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220)
ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x0010)
ACPI BIOS Error (bug): Could not resolve symbol [_SB.PCI0.TRP0], AE_NOT_FOUND (20230628/dswload2-162)
ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220)
Tested on lemp12: ACPI errors in dmesg are gone.
Change-Id: I9b79cb04f57a27af2a6c8f3118e573f7ac0041e5
Signed-off-by: Dan Campbell <dan(a)compiledworks.com>
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
M src/mainboard/system76/rpl/dsdt.asl
1 file changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/80791/1
diff --git a/src/mainboard/system76/rpl/dsdt.asl b/src/mainboard/system76/rpl/dsdt.asl
index addb4df..cbf9e6a 100644
--- a/src/mainboard/system76/rpl/dsdt.asl
+++ b/src/mainboard/system76/rpl/dsdt.asl
@@ -19,9 +19,7 @@
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/alderlake/acpi/southbridge.asl>
- #if CONFIG(BOARD_SYSTEM76_ORYP11)
- #include <soc/intel/alderlake/acpi/tcss.asl>
- #endif // CONFIG(BOARD_SYSTEM76_ORYP11)
+ #include <soc/intel/alderlake/acpi/tcss.asl>
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
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Change subject: mb/emulation/qemu-riscv: Change to -bios option
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> what is the reason for using both -bios and -pflash? […]
If I only use -pflash QEMU will start OpenSBI and skip coreboot alltogether.
If I only use -bios than QEMU will place coreboot in DRAM, but will not give us a flash as backing storage (which we need to fetch CBFS stuff from).
If I use -pflash and `-bios none` than QEMU will jump to Flash with XIP. That is also something we could support, but it is a bit inconvenient and not done in coreboot yet for RISC-V and ARM I think.
If I use both -pflash and -bios coreboot.rom then QEMU will place coreboot in DRAM (like on current AMD platforms I think) and give us a backing storage to pull CBFS stages and stuff from.
It is a bit confusing.
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Change subject: soc/sifive/fu740: Add FU740 SOC
......................................................................
Patch Set 10:
(1 comment)
This change is ready for review.
File src/soc/sifive/fu740/sdram.c:
https://review.coreboot.org/c/coreboot/+/76689/comment/2210178a_0734ba2f :
PS10, Line 161: static void ux00ddr_phy_fixup(void *ahbregaddr)
this has never actually been tested by me, but it is hard to test.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80711?usp=email )
Change subject: mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS
......................................................................
mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS
No Windows driver exists or is needed, so hide to prevent an unknown
device from being listed in Windows Device Manager. Same change was
made for frostflow variant previously.
TEST=build/boot Win11 on skyrim, verify unknown device for the
fingerprint reader no longer present.
Change-Id: Ia700aa4ccd478bc734db012e1419e566a5dcf493
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80711
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/skyrim/variants/skyrim/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Nico Huber: Looks good to me, but someone else must approve
Felix Held: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb
index eb16120..be498fc 100644
--- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb
@@ -238,7 +238,7 @@
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_4)"
register "enable_delay_ms" = "3"
- device generic 0 alias fpmcu on
+ device generic 0 alias fpmcu hidden
probe FP FP_PRESENT
end
end
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Change subject: mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/emulation/qemu-riscv: Change to -bios option
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
what is the reason for using both -bios and -pflash?
qemu supports booting from flash only:
see https://github.com/qemu/qemu/blob/master/hw/riscv/virt.c#L1305
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Change subject: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/
......................................................................
Patch Set 4:
(2 comments)
File src/acpi/acpigen_pci_root_resource_producer.c:
https://review.coreboot.org/c/coreboot/+/80464/comment/81a1f1c3_50672b0d :
PS3, Line 14: IO
> pad by two spaces to align with MMIO
since the values after that have a substantially different length, i'm not sure if that's worth it
https://review.coreboot.org/c/coreboot/+/80464/comment/17444622_64dfd8c2 :
PS3, Line 57: -%
> i'll push a follow-up to address those
CB:80804
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