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Change subject: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver
......................................................................
Patch Set 30:
(2 comments)
File src/soc/mediatek/common/mt6363_sdmadc.c:
https://review.coreboot.org/c/coreboot/+/85128/comment/767317c6_783603c2?us… :
PS30, Line 64: int
Sorry, I just found a few problems when reviewing CB:85666.
Is this supposed to be u32 (or u16)? Either way, it should not be a signed type.
https://review.coreboot.org/c/coreboot/+/85128/comment/b1a86fb0_0a5f6974?us… :
PS30, Line 107: regval * chan->hw_info.ratio[0] * chan->hw_info.ref_volt
Is the multiplication likely to overflow (if so we need to cast to u64)? Could you check the maximum possible values of `chan->hw_info.res`, `chan->hw_info.ratio[0]` and `chan->hw_info.ref_volt`?
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Change subject: mb/google/rauru: Implement SKU ID
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Patch Set 7:
This change is ready for review.
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Change subject: mb/google/rauru: Disable modem power
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/rauru/romstage.c:
https://review.coreboot.org/c/coreboot/+/85663/comment/4a8883cb_73bfea63?us… :
PS1, Line 7: #include <soc/md_power_ctrl.h>
sort
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Change subject: soc/mediatek/mt8196: Add disable modem power driver
......................................................................
Patch Set 3:
(8 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85651/comment/8d550187_c1a2f334?us… :
PS3, Line 7: disable modem power driver
modem power driver to disable unused power
File src/soc/mediatek/mt8196/include/soc/md_power_ctrl.h:
https://review.coreboot.org/c/coreboot/+/85651/comment/715ad173_8daad33e?us… :
PS3, Line 6: /*
: * md_power_down() - Power down modem
: */
`/* Power down modem. */`
https://review.coreboot.org/c/coreboot/+/85651/comment/7849b714_22a9c652?us… :
PS3, Line 9: md
> modem
Also rename the file to modem_power_ctrl.*.
File src/soc/mediatek/mt8196/md_power_ctrl.c:
https://review.coreboot.org/c/coreboot/+/85651/comment/1d579c43_ba13bfc2?us… :
PS3, Line 28: mtk_apifrbus_ao_io_reg_bus
As this is used only in this file, can we have a shorter name?
https://review.coreboot.org/c/coreboot/+/85651/comment/3984858b_1fe0e54a?us… :
PS3, Line 31: struct mtk_spm_regs {
: u32 reserved0[896];
: u32 md1_pwr_con;
: u32 reserved1[20];
: u32 adsp_top_pwr_con;
: u32 adsp_infra_pwr_con;
: u32 adsp_ao_pwr_con;
: u32 reserved2[11];
: u32 spu_hwrot_pwr_con;
: u32 reserved3[27];
: u32 md_buck_iso_con;
: u32 reserved4[5];
: u32 pwr_status;
: u32 pwr_status_2nd;
: };
:
: static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
This is already defined in spm.h. Please rebase onto CB:85599.
https://review.coreboot.org/c/coreboot/+/85651/comment/74ed6362_e3c301dd?us… :
PS3, Line 50: OTHER_SRAM_CKISO = BIT(0),
: PWR_RST_B = BIT(0),
Are these both for the `md1_pwr_con` register?
https://review.coreboot.org/c/coreboot/+/85651/comment/2c8a9a89_030cd488?us… :
PS3, Line 52: OTHER_SRAM_ISOINT_B = BIT(1),
: PWR_ISO = BIT(1),
Same here. Why do we have two definitions for the same bit?
https://review.coreboot.org/c/coreboot/+/85651/comment/814c3d5d_da2b69a5?us… :
PS3, Line 90: struct pmif *pmif_arb = get_pmif_controller(PMIF_SPMI, SPMI_MASTER_1);
:
: /* Vsram_vosel = 0x24d, read Vsram value */
: reg = VSRAM_VOSEL;
: pmif_arb->read(pmif_arb, SPMI_SLAVE_4, reg, &val);
:
: /* Vmodem_vosel = 0x24e, write Vmodem 0.75V */
: reg = VMODEM_VOSEL;
: pmif_arb->write(pmif_arb, SPMI_SLAVE_4, reg, SPMI_SLAVE_4_750MV);
: pmif_arb->read(pmif_arb, SPMI_SLAVE_4, reg, &val);
> Add `mt6363_write8` to `common/mt6363.c`. […]
One minor side effect is that `pmif_check_init_done` will be called multiple times. As future improvement, we may store `bool is_init_done` in `struct pmif` to prevent multiple calls.
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Change subject: soc/intel/alderlake: Add function to force disable memory channels
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/85529/comment/081f3f29_03cb9e0b?us… :
PS8, Line 259: printk(BIOS_ERR, "Cannot disable the first channel.\n");
(Mc0Ch0)
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Change subject: mb/google/fatcat: Keep GSPIx interface default PCI
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Why are we keeping this default to PCI instead of disabled?
I think it's a good idea to keep the GSPIx interface enabled by default in the devicetree. That way, we can configure it from the respective overrides, and we won't accidentally miss anything if we forget to add an override tree entry.
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Change subject: soc/mediatek/mt8189: Initialize watchdog
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Patch Set 3: Code-Review+2
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Change subject: soc/mediatek/common: Update timer macro name
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Patch Set 1: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85681/comment/f12f8e4a_c52c460d?us… :
PS1, Line 7: Update timer macro name
> Replace GPT_MHZ with TIMER_MHZ for readability
Or `Rename GPT_MHZ to TIMER_MHZ for readability`
https://review.coreboot.org/c/coreboot/+/85681/comment/4cef5c35_50b9829b?us… :
PS1, Line 11: The new ICs(e.g. mt8196, mt8189) will no longer use GPT, and in order
: to improve code readability, so replace GPT_MHZ of existing Soc's
: with macro name TIMER_MHZ.
> The new ICs(e.g. mt8196, mt8189) is no longer using GPT. […]
nit: space before `(`
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