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Change subject: docs/security/vboot: Update supported boards
......................................................................
Patch Set 1: Code-Review+2
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Change subject: docs: Add 24.12 release notes
......................................................................
Patch Set 6: Code-Review+2
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Change subject: util/ifdtool: Fix memory leaks
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Patch Set 1: Code-Review+2
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Hello Angel Pons, Jason Glenesk, Martin L Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85683?usp=email
to look at the new patch set (#6).
Change subject: docs: Add 24.12 release notes
......................................................................
docs: Add 24.12 release notes
Change-Id: Ifeb88a1bb4f05183ac9274de9b26970b6155017d
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
A Documentation/releases/coreboot-24.12-relnotes.md
1 file changed, 337 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/85683/6
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Hello Angel Pons, Jason Glenesk, Martin L Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85683?usp=email
to look at the new patch set (#5).
Change subject: docs: Add 24.12 release notes
......................................................................
docs: Add 24.12 release notes
Change-Id: Ifeb88a1bb4f05183ac9274de9b26970b6155017d
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
A Documentation/releases/coreboot-24.12-relnotes.md
1 file changed, 337 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/85683/5
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85685?usp=email )
Change subject: soc/intel/pantherlake: Rename GSPI2 to GSPI0A
......................................................................
soc/intel/pantherlake: Rename GSPI2 to GSPI0A
Rename GSPI2 to GSPI0A to align with the latest Intel documentation
and platform specifications (doc: 815002)
BUG=b:377595986
TEST=Able to see 0x12.6 device is visible using `lspci`.
Change-Id: I9b87d38e44c07a053104b53df38ee1ce14a86c7f
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/pantherlake/chipset.cb
M src/soc/intel/pantherlake/include/soc/serialio.h
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/85685/1
diff --git a/src/soc/intel/pantherlake/chipset.cb b/src/soc/intel/pantherlake/chipset.cb
index 67e0785..0f7967b 100644
--- a/src/soc/intel/pantherlake/chipset.cb
+++ b/src/soc/intel/pantherlake/chipset.cb
@@ -90,7 +90,7 @@
device pci 10.1 alias thc1 off end
device pci 12.0 alias ish off end
device pci 12.1 alias p2sb2 hidden end
- device pci 12.6 alias gspi2 off end
+ device pci 12.6 alias gspi0a off end
device pci 13.0 alias heci_1 off end
device pci 13.1 alias heci_2 off end
device pci 13.2 alias heci_3 off end
diff --git a/src/soc/intel/pantherlake/include/soc/serialio.h b/src/soc/intel/pantherlake/include/soc/serialio.h
index def5565..1c15001 100644
--- a/src/soc/intel/pantherlake/include/soc/serialio.h
+++ b/src/soc/intel/pantherlake/include/soc/serialio.h
@@ -23,7 +23,7 @@
enum {
PchSerialIoIndexGSPI0,
PchSerialIoIndexGSPI1,
- PchSerialIoIndexGSPI2,
+ PchSerialIoIndexGSPI0A,
};
enum {
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