coreboot-gerrit December 2024

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[L] Change in coreboot[main]: soc/mediatek/mt8189: Add GPIO driver
by Yidi Lin (Code Review) 21 Dec '24

21 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85667?usp=email ) Change subject: soc/mediatek/mt8189: Add GPIO driver ...................................................................... soc/mediatek/mt8189: Add GPIO driver Add GPIO driver for other modules to control GPIO pins. BUG=b:379008996 BRANCH=none TEST=build pass Change-Id: Ia87fe0975add95fcfad16d55586559c7f912a624 Signed-off-by: Cathy Xu <ot_cathy.xu(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85667 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8189/Makefile.mk A src/soc/mediatek/mt8189/gpio.c A src/soc/mediatek/mt8189/include/soc/gpio.h 3 files changed, 854 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk index e997ec1..3dc16be 100644 --- a/src/soc/mediatek/mt8189/Makefile.mk +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8189),y) +all-y += ../common/gpio.c ../common/gpio_op.c gpio.c all-$(CONFIG_SPI_FLASH) += spi.c all-y += timer.c all-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8189/gpio.c b/src/soc/mediatek/mt8189/gpio.c new file mode 100644 index 0000000..27179c3 --- /dev/null +++ b/src/soc/mediatek/mt8189/gpio.c @@ -0,0 +1,274 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 9.2 + */ + +#include <device/mmio.h> +#include <gpio.h> + +static const struct gpio_drv_info gpio_driving_info[] = { + [0] = { 0x10, 15, 3, }, + [1] = { 0x10, 9, 3, }, + [2] = { 0x10, 12, 3, }, + [3] = { 0x10, 15, 3, }, + [4] = { 0x10, 18, 3, }, + [5] = { 0x10, 21, 3, }, + [6] = { 0x10, 18, 3, }, + [7] = { 0x10, 21, 3, }, + [8] = { 0x10, 24, 3, }, + [9] = { 0x10, 27, 3, }, + [10] = { 0x10, 0, 3, }, + [11] = { 0x10, 3, 3, }, + [12] = { 0x10, 15, 3, }, + [13] = { 0x10, 18, 3, }, + [14] = { 0x10, 0, 3, }, + [15] = { 0x10, 3, 3, }, + [16] = { 0x10, 21, 3, }, + [17] = { 0x10, 24, 3, }, + [18] = { 0x10, 0, 3, }, + [19] = { 0x10, 6, 3, }, + [20] = { 0x10, 3, 3, }, + [21] = { 0x10, 9, 3, }, + [22] = { 0x10, 0, 3, }, + [23] = { 0x10, 3, 3, }, + [24] = { 0x10, 6, 3, }, + [25] = { 0x10, 6, 3, }, + [26] = { 0x10, 3, 3, }, + [27] = { 0x10, 3, 3, }, + [28] = { 0x10, 6, 3, }, + [29] = { 0x10, 0, 3, }, + [30] = { 0x10, 0, 3, }, + [31] = { 0x10, 27, 3, }, + [32] = { 0x10, 0, 3, }, + [33] = { 0x10, 3, 3, }, + [34] = { 0x10, 0, 3, }, + [35] = { 0x10, 9, 3, }, + [36] = { 0x10, 6, 3, }, + [37] = { 0x10, 15, 3, }, + [38] = { 0x10, 12, 3, }, + [39] = { 0x10, 15, 3, }, + [40] = { 0x10, 6, 3, }, + [41] = { 0x10, 9, 3, }, + [42] = { 0x10, 12, 3, }, + [43] = { 0x10, 18, 3, }, + [44] = { 0x10, 0, 3, }, + [45] = { 0x10, 3, 3, }, + [46] = { 0x10, 6, 3, }, + [47] = { 0x10, 9, 3, }, + [48] = { 0x10, 15, 3, }, + [49] = { 0x10, 12, 3, }, + [50] = { 0x10, 9, 3, }, + [51] = { 0x10, 24, 3, }, + [52] = { 0x10, 0, 3, }, + [53] = { 0x10, 27, 3, }, + [54] = { 0x10, 3, 3, }, + [55] = { 0x10, 18, 3, }, + [56] = { 0x10, 21, 3, }, + [57] = { 0x10, 9, 3, }, + [58] = { 0x10, 21, 3, }, + [59] = { 0x10, 12, 3, }, + [60] = { 0x10, 24, 3, }, + [61] = { 0x10, 15, 3, }, + [62] = { 0x10, 27, 3, }, + [63] = { 0x10, 18, 3, }, + [64] = { 0x10, 0, 3, }, + [65] = { 0x10, 0, 3, }, + [66] = { 0x10, 6, 3, }, + [67] = { 0x10, 3, 3, }, + [68] = { 0x10, 9, 3, }, + [69] = { 0x10, 6, 3, }, + [70] = { 0x10, 3, 3, }, + [71] = { 0x10, 12, 3, }, + [72] = { 0x10, 9, 3, }, + [73] = { 0x10, 18, 3, }, + [74] = { 0x10, 15, 3, }, + [75] = { 0x10, 9, 3, }, + [76] = { 0x10, 21, 3, }, + [77] = { 0x10, 9, 3, }, + [78] = { 0x10, 6, 3, }, + [79] = { 0x10, 15, 3, }, + [80] = { 0x10, 12, 3, }, + [81] = { 0x10, 27, 3, }, + [82] = { 0x10, 24, 3, }, + [83] = { 0x10, 0, 3, }, + [84] = { 0x10, 12, 3, }, + [85] = { 0x10, 15, 3, }, + [86] = { 0x10, 18, 3, }, + [87] = { 0x10, 21, 3, }, + [88] = { 0x10, 0, 3, }, + [89] = { 0x10, 27, 3, }, + [90] = { 0x10, 6, 3, }, + [91] = { 0x10, 3, 3, }, + [92] = { 0x10, 18, 3, }, + [93] = { 0x10, 21, 3, }, + [94] = { 0x10, 9, 3, }, + [95] = { 0x10, 15, 3, }, + [96] = { 0x10, 24, 3, }, + [97] = { 0x10, 0, 3, }, + [98] = { 0x10, 15, 3, }, + [99] = { 0x10, 9, 3, }, + [100] = { 0x10, 12, 3, }, + [101] = { 0x10, 3, 3, }, + [102] = { 0x10, 6, 3, }, + [103] = { 0x10, 15, 3, }, + [104] = { 0x10, 6, 3, }, + [105] = { 0x10, 12, 3, }, + [106] = { 0x10, 9, 3, }, + [107] = { 0x10, 27, 3, }, + [108] = { 0x10, 18, 3, }, + [109] = { 0x10, 24, 3, }, + [110] = { 0x10, 21, 3, }, + [111] = { 0x10, 12, 3, }, + [112] = { 0x10, 0, 3, }, + [113] = { 0x10, 3, 3, }, + [114] = { 0x10, 6, 3, }, + [115] = { 0x10, 27, 3, }, + [116] = { 0x10, 6, 3, }, + [117] = { 0x10, 0, 3, }, + [118] = { 0x10, 3, 3, }, + [119] = { 0x10, 18, 3, }, + [120] = { 0x10, 15, 3, }, + [121] = { 0x10, 12, 3, }, + [122] = { 0x10, 9, 3, }, + [123] = { 0x10, 27, 3, }, + [124] = { 0x10, 24, 3, }, + [125] = { 0x10, 21, 3, }, + [126] = { 0x10, 18, 3, }, + [127] = { 0x10, 6, 3, }, + [128] = { 0x10, 15, 3, }, + [129] = { 0x10, 0, 3, }, + [130] = { 0x10, 21, 3, }, + [131] = { 0x10, 9, 3, }, + [132] = { 0x10, 12, 3, }, + [133] = { 0x10, 24, 3, }, + [134] = { 0x10, 3, 3, }, + [135] = { 0x10, 3, 3, }, + [136] = { 0x10, 6, 3, }, + [137] = { 0x10, 9, 3, }, + [138] = { 0x10, 12, 3, }, + [139] = { 0x10, 9, 3, }, + [140] = { 0x10, 12, 3, }, + [141] = { 0x10, 0, 3, }, + [142] = { 0x10, 3, 3, }, + [143] = { 0x10, 6, 3, }, + [144] = { 0x10, 15, 3, }, + [145] = { 0x10, 18, 3, }, + [146] = { 0x10, 21, 3, }, + [147] = { 0x10, 24, 3, }, + [148] = { 0x10, 27, 3, }, + [149] = { 0x10, 0, 3, }, + [150] = { 0x10, 12, 3, }, + [151] = { 0x10, 27, 3, }, + [152] = { 0x10, 15, 3, }, + [153] = { 0x10, 18, 3, }, + [154] = { 0x10, 21, 3, }, + [155] = { 0x10, 24, 3, }, + [156] = { 0x10, 6, 3, }, + [157] = { 0x10, 3, 3, }, + [158] = { 0x10, 0, 3, }, + [159] = { 0x10, 6, 3, }, + [160] = { 0x10, 12, 3, }, + [161] = { 0x10, 21, 3, }, + [162] = { 0x10, 18, 3, }, + [163] = { 0x10, 3, 3, }, + [164] = { 0x10, 27, 3, }, + [165] = { 0x10, 24, 3, }, + [166] = { 0x10, 0, 3, }, + [167] = { 0x10, 9, 3, }, + [168] = { 0x10, 24, 3, }, + [169] = { 0x10, 21, 3, }, + [170] = { 0x10, 27, 3, }, + [171] = { 0x10, 0, 3, }, + [172] = { 0x10, 3, 3, }, + [173] = { 0x10, 6, 3, }, + [174] = { 0x10, 15, 3, }, + [175] = { 0x10, 12, 3, }, + [176] = { 0x10, 18, 3, }, + [177] = { 0x10, 21, 3, }, + [178] = { 0x10, 24, 3, }, + [179] = { 0x10, 27, 3, }, + [180] = { 0x10, 12, 3, }, + [181] = { 0x10, 15, 3, }, + [182] = { 0x10, 9, 3, }, +}; +_Static_assert(ARRAY_SIZE(gpio_driving_info) == GPIO_NUM, + "gpio_driving_info array size not match"); + +static const struct gpio_drv_info gpio_driving_adv_info[] = { + [51] = { 0x10, 0, 3, }, + [52] = { 0x10, 6, 3, }, + [53] = { 0x10, 3, 3, }, + [54] = { 0x10, 9, 3, }, + [55] = { 0x10, 0, 3, }, + [56] = { 0x10, 3, 3, }, + [57] = { 0x10, 0, 3, }, + [58] = { 0x10, 12, 3, }, + [59] = { 0x10, 3, 3, }, + [60] = { 0x10, 15, 3, }, + [61] = { 0x10, 6, 3, }, + [62] = { 0x10, 18, 3, }, + [63] = { 0x10, 9, 3, }, + [64] = { 0x10, 21, 3, }, + [65] = { 0x10, 0, 3, }, + [66] = { 0x10, 6, 3, }, + [67] = { 0x10, 3, 3, }, + [68] = { 0x10, 9, 3, }, + [180] = { 0x10, 0, 3, }, + [181] = { 0x10, 3, 3, }, +}; + +void *gpio_find_reg_addr(gpio_t gpio) +{ + void *reg_addr; + + switch (gpio.base & 0x0f) { + case 1: + reg_addr = (void *)IOCFG_LM_BASE; + break; + case 2: + reg_addr = (void *)IOCFG_RB0_BASE; + break; + case 3: + reg_addr = (void *)IOCFG_RB1_BASE; + break; + case 4: + reg_addr = (void *)IOCFG_BM0_BASE; + break; + case 5: + reg_addr = (void *)IOCFG_BM1_BASE; + break; + case 6: + reg_addr = (void *)IOCFG_BM2_BASE; + break; + case 7: + reg_addr = (void *)IOCFG_LT0_BASE; + break; + case 8: + reg_addr = (void *)IOCFG_LT1_BASE; + break; + case 9: + reg_addr = (void *)IOCFG_RT_BASE; + break; + default: + reg_addr = NULL; + break; + } + + return reg_addr; +} + +const struct gpio_drv_info *get_gpio_driving_info(uint32_t raw_id) +{ + if (raw_id >= ARRAY_SIZE(gpio_driving_info)) + return NULL; + return &gpio_driving_info[raw_id]; +} + +const struct gpio_drv_info *get_gpio_driving_adv_info(uint32_t raw_id) +{ + if (raw_id >= ARRAY_SIZE(gpio_driving_adv_info)) + return NULL; + return &gpio_driving_adv_info[raw_id]; +} diff --git a/src/soc/mediatek/mt8189/include/soc/gpio.h b/src/soc/mediatek/mt8189/include/soc/gpio.h new file mode 100644 index 0000000..91914f1 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/gpio.h @@ -0,0 +1,579 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 9.2 + */ + +#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_GPIO_H__ +#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_GPIO_H__ + +#include <soc/addressmap.h> +#include <soc/gpio_common.h> +#include <soc/gpio_defs.h> +#include <types.h> + +#define GPIO_NUM 183 + +struct gpio_regs { + struct gpio_val_regs dir[16]; + struct gpio_val_regs dout[16]; + struct gpio_val_regs din[16]; + struct gpio_val_regs mode[32]; + uint32_t dram_pinmux_trapping; +}; + +enum { + PIN(0, GPIO00, 0, 0, 0x01, 0, + TP_GPIO0_AO, SPIM3_A_CSB, I2SOUT0_MCK, SCP_SPI0_CS, + RES5, CONN_BPI_BUS6, DBG_MON_A0), + PIN(1, GPIO01, 0, 0, 0x01, 0, + TP_GPIO1_AO, SPIM3_A_CLK, I2SOUT0_BCK, SCP_SPI0_CK, + RES5, CONN_BPI_BUS7, DBG_MON_A1), + PIN(2, GPIO02, 0, 0, 0x01, 0, + TP_GPIO2_AO, SPIM3_A_MO, I2SOUT0_LRCK, SCP_SPI0_MO, + RES5, CONN_BPI_BUS8, DBG_MON_A2), + PIN(3, GPIO03, 0, 0, 0x01, 0, + TP_GPIO3_AO, SPIM3_A_MI, I2SOUT0_DO, SCP_SPI0_MI, + RES5, CONN_BPI_BUS9, DBG_MON_A3), + PIN(4, GPIO04, 0, 0, 0x01, 0, + TP_GPIO4_AO, SPIM4_A_CSB, I2SIN0_DI, SCP_SPI1_CS, + RES5, CONN_BPI_BUS10, DBG_MON_A4), + PIN(5, GPIO05, 0, 0, 0x01, 0, + TP_GPIO5_AO, SPIM4_A_CLK, I2SIN0_BCK, SCP_SPI1_CK, + RES5, CONN_BPI_BUS11_OLAT0, DBG_MON_A5), + PIN(6, GPIO06, 0, 0, 0x01, 0, + TP_GPIO6_AO, SPIM4_A_MO, I2SIN0_LRCK, SCP_SPI1_MO, + RES5, CONN_BPI_BUS12_OLAT1, DBG_MON_A6), + PIN(7, GPIO07, 0, 0, 0x01, 0, + TP_GPIO7_AO, SPIM4_A_MI, I2SIN0_MCK, SCP_SPI1_MI, + RES5, CONN_BPI_BUS13_OLAT2, DBG_MON_A7), + PIN(8, GPIO08, 0, 0, 0x01, 0, + TP_UTXD1_VLP, SPIM5_A_CSB, I2SOUT1_MCK, VADSP_UTXD0, + RES5, CONN_BPI_BUS14_OLAT3, DBG_MON_A8), + PIN(9, GPIO09, 0, 0, 0x01, 0, + TP_URXD1_VLP, SPIM5_A_CLK, I2SOUT1_BCK, VADSP_URXD0, + RES5, CONN_BPI_BUS15_OLAT4, DBG_MON_A9), + PIN(10, GPIO10, 0, 0, 0x01, 0, + TP_UCTS1_VLP, SPIM5_A_MO, I2SOUT1_LRCK, SRCLKENAI0, + RES5, CONN_BPI_BUS16_OLAT5, DBG_MON_A10), + PIN(11, GPIO11, 0, 0, 0x01, 0, + TP_URTS1_VLP, SPIM5_A_MI, I2SOUT1_DO, SRCLKENAI1, + PWM_vlp, RES6, DBG_MON_A11), + PIN(12, GPIO12, 0, 0, 0x01, 0, + TP_UTXD1_VCORE, UTXD3, CLKM0, CMFLASH0, + RES5, ANT_SEL0, DBG_MON_B20), + PIN(13, GPIO13, 0, 0, 0x01, 0, + TP_URXD1_VCORE, URXD3, CLKM1, CMFLASH1, + RES5, ANT_SEL1, DBG_MON_B21), + PIN(14, GPIO14, 0, 0, 0x01, 0, + TP_UCTS1_VCORE, UCTS3, CLKM2, CMFLASH2, + RES5, ANT_SEL2, DBG_MON_B22), + PIN(15, GPIO15, 0, 0, 0x01, 0, + TP_URTS1_VCORE, URTS3, CLKM3, CMVREF0, + RES5, ANT_SEL3, DBG_MON_B23), + PIN(16, GPIO16, 0, 0, 0x01, 0, + PWM_0, UCTS2, DP_TX_HPD, CMVREF1, + MD32_0_GPIO0, ANT_SEL4, DBG_MON_B24), + PIN(17, GPIO17, 0, 0, 0x01, 0, + PWM_1, URTS2, EDP_TX_HPD, CMVREF2, + MD32_1_GPIO0, PMSR_SMAP, DBG_MON_B25), + PIN(18, CMMPDN0, 0, 0, 0x01, 0, + CMFLASH0, CMVREF3, UTXD2, DISP_PWM1, + I2SIN1_MCK, mbistreaden_trigger, DBG_MON_A12), + PIN(19, CMMRST0, 0, 0, 0x01, 0, + CMFLASH1, CMVREF2, URXD2, USB_DRVVBUS_1P, + I2SIN1_BCK, mbistwriteen_trigger, DBG_MON_A13), + PIN(20, CMMPDN1, 0, 0, 0x01, 0, + CMFLASH2, CMVREF1, UCTS2, PERSTN, + I2SIN1_LRCK, DMIC0_DAT1, DBG_MON_A14), + PIN(21, CMMRST1, 0, 0, 0x01, 0, + CMFLASH3, CMVREF0, URTS2, CLKREQN, + I2SIN1_DI, DMIC1_DAT1, DBG_MON_A15), + PIN(22, CMMCLK0, 0, 0, 0x01, 0, + CMMCLK0, TP_GPIO4_AO, RES3, RES4, + RES5, RES6, RES7), + PIN(23, CMMCLK1, 0, 0, 0x01, 0, + CMMCLK1, TP_GPIO5_AO, SSPM_UTXD_AO_VLP, PWM_vlp, + RES5, SRCLKENAI0, RES7), + PIN(24, CMMCLK2, 0, 0, 0x01, 0, + CMMCLK2, TP_GPIO6_AO, SSPM_URXD_AO_VLP, WAKEN, + SPMI_P_TRIG_FLAG, SRCLKENAI1, RES7), + PIN(25, DSI_LCM_RST, 0, 0, 0x01, 0, + LCM_RST, DP_TX_HPD, CMFLASH3, MD32_0_GPIO0, + USB_DRVVBUS_2P, RES6, RES7), + PIN(26, DSI_DSI_TE, 0, 0, 0x01, 0, + DSI_TE, EDP_TX_HPD, CMVREF3, MD32_1_GPIO0, + USB_DRVVBUS_3P, RES6, RES7), + PIN(27, DP_TX_HPD, 0, 0, 0x01, 0, + DP_TX_HPD, mbistreaden_trigger, MD32_0_GPIO0, TP_UCTS1_VCORE, + CMVREF4, EXTIF0_ACT, ANT_SEL0), + PIN(28, EDP_TX_HPD, 0, 0, 0x01, 0, + EDP_TX_HPD, mbistwriteen_trigger, MD32_1_GPIO0, TP_URTS1_VCORE, + RES5, EXTIF0_PRI, ANT_SEL1), + PIN(29, DISP_PWM0, 0, 0, 0x01, 0, + DISP_PWM0, MD32_1_TXD, SSPM_UTXD_AO_VCORE, RES4, + USB_DRVVBUS_4P, RES6, RES7), + PIN(30, DISP_PWM1, 0, 0, 0x01, 0, + DISP_PWM1, MD32_1_RXD, SSPM_URXD_AO_VCORE, RES4, + PMSR_SMAP, EXTIF0_GNT_B, ANT_SEL2), + PIN(31, UART0_TXD, 0, 0, 0x01, 0, + UTXD0, MD32_0_TXD, RES3, RES4, + RES5, RES6, RES7), + PIN(32, UART0_RXD, 0, 0, 0x01, 0, + URXD0, MD32_0_RXD, RES3, RES4, + RES5, RES6, RES7), + PIN(33, UART1_TXD, 0, 0, 0x01, 0, + UTXD1, VADSP_UTXD0, TP_UTXD1_VLP, MD32_1_TXD, + CONN_BGF_UART0_TXD, CONN_WIFI_TXD, RES7), + PIN(34, UART1_RXD, 0, 0, 0x01, 0, + URXD1, VADSP_URXD0, TP_URXD1_VLP, MD32_1_RXD, + CONN_BGF_UART0_RXD, RES6, RES7), + PIN(35, UART2_TXD, 0, 0, 0x01, 0, + UTXD2, UCTS1, TP_UCTS1_VLP, SSPM_UTXD_AO_VLP, + VADSP_UTXD0, CONN_BT_TXD, RES7), + PIN(36, UART2_RXD, 0, 0, 0x01, 0, + URXD2, URTS1, TP_URTS1_VLP, SSPM_URXD_AO_VLP, + VADSP_URXD0, RES6, RES7), + PIN(37, UART3_TXD, 0, 0, 0x01, 0, + UTXD3, UCTS0, TP_UTXD1_VCORE, SSPM_UTXD_AO_VCORE, + RES5, MD32_0_TXD, CONN_BGF_UART0_TXD), + PIN(38, UART3_RXD, 0, 0, 0x01, 0, + URXD3, URTS0, TP_URXD1_VCORE, SSPM_URXD_AO_VCORE, + RES5, MD32_0_RXD, CONN_BGF_UART0_RXD), + PIN(39, JTMS, 0, 0, 0x01, 0, + JTMS_SEL1, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(40, JTCK, 0, 0, 0x01, 0, + JTCK_SEL1, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(41, JTDI, 0, 0, 0x01, 0, + JTDI_SEL1, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(42, JTDO, 0, 0, 0x01, 0, + JTDO_SEL1, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(43, JTRST, 0, 0, 0x01, 0, + JTRSTn_SEL1, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(44, KPCOL0, 0, 0, 0x01, 0, + KPCOL0, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(45, KPCOL1, 0, 0, 0x01, 0, + KPCOL1, TP_GPIO0_AO, SRCLKENAI1, RES4, + RES5, RES6, DBG_MON_A31), + PIN(46, KPROW0, 0, 0, 0x01, 0, + KPROW0, TP_GPIO1_AO, RES3, RES4, + RES5, RES6, RES7), + PIN(47, KPROW1, 0, 0, 0x01, 0, + KPROW1, TP_GPIO2_AO, SRCLKENAI0, RES4, + RES5, RES6, DBG_MON_A32), + PIN(48, PCIE_WAKE_N, 0, 0, 0x01, 0, + WAKEN, TP_GPIO3_AO, SPMI_P_TRIG_FLAG, RES4, + RES5, RES6, RES7), + PIN(49, PCIE_PERESET_N, 0, 0, 0x01, 0, + PERSTN, MD32_0_GPIO0, UFS_MPHY_SCL, RES4, + RES5, RES6, ANT_SEL3), + PIN(50, PCIE_CLKREQ_N, 0, 0, 0x01, 0, + CLKREQN, MD32_1_GPIO0, UFS_MPHY_SDA, RES4, + RES5, RES6, ANT_SEL4), + PIN(51, SCP_SCL0, 0, 0, 0x01, 0, + SCP_SCL0, SCL0, RES3, RES4, + RES5, RES6, RES7), + PIN(52, SCP_SDA0, 0, 0, 0x01, 0, + SCP_SDA0, SDA0, RES3, RES4, + RES5, RES6, RES7), + PIN(53, SCP_SCL1, 0, 0, 0x01, 0, + SCP_SCL1, SCL1, RES3, RES4, + RES5, RES6, RES7), + PIN(54, SCP_SDA1, 0, 0, 0x01, 0, + SCP_SDA1, SDA1, RES3, RES4, + RES5, RES6, RES7), + PIN(55, SCL2, 0, 0, 0x01, 0, + SCL2, UFS_MPHY_SCL, SSUSB_U2SIF_SCL, RES4, + RES5, RES6, RES7), + PIN(56, SDA2, 0, 0, 0x01, 0, + SDA2, UFS_MPHY_SDA, SSUSB_U2SIF_SDA, RES4, + RES5, RES6, RES7), + PIN(57, SCL3, 0, 0, 0x01, 0, + SCL3, PCIE_PHY_I2C_SCL, SSUSB_U2SIF_SCL_1P, RES4, + RES5, RES6, RES7), + PIN(58, SDA3, 0, 0, 0x01, 0, + SDA3, PCIE_PHY_I2C_SDA, SSUSB_U2SIF_SDA_1P, RES4, + RES5, RES6, RES7), + PIN(59, SCL4, 0, 0, 0x01, 0, + SCL4, SSUSB_U3PHY_I2C_SCL, RES3, RES4, + RES5, RES6, RES7), + PIN(60, SDA4, 0, 0, 0x01, 0, + SDA4, SSUSB_U3PHY_I2C_SDA, RES3, RES4, + RES5, RES6, RES7), + PIN(61, SCL5, 0, 0, 0x01, 0, + SCL5, SSPXTP_U3PHY_I2C_SCL, RES3, RES4, + RES5, RES6, RES7), + PIN(62, SDA5, 0, 0, 0x01, 0, + SDA5, SSPXTP_U3PHY_I2C_SDA, RES3, RES4, + RES5, RES6, RES7), + PIN(63, SCL6, 0, 0, 0x01, 0, + SCL6, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(64, SDA6, 0, 0, 0x01, 0, + SDA6, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(65, SCL7, 0, 0, 0x01, 0, + SCL7, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(66, SDA7, 0, 0, 0x01, 0, + SDA7, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(67, SCL8, 0, 0, 0x01, 0, + SCL8, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(68, SDA8, 0, 0, 0x01, 0, + SDA8, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(69, SPIM0_CSB, 0, 0, 0x01, 0, + SPIM0_CSB, SCP_SPI0_CS, SPM_JTAG_TMS_VCORE, VADSP_JTAG0_TMS, + SPM_JTAG_TMS, SSPM_JTAG_TMS_VLP, SCP_JTAG0_TMS_VLP), + PIN(70, SPIM0_CLK, 0, 0, 0x01, 0, + SPIM0_CLK, SCP_SPI0_CK, SPM_JTAG_TCK_VCORE, VADSP_JTAG0_TCK, + SPM_JTAG_TCK, SSPM_JTAG_TCK_VLP, SCP_JTAG0_TCK_VLP), + PIN(71, SPIM0_MOSI, 0, 0, 0x01, 0, + SPIM0_MO, SCP_SPI0_MO, SPM_JTAG_TDI_VCORE, VADSP_JTAG0_TDI, + SPM_JTAG_TDI, SSPM_JTAG_TDI_VLP, SCP_JTAG0_TDI_VLP), + PIN(72, SPIM0_MISO, 0, 0, 0x01, 0, + SPIM0_MI, SCP_SPI0_MI, SPM_JTAG_TDO_VCORE, VADSP_JTAG0_TDO, + SPM_JTAG_TDO, SSPM_JTAG_TDO_VLP, SCP_JTAG0_TDO_VLP), + PIN(73, SPIM1_CSB, 0, 0, 0x01, 0, + SPIM1_CSB, SCP_SPI1_CS, SPM_JTAG_TRSTN_VCORE, VADSP_JTAG0_TRSTN, + SPM_JTAG_TRSTN, SSPM_JTAG_TRSTN_VLP, SCP_JTAG0_TRSTN_VLP), + PIN(74, SPIM1_CLK, 0, 0, 0x01, 0, + SPIM1_CLK, SCP_SPI1_CK, RES3, RES4, + RES5, RES6, RES7), + PIN(75, SPIM1_MOSI, 0, 0, 0x01, 0, + SPIM1_MO, SCP_SPI1_MO, RES3, RES4, + RES5, RES6, RES7), + PIN(76, SPIM1_MISO, 0, 0, 0x01, 0, + SPIM1_MI, SCP_SPI1_MI, RES3, RES4, + RES5, RES6, RES7), + PIN(77, SPIM2_CSB, 0, 0, 0x01, 0, + SPIM2_CSB, PCM0_SYNC, SSUSB_U2SIF_SCL, RES4, + RES5, RES6, DBG_MON_A27), + PIN(78, SPIM2_CLK, 0, 0, 0x01, 0, + SPIM2_CLK, PCM0_CLK, SSUSB_U2SIF_SDA, RES4, + RES5, RES6, DBG_MON_A28), + PIN(79, SPIM2_MOSI, 0, 0, 0x01, 0, + SPIM2_MO, PCM0_DO, SSUSB_U2SIF_SCL_1P, RES4, + RES5, RES6, DBG_MON_A29), + PIN(80, SPIM2_MISO, 0, 0, 0x01, 0, + SPIM2_MI, PCM0_DI, SSUSB_U2SIF_SDA_1P, RES4, + RES5, RES6, DBG_MON_A30), + PIN(81, USB0_IDDIG, 0, 0, 0x01, 0, + IDDIG, RES2, RES3, RES4, + RES5, RES6, DBG_MON_B32), + PIN(82, USB0_DRV_VBUS, 0, 0, 0x01, 0, + USB_DRVVBUS, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(83, USB0_VBUS_VALID, 0, 0, 0x01, 0, + VBUSVALID, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(84, USB1_DRV_VBUS, 0, 0, 0x01, 0, + USB_DRVVBUS_1P, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A16), + PIN(85, USB2_DRV_VBUS, 0, 0, 0x01, 0, + USB_DRVVBUS_2P, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A17), + PIN(86, USB3_DRV_VBUS, 0, 0, 0x01, 0, + USB_DRVVBUS_3P, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A18), + PIN(87, USB4_DRV_VBUS, 0, 0, 0x01, 0, + USB_DRVVBUS_4P, RES2, RES3, RES4, + RES5, CMVREF4, DBG_MON_A19), + PIN(88, PWRAP_SPI_CSN, 0, 0, 0x01, 0, + PWRAP_SPI0_CSN, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(89, PWRAP_SPI_CK, 0, 0, 0x01, 0, + PWRAP_SPI0_CK, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(90, PWRAP_SPI_MO, 0, 0, 0x01, 0, + PWRAP_SPI0_MO, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(91, PWRAP_SPI_MI, 0, 0, 0x01, 0, + PWRAP_SPI0_MI, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(92, PMIC_SRCLKENA0, 0, 0, 0x01, 0, + SRCLKENA0, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(93, PMIC_SRCLKENA1, 0, 0, 0x01, 0, + SRCLKENA1, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(94, SCP_VREQ_VAO, 0, 0, 0x01, 0, + SCP_VREQ_VAO, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(95, PMIC_RTC32K_CK, 0, 0, 0x01, 0, + RTC32K_CK, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(96, PMIC_WATCHDOG, 0, 0, 0x01, 0, + WATCHDOG, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(97, AUD_CLK_MOSI, 0, 0, 0x01, 0, + AUD_CLK_MOSI, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(98, AUD_SYNC_MOSI, 0, 0, 0x01, 0, + AUD_SYNC_MOSI, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(99, AUD_DAT_MOSI0, 0, 0, 0x01, 0, + AUD_DAT_MOSI0, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(100, AUD_DAT_MOSI1, 0, 0, 0x01, 0, + AUD_DAT_MOSI1, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(101, AUD_DAT_MISO0, 0, 0, 0x01, 0, + AUD_DAT_MISO0, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(102, AUD_DAT_MISO1, 0, 0, 0x01, 0, + AUD_DAT_MISO1, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(103, I2SIN0_MCK, 0, 0, 0x01, 0, + I2SIN0_MCK, SPIM3_B_CSB, APU_JTAG_TMS, SCP_JTAG0_TMS_VCORE, + CONN_WF_MCU_TMS, SSPM_JTAG_TMS_VCORE, IPU_JTAG_TMS), + PIN(104, I2SIN0_BCK, 0, 0, 0x01, 0, + I2SIN0_BCK, SPIM3_B_CLK, APU_JTAG_TCK, SCP_JTAG0_TCK_VCORE, + CONN_WF_MCU_TCK, SSPM_JTAG_TCK_VCORE, IPU_JTAG_TCK), + PIN(105, I2SIN0_LRCK, 0, 0, 0x01, 0, + I2SIN0_LRCK, SPIM3_B_MO, APU_JTAG_TDI, SCP_JTAG0_TDI_VCORE, + CONN_WF_MCU_TDI, SSPM_JTAG_TDI_VCORE, IPU_JTAG_TDI), + PIN(106, I2SIN0_DI, 0, 0, 0x01, 0, + I2SIN0_DI, SPIM3_B_MI, APU_JTAG_TDO, SCP_JTAG0_TDO_VCORE, + CONN_WF_MCU_TDO, SSPM_JTAG_TDO_VCORE, IPU_JTAG_TDO), + PIN(107, I2SOUT0_MCK, 0, 0, 0x01, 0, + I2SOUT0_MCK, SPIM4_B_CSB, APU_JTAG_TRST, SCP_JTAG0_TRSTN_VCORE, + CONN_WF_MCU_TRST_B, SSPM_JTAG_TRSTN_VCORE, IPU_JTAG_TRST), + PIN(108, I2SOUT0_BCK, 0, 0, 0x01, 0, + I2SOUT0_BCK, SPIM4_B_CLK, EXTIF0_ACT, SPM_JTAG_TMS_VCORE, + RES5, CLKM2, DBG_MON_A20), + PIN(109, I2SOUT0_LRCK, 0, 0, 0x01, 0, + I2SOUT0_LRCK, SPIM4_B_MO, EXTIF0_PRI, SPM_JTAG_TCK_VCORE, + RES5, CLKM3, DBG_MON_A21), + PIN(110, I2SOUT0_DO, 0, 0, 0x01, 0, + I2SOUT0_DO, SPIM4_B_MI, EXTIF0_GNT_B, SPM_JTAG_TDI_VCORE, + RES5, RES6, DBG_MON_A22), + PIN(111, DMIC0_CLK, 0, 0, 0x01, 0, + DMIC0_CLK, I2SIN1_MCK, I2SOUT1_MCK, SPM_JTAG_TDO_VCORE, + RES5, CONN_MIPI0_SDATA, DBG_MON_A23), + PIN(112, DMIC0_DAT0, 0, 0, 0x01, 0, + DMIC0_DAT0, I2SIN1_BCK, I2SOUT1_BCK, SPM_JTAG_TRSTN_VCORE, + RES5, CONN_MIPI0_SCLK, DBG_MON_A24), + PIN(113, DMIC1_CLK, 0, 0, 0x01, 0, + DMIC1_CLK, I2SIN1_LRCK, I2SOUT1_LRCK, PMSR_SMAP, + RES5, CONN_MIPI1_SDATA, DBG_MON_A25), + PIN(114, DMIC1_DAT0, 0, 0, 0x01, 0, + DMIC1_DAT0, I2SIN1_DI, I2SOUT1_DO, RES4, + RES5, CONN_MIPI1_SCLK, DBG_MON_A26), + PIN(115, PCM_CLK, 0, 0, 0x01, 0, + PCM0_CLK, USB_DRVVBUS_1P, PCIE_PHY_I2C_SCL, SSUSB_U3PHY_I2C_SCL, + RES5, CMFLASH0, EXTIF0_ACT), + PIN(116, PCM_SYNC, 0, 0, 0x01, 0, + PCM0_SYNC, USB_DRVVBUS_2P, PCIE_PHY_I2C_SDA, SSUSB_U3PHY_I2C_SDA, + RES5, CMFLASH1, EXTIF0_PRI), + PIN(117, PCM_DI, 0, 0, 0x01, 0, + PCM0_DI, USB_DRVVBUS_3P, DP_TX_HPD, SSPXTP_U3PHY_I2C_SCL, + RES5, CMVREF0, EXTIF0_GNT_B), + PIN(118, PCM_DO, 0, 0, 0x01, 0, + PCM0_DO, USB_DRVVBUS_4P, EDP_TX_HPD, SSPXTP_U3PHY_I2C_SDA, + RES5, CMVREF1, RES7), + PIN(119, GBE_TXD3, 0, 0, 0x01, 0, + GBE_TXD3, DMIC0_CLK, LVTS_FOUT, CONN_BGF_MCU_TMS, + UDI_TMS, ANT_SEL5, DBG_MON_B0), + PIN(120, GBE_TXD2, 0, 0, 0x01, 0, + GBE_TXD2, DMIC0_DAT0, LVTS_SDO, CONN_BGF_MCU_TCK, + UDI_TCK, ANT_SEL6, DBG_MON_B1), + PIN(121, GBE_TXD1, 0, 0, 0x01, 0, + GBE_TXD1, DMIC0_DAT1, LVTS_26M, CONN_BGF_MCU_TDI, + UDI_TDI, ANT_SEL7, DBG_MON_B2), + PIN(122, GBE_TXD0, 0, 0, 0x01, 0, + GBE_TXD0, DMIC1_CLK, LVTS_SCF, CONN_BGF_MCU_TDO, + UDI_TDO, ANT_SEL8, DBG_MON_B3), + PIN(123, GBE_RXD3, 0, 0, 0x01, 0, + GBE_RXD3, DMIC1_DAT0, LVTS_SCK, CONN_BGF_MCU_TRST_B, + UDI_NTRST, ANT_SEL9, DBG_MON_B4), + PIN(124, GBE_RXD2, 0, 0, 0x01, 0, + GBE_RXD2, DMIC1_DAT1, LVTS_SDI, CONN_WF_MCU_TMS, + SCP_JTAG0_TMS_VCORE, ANT_SEL10, DBG_MON_B5), + PIN(125, GBE_RXD1, 0, 0, 0x01, 0, + GBE_RXD1, CLKM2, RES3, CONN_WF_MCU_TCK, + SCP_JTAG0_TCK_VCORE, ANT_SEL11, DBG_MON_B6), + PIN(126, GBE_RXD0, 0, 0, 0x01, 0, + GBE_RXD0, CLKM3, RES3, CONN_WF_MCU_TDI, + SCP_JTAG0_TDI_VCORE, ANT_SEL12, DBG_MON_B7), + PIN(127, GBE_TXC, 0, 0, 0x01, 0, + GBE_TXC, I2SIN1_MCK, RES3, CONN_WF_MCU_TDO, + SCP_JTAG0_TDO_VCORE, ANT_SEL13, DBG_MON_B8), + PIN(128, GBE_RXC, 0, 0, 0x01, 0, + GBE_RXC, I2SIN1_BCK, RES3, CONN_WF_MCU_TRST_B, + SCP_JTAG0_TRSTN_VCORE, ANT_SEL14, DBG_MON_B9), + PIN(129, GBE_RXDV, 0, 0, 0x01, 0, + GBE_RXDV, I2SIN1_LRCK, RES3, CONN_BGF_MCU_AICE_TMSC, + IPU_JTAG_TMS, ANT_SEL15, DBG_MON_B10), + PIN(130, GBE_TXEN, 0, 0, 0x01, 0, + GBE_TXEN, I2SIN1_DI, RES3, CONN_BGF_MCU_AICE_TCKC, + IPU_JTAG_TCK, ANT_SEL16, DBG_MON_B11), + PIN(131, GBE_MDC, 0, 0, 0x01, 0, + GBE_MDC, CLKM0, mbistreaden_trigger, CONN_BGF_UART0_TXD, + IPU_JTAG_TDI, ANT_SEL17, DBG_MON_B12), + PIN(132, GBE_MDIO, 0, 0, 0x01, 0, + GBE_MDIO, CLKM1, mbistwriteen_trigger, CONN_BGF_UART0_RXD, + IPU_JTAG_TDO, ANT_SEL18, DBG_MON_B13), + PIN(133, GBE_TXER, 0, 0, 0x01, 0, + GBE_TXER, GBE_AUX_PPS2, RES3, CONN_BT_TXD, + IPU_JTAG_TRST, ANT_SEL19, DBG_MON_B14), + PIN(134, GBE_RXER, 0, 0, 0x01, 0, + GBE_RXER, GBE_AUX_PPS3, MCUPM_JTAG_TMS, CONN_WF_MCU_AICE_TMSC, + APU_JTAG_TMS, ANT_SEL20, DBG_MON_B15), + PIN(135, GBE_COL, 0, 0, 0x01, 0, + GBE_COL, I2SOUT1_MCK, MCUPM_JTAG_TCK, CONN_WF_MCU_AICE_TCKC, + APU_JTAG_TCK, ANT_SEL21, DBG_MON_B16), + PIN(136, GBE_INTR, 0, 0, 0x01, 0, + GBE_INTR, I2SOUT1_BCK, MCUPM_JTAG_TDI, CONN_WIFI_TXD, + APU_JTAG_TDI, PWM_0, DBG_MON_B17), + PIN(137, GBE_AUX_PPS0, 0, 0, 0x01, 0, + GBE_AUX_PPS0, I2SOUT1_LRCK, MCUPM_JTAG_TDO, DP_TX_HPD, + APU_JTAG_TDO, PWM_1, DBG_MON_B18), + PIN(138, GBE_AUX_PPS1, 0, 0, 0x01, 0, + GBE_AUX_PPS1, I2SOUT1_DO, MCUPM_JTAG_TRSTN, EDP_TX_HPD, + APU_JTAG_TRST, PWM_2, DBG_MON_B19), + PIN(139, CONN_TOP_CLK, 0, 0, 0x01, 0, + CONN_TOP_CLK, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(140, CONN_TOP_DATA, 0, 0, 0x01, 0, + CONN_TOP_DATA, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(141, CONN_BT_CLK, 0, 0, 0x01, 0, + CONN_BT_CLK, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(142, CONN_BT_DATA, 0, 0, 0x01, 0, + CONN_BT_DATA, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(143, CONN_HRST_B, 0, 0, 0x01, 0, + CONN_HRST_B, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(144, CONN_WB_PTA, 0, 0, 0x01, 0, + CONN_WB_PTA, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(145, CONN_WF_CTRL0, 0, 0, 0x01, 0, + CONN_WF_CTRL0, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(146, CONN_WF_CTRL1, 0, 0, 0x01, 0, + CONN_WF_CTRL1, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(147, CONN_WF_CTRL2, 0, 0, 0x01, 0, + CONN_WF_CTRL2, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(148, CONN_WF_CTRL3, 0, 0, 0x01, 0, + CONN_WF_CTRL3, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(149, CONN_WF_CTRL4, 0, 0, 0x01, 0, + CONN_WF_CTRL4, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(150, SPINOR_CK, 0, 0, 0x01, 0, + SPINOR_CK, DMIC0_CLK, DP_TX_HPD, PWM_0, + CONN_BPI_BUS17_ANT0, LVTS_FOUT, DBG_MON_B26), + PIN(151, SPINOR_CS, 0, 0, 0x01, 0, + SPINOR_CS, DMIC0_DAT0, EDP_TX_HPD, PWM_1, + CONN_BPI_BUS18_ANT1, LVTS_SDO, DBG_MON_B27), + PIN(152, SPINOR_IO0, 0, 0, 0x01, 0, + SPINOR_IO0, DMIC0_DAT1, UTXD2, USB_DRVVBUS_1P, + CONN_BPI_BUS19_ANT2, LVTS_26M, DBG_MON_B28), + PIN(153, SPINOR_IO1, 0, 0, 0x01, 0, + SPINOR_IO1, DMIC1_CLK, UCTS2, USB_DRVVBUS_2P, + CONN_BPI_BUS20_ANT3, LVTS_SCF, DBG_MON_B29), + PIN(154, SPINOR_IO2, 0, 0, 0x01, 0, + SPINOR_IO2, DMIC1_DAT0, URTS2, USB_DRVVBUS_3P, + CONN_BPI_BUS21_ANT4, LVTS_SCK, DBG_MON_B30), + PIN(155, SPINOR_IO3, 0, 0, 0x01, 0, + SPINOR_IO3, DMIC1_DAT1, URXD2, USB_DRVVBUS_4P, + DISP_PWM1, LVTS_SDI, DBG_MON_B31), + PIN(156, EMMC_DAT7, 0, 0, 0x01, 0, + MSDC0_DAT7, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(157, EMMC_DAT6, 0, 0, 0x01, 0, + MSDC0_DAT6, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(158, EMMC_DAT5, 0, 0, 0x01, 0, + MSDC0_DAT5, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(159, EMMC_DAT4, 0, 0, 0x01, 0, + MSDC0_DAT4, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(160, EMMC_RSTB, 0, 0, 0x01, 0, + MSDC0_RSTB, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(161, EMMC_CMD, 0, 0, 0x01, 0, + MSDC0_CMD, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(162, EMMC_CLK, 0, 0, 0x01, 0, + MSDC0_CLK, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(163, EMMC_DAT3, 0, 0, 0x01, 0, + MSDC0_DAT3, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(164, EMMC_DAT2, 0, 0, 0x01, 0, + MSDC0_DAT2, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(165, EMMC_DAT1, 0, 0, 0x01, 0, + MSDC0_DAT1, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(166, EMMC_DAT0, 0, 0, 0x01, 0, + MSDC0_DAT0, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(167, EMMC_DSL, 0, 0, 0x01, 0, + MSDC0_DSL, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(168, MSDC1_CMD, 0, 0, 0x01, 0, + MSDC1_CMD, CONN_WF_MCU_AICE_TMSC, UCTS1, UDI_TMS, + SSPM_JTAG_TMS_VCORE, MCUPM_JTAG_TMS, CONN_BGF_MCU_TMS), + PIN(169, MSDC1_CLK, 0, 0, 0x01, 0, + MSDC1_CLK, CONN_WF_MCU_AICE_TCKC, URTS1, UDI_TCK, + SSPM_JTAG_TCK_VCORE, MCUPM_JTAG_TCK, CONN_BGF_MCU_TCK), + PIN(170, MSDC1_DAT0, 0, 0, 0x01, 0, + MSDC1_DAT0, SPIM5_B_CSB, UCTS2, UDI_TDI, + SSPM_JTAG_TDI_VCORE, MCUPM_JTAG_TDI, CONN_BGF_MCU_TDI), + PIN(171, MSDC1_DAT1, 0, 0, 0x01, 0, + MSDC1_DAT1, SPIM5_B_CLK, URTS2, UDI_TDO, + SSPM_JTAG_TDO_VCORE, MCUPM_JTAG_TDO, CONN_BGF_MCU_TDO), + PIN(172, MSDC1_DAT2, 0, 0, 0x01, 0, + MSDC1_DAT2, SPIM5_B_MO, UCTS3, UDI_NTRST, + SSPM_JTAG_TRSTN_VCORE, MCUPM_JTAG_TRSTN, CONN_BGF_MCU_TRST_B), + PIN(173, MSDC1_DAT3, 0, 0, 0x01, 0, + MSDC1_DAT3, SPIM5_B_MI, URTS3, CLKM0, + PWM_2, RES6, RES7), + PIN(174, MSDC2_CMD, 0, 0, 0x01, 0, + MSDC2_CMD, CONN_BGF_MCU_AICE_TMSC, UTXD1, VADSP_JTAG0_TMS, + SSPM_JTAG_TMS_VLP, SPM_JTAG_TMS, SCP_JTAG0_TMS_VLP), + PIN(175, MSDC2_CLK, 0, 0, 0x01, 0, + MSDC2_CLK, CONN_BGF_MCU_AICE_TCKC, URXD1, VADSP_JTAG0_TCK, + SSPM_JTAG_TCK_VLP, SPM_JTAG_TCK, SCP_JTAG0_TCK_VLP), + PIN(176, MSDC2_DAT0, 0, 0, 0x01, 0, + MSDC2_DAT0, SRCLKENAI0, UTXD2, VADSP_JTAG0_TDI, + SSPM_JTAG_TDI_VLP, SPM_JTAG_TDI, SCP_JTAG0_TDI_VLP), + PIN(177, MSDC2_DAT1, 0, 0, 0x01, 0, + MSDC2_DAT1, SRCLKENAI1, URXD2, VADSP_JTAG0_TDO, + SSPM_JTAG_TDO_VLP, SPM_JTAG_TDO, SCP_JTAG0_TDO_VLP), + PIN(178, MSDC2_DAT2, 0, 0, 0x01, 0, + MSDC2_DAT2, RES2, UTXD3, VADSP_JTAG0_TRSTN, + SSPM_JTAG_TRSTN_VLP, SPM_JTAG_TRSTN, SCP_JTAG0_TRSTN_VLP), + PIN(179, MSDC2_DAT3, 0, 0, 0x01, 0, + MSDC2_DAT3, RES2, URXD3, CLKM1, + PWM_vlp, RES6, TP_GPIO7_AO), + PIN(180, SPMI_P_SCL, 0, 0, 0x01, 0, + SPMI_P_SCL, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(181, SPMI_P_SDA, 0, 0, 0x01, 0, + SPMI_P_SDA, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(182, EMI_RESETB, 0, 0, 0x01, 0, + DDR_PAD_RRESETB, RES2, RES3, RES4, + RES5, RES6, RES7), +}; + +static struct gpio_regs *const mtk_gpio = (void *)GPIO_BASE; + +#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85667?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia87fe0975add95fcfad16d55586559c7f912a624 Gerrit-Change-Number: 85667 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8189: Initialize watchdog
by Yidi Lin (Code Review) 21 Dec '24

21 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85678?usp=email ) Change subject: soc/mediatek/mt8189: Initialize watchdog ...................................................................... soc/mediatek/mt8189: Initialize watchdog Add watchdog support for MT8189. BUG=b:379008996 BRANCH=none TEST=build pass and WDT makes DUT reboot when MTK_WDT_MODE_ENABLE is set. Change-Id: I496fce91e52393db31fd1fb5a1c68d91b2ed073e Signed-off-by: Vince Liu <vince-wl.liu(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85678 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8189/Makefile.mk M src/soc/mediatek/mt8189/bootblock.c A src/soc/mediatek/mt8189/include/soc/wdt.h A src/soc/mediatek/mt8189/wdt.c 4 files changed, 39 insertions(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk index 9b09628..e997ec1 100644 --- a/src/soc/mediatek/mt8189/Makefile.mk +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -8,6 +8,7 @@ bootblock-y += bootblock.c bootblock-y += ../common/mmu_operations.c +bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c romstage-y += ../common/cbmem.c romstage-y += emi.c diff --git a/src/soc/mediatek/mt8189/bootblock.c b/src/soc/mediatek/mt8189/bootblock.c index 89cd22d..ed78d65 100644 --- a/src/soc/mediatek/mt8189/bootblock.c +++ b/src/soc/mediatek/mt8189/bootblock.c @@ -2,8 +2,10 @@ #include <bootblock_common.h> #include <soc/mmu_operations.h> +#include <soc/wdt.h> void bootblock_soc_init(void) { mtk_mmu_init(); + mtk_wdt_init(); } diff --git a/src/soc/mediatek/mt8189/include/soc/wdt.h b/src/soc/mediatek/mt8189/include/soc/wdt.h new file mode 100644 index 0000000..f6e808c --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/wdt.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 8.2 + */ + +#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_WDT_H__ +#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_WDT_H__ + +#include <soc/wdt_common.h> + +#define MTK_WDT_SPM_THERMAL_VAL 1 + +DEFINE_BIT(MTK_WDT_SPM_THERMAL_EN, 0) +DEFINE_BIT(MTK_WDT_THERMAL_EN, 18) +DEFINE_BIT(MTK_WDT_THERMAL_IRQ, 18) + +#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_WDT_H__ */ diff --git a/src/soc/mediatek/mt8189/wdt.c b/src/soc/mediatek/mt8189/wdt.c new file mode 100644 index 0000000..ca6518b --- /dev/null +++ b/src/soc/mediatek/mt8189/wdt.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 8.2 + */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/wdt.h> + +#define MTK_WDT_CLR_STATUS 0x230001FF + +void mtk_wdt_clr_status(void) +{ + write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85678?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I496fce91e52393db31fd1fb5a1c68d91b2ed073e Gerrit-Change-Number: 85678 Gerrit-PatchSet: 4 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/mediatek: Add support for MediaTek firmware support package
by Yidi Lin (Code Review) 21 Dec '24

21 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85665?usp=email ) Change subject: soc/mediatek: Add support for MediaTek firmware support package ...................................................................... soc/mediatek: Add support for MediaTek firmware support package Starting from MT8196, MediaTek platform introudces a new blob named MediaTek firmware support package (mtk-fsp). The features of mtk-fsp include but not limit to, - Security settings, e.g: Device Access Proctection Control, Security Memory Protection Unit. - Initialization for advanced CPU frequency control. This patch implements APIs for 1) Exchanging data between coreboot and mtk-fsp. 2) Loading and running the mtk-fsp blob at a specific bootstage. BUG=b:373797027 TEST=emerge-rauru coreboot; Run mock blob and return from mock blob. Change-Id: Idef3518f9763fe5f74adb459c137db164563e483 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85665 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/mediatek/common/include/soc/mtk_fsp.h A src/soc/mediatek/common/include/soc/mtk_fsp_common.h A src/soc/mediatek/common/mtk_fsp.c M src/soc/mediatek/mt8196/Makefile.mk 4 files changed, 184 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/mtk_fsp.h b/src/soc/mediatek/common/include/soc/mtk_fsp.h new file mode 100644 index 0000000..2e9095f --- /dev/null +++ b/src/soc/mediatek/common/include/soc/mtk_fsp.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_COMMON_INCLUDE_SOC_MTK_FSP_H__ +#define __SOC_MEDIATEK_COMMON_INCLUDE_SOC_MTK_FSP_H__ + +#include <soc/mtk_fsp_common.h> + +void mtk_fsp_init(enum fsp_phase phase); +enum cb_err mtk_fsp_add_param(enum fsp_param_type type, size_t param_size, + void *param); +enum cb_err mtk_fsp_load_and_run(void); + +#endif /* __SOC_MEDIATEK_COMMON_INCLUDE_SOC_MTK_FSP_H__ */ diff --git a/src/soc/mediatek/common/include/soc/mtk_fsp_common.h b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h new file mode 100644 index 0000000..ea3d46f --- /dev/null +++ b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __COMMON_INCLUDE_MTK_FSP_COMMON_H__ +#define __COMMON_INCLUDE_MTK_FSP_COMMON_H__ + +#include <stdarg.h> +#include <stdint.h> + +#define INTF_MAJOR_VER 1 +#define INTF_MINOR_VER 0 + +enum fsp_status { + FSP_STATUS_SUCCESS = 0, + FSP_STATUS_INVALID_VERSION, +}; + +enum fsp_phase { + ROMSTAGE_INIT = 0x30, + RAMSTAGE_MAINBOARD_INIT = 0x40, + RAMSTAGE_SOC_INIT = 0x50, +}; + +enum fsp_param_io { + FSP_PARAM_IO_INVALID = 0, + FSP_PARAM_IO_IN, + FSP_PARAM_IO_OUT, + FSP_PARAM_IO_INOUT, +}; + +#define FSP_PARAM_IO_ENCODE(x) ((uint32_t)(x) << 30) + +enum fsp_param_type { + FSP_PARAM_TYPE_INVALID = 0, + /* 0x40000000+ reserved for input type params */ + FSP_PARAM_TYPE_IN = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_IN), + + /* 0x80000000+ reserved for output type params */ + FSP_PARAM_TYPE_OUT = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_OUT), + + /* 0xC0000000+ reserved for the params that support both input and output */ + FSP_PARAM_TYPE_INOUT = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_INOUT), +}; + +struct mtk_fsp_intf { + uint8_t major_version; + uint8_t minor_version; + uint16_t header_size; + uint32_t phase; /* enum fsp_phase */ + int32_t status; /* enum fsp_status */ + uint16_t entry_size; + uint8_t num_entries; + uint8_t reserved; + int (*do_vprintf)(const char *fmt, va_list args); + struct mtk_fsp_param { + uint32_t param_type; + uint32_t param_size; + void *param; + } entries[]; +}; + +#endif /* __COMMON_INCLUDE_MTK_FSP_COMMON_H__ */ diff --git a/src/soc/mediatek/common/mtk_fsp.c b/src/soc/mediatek/common/mtk_fsp.c new file mode 100644 index 0000000..bc1b5d5 --- /dev/null +++ b/src/soc/mediatek/common/mtk_fsp.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbfs.h> +#include <console/console.h> +#include <soc/mtk_fsp.h> + +#define MAX_PARAM_ENTRIES 32 +#define FSP_INTF_SIZE (sizeof(struct mtk_fsp_intf) + \ + sizeof(struct mtk_fsp_param) * MAX_PARAM_ENTRIES) + +static struct mtk_fsp_intf *intf; +static uint8_t fsp_intf_buf[FSP_INTF_SIZE] __aligned(8); + +static int vprintf_wrapper(const char *fmt, va_list args) +{ + return vprintk(BIOS_INFO, fmt, args); +} + +void mtk_fsp_init(enum fsp_phase phase) +{ + intf = (struct mtk_fsp_intf *)fsp_intf_buf; + intf->major_version = INTF_MAJOR_VER; + intf->minor_version = INTF_MINOR_VER; + intf->header_size = sizeof(struct mtk_fsp_intf); + intf->entry_size = sizeof(struct mtk_fsp_param); + intf->num_entries = 0; + intf->phase = phase; + intf->do_vprintf = vprintf_wrapper; +} + +enum cb_err mtk_fsp_add_param(enum fsp_param_type type, size_t param_size, + void *param) +{ + struct mtk_fsp_param *entry; + + if (!intf) { + printk(BIOS_ERR, "%s: intf is not initialized\n", __func__); + return CB_ERR; + } + + if (intf->num_entries == MAX_PARAM_ENTRIES) { + printk(BIOS_ERR, "%s: run out all entries\n", __func__); + return CB_ERR; + } + + entry = &intf->entries[intf->num_entries]; + + entry->param_type = type; + entry->param_size = param_size; + entry->param = param; + intf->num_entries++; + + return CB_SUCCESS; +} + +static void mtk_fsp_dump_intf(void) +{ + struct mtk_fsp_param *entry; + + if (!intf) { + printk(BIOS_ERR, "%s: intf is not initialized\n", __func__); + return; + } + + printk(BIOS_DEBUG, "%s: major version: %u, minor version: %u\n", + __func__, intf->major_version, intf->minor_version); + printk(BIOS_DEBUG, "%s: FSP phase: %u, status: %d\n", + __func__, intf->phase, intf->status); + printk(BIOS_DEBUG, "%-5s %-10s %-10s %s\n", "Param", "type", "size", "address"); + for (int i = 0; i < intf->num_entries; i++) { + entry = &intf->entries[i]; + printk(BIOS_DEBUG, "%-5u %-10u %-10u %p\n", + i, entry->param_type, entry->param_size, entry->param); + } +} + +static const char *mtk_fsp_file(void) +{ + return CONFIG_CBFS_PREFIX "/mtk_fsp_" ENV_STRING; +} + +enum cb_err mtk_fsp_load_and_run(void) +{ + struct prog fsp = PROG_INIT(PROG_REFCODE, mtk_fsp_file()); + + if (cbfs_prog_stage_load(&fsp)) { + printk(BIOS_ERR, "%s: CBFS load program failed\n", __func__); + return CB_ERR; + } + + if (!intf) { + printk(BIOS_ERR, "%s: intf is not initialized\n", __func__); + return CB_ERR; + } + + prog_set_arg(&fsp, intf); + prog_run(&fsp); + + if (intf->status != FSP_STATUS_SUCCESS) { + mtk_fsp_dump_intf(); + return CB_ERR; + } + + printk(BIOS_INFO, "%s: run %s at phase %#x done\n", + __func__, mtk_fsp_file(), intf->phase); + + return CB_SUCCESS; +} diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index a9ed31d..e09ea3a 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -34,6 +34,7 @@ romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-y += ../common/mt6363.c mt6363.c romstage-y += ../common/mt6373.c mt6373.c +romstage-y += ../common/mtk_fsp.c romstage-y += mtk_pwrsel.c romstage-y += ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif.c pmif_init.c @@ -52,6 +53,7 @@ ramstage-y += ../common/mt6363.c mt6363.c ramstage-y += ../common/mt6363_sdmadc.c ramstage-y += ../common/mt6373.c mt6373.c +ramstage-y += ../common/mtk_fsp.c ramstage-y += soc.c ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/sspm.c sspm_sram.c -- To view, visit https://review.coreboot.org/c/coreboot/+/85665?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idef3518f9763fe5f74adb459c137db164563e483 Gerrit-Change-Number: 85665 Gerrit-PatchSet: 8 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: soc/mediatek/common: Rename GPT_MHZ to TIMER_MHZ for readability
by Yidi Lin (Code Review) 21 Dec '24

21 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85681?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/common: Rename GPT_MHZ to TIMER_MHZ for readability ...................................................................... soc/mediatek/common: Rename GPT_MHZ to TIMER_MHZ for readability Update timer macro name for common. The new ICs (e.g. mt8196, mt8189) will no longer use GPT. In order to improve code readability, replace GPT_MHZ with TIMER_MHZ for existing SoCs. BUG=b:379008996 BRANCH=none TEST=Build pass, Macro name is correct. Change-Id: I02f18bfa5b5912f28e322d40cd46823a0095bbf4 Signed-off-by: Ke Zheng <ot_ke.zheng(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85681 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/timer_v1.h M src/soc/mediatek/common/include/soc/timer_v2.h M src/soc/mediatek/common/timer.c M src/soc/mediatek/mt8173/timer.c M src/soc/mediatek/mt8196/timer.c 5 files changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/timer_v1.h b/src/soc/mediatek/common/include/soc/timer_v1.h index 8d64b5d..d71d270 100644 --- a/src/soc/mediatek/common/include/soc/timer_v1.h +++ b/src/soc/mediatek/common/include/soc/timer_v1.h @@ -7,7 +7,7 @@ #include <soc/timer_common.h> #include <types.h> -#define GPT_MHZ 13 +#define TIMER_MHZ 13 struct mtk_gpt_regs { u32 reserved1[24]; diff --git a/src/soc/mediatek/common/include/soc/timer_v2.h b/src/soc/mediatek/common/include/soc/timer_v2.h index 2305928..d4f854c 100644 --- a/src/soc/mediatek/common/include/soc/timer_v2.h +++ b/src/soc/mediatek/common/include/soc/timer_v2.h @@ -7,7 +7,7 @@ #include <soc/timer_common.h> #include <types.h> -#define GPT_MHZ 13 +#define TIMER_MHZ 13 enum { TIE_0_EN = 1 << 3, diff --git a/src/soc/mediatek/common/timer.c b/src/soc/mediatek/common/timer.c index 5feed34..5412a9e 100644 --- a/src/soc/mediatek/common/timer.c +++ b/src/soc/mediatek/common/timer.c @@ -27,7 +27,7 @@ void timer_monotonic_get(struct mono_time *mt) { - mono_time_set_usecs(mt, timer_raw_value() / GPT_MHZ); + mono_time_set_usecs(mt, timer_raw_value() / TIMER_MHZ); } void init_timer(void) diff --git a/src/soc/mediatek/mt8173/timer.c b/src/soc/mediatek/mt8173/timer.c index 0a9de6b..fc71877 100644 --- a/src/soc/mediatek/mt8173/timer.c +++ b/src/soc/mediatek/mt8173/timer.c @@ -18,5 +18,5 @@ */ write32(&mt8173_mcucfg->xgpt_idx, 0); /* Set clock mode to 13Mhz and enable XGPT */ - write32(&mt8173_mcucfg->xgpt_ctl, (0x1 | ((26 / GPT_MHZ) << 8))); + write32(&mt8173_mcucfg->xgpt_ctl, (0x1 | ((26 / TIMER_MHZ) << 8))); } diff --git a/src/soc/mediatek/mt8196/timer.c b/src/soc/mediatek/mt8196/timer.c index bf3f3ce..5db5c4a 100644 --- a/src/soc/mediatek/mt8196/timer.c +++ b/src/soc/mediatek/mt8196/timer.c @@ -9,5 +9,5 @@ { timer_prepare(); - raw_write_cntfrq_el0(GPT_MHZ * MHz); + raw_write_cntfrq_el0(TIMER_MHZ * MHz); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85681?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I02f18bfa5b5912f28e322d40cd46823a0095bbf4 Gerrit-Change-Number: 85681 Gerrit-PatchSet: 3 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add SPM loader
by Yidi Lin (Code Review) 21 Dec '24

21 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85599?usp=email ) Change subject: soc/mediatek/mt8196: Add SPM loader ...................................................................... soc/mediatek/mt8196: Add SPM loader This patch adds support for loading SPM firmware from CBFS to SPM SRAM and fix the SPM register definitions. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspends. coreboot log: CBFS: Found 'spm_firmware.pm' @0xadf00 size 0x5a60 in mcache @0xfffdd3c mtk_init_mcu: Loaded (and reset) spm_firmware.pm in 3 msecs (30080 byt) TEST=build pass BUG=348147674 Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Signed-off-by: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85599 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/include/soc/pll.h M src/soc/mediatek/mt8196/include/soc/spm.h A src/soc/mediatek/mt8196/spm.c 6 files changed, 1,357 insertions(+), 169 deletions(-) Approvals: Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig index 2133dbb..c5c6bf4 100644 --- a/src/soc/mediatek/mt8196/Kconfig +++ b/src/soc/mediatek/mt8196/Kconfig @@ -45,4 +45,9 @@ help The file name of the MediaTek SSPM firmware. +config SPM_FIRMWARE + string + default "spm_firmware.pm" + help + The file name of the MediaTek SPM firmware. endif diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index b61f7d9..a9ed31d 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -53,6 +53,7 @@ ramstage-y += ../common/mt6363_sdmadc.c ramstage-y += ../common/mt6373.c mt6373.c ramstage-y += soc.c +ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/sspm.c sspm_sram.c ramstage-y += ../common/pmif_clk.c pmif_clk.c ramstage-y += ../common/pmif.c pmif_init.c @@ -69,7 +70,8 @@ mcu-firmware-files := \ $(CONFIG_DPM_DM_FIRMWARE) \ $(CONFIG_DPM_PM_FIRMWARE) \ - $(CONFIG_SSPM_FIRMWARE) + $(CONFIG_SSPM_FIRMWARE) \ + $(CONFIG_SPM_FIRMWARE) $(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \ $(eval $(fw)-file := $(MT8196_BLOB_DIR)/$(fw)) \ diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index fcb5fc8..96efa40 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -159,6 +159,7 @@ SSPM_CFG_BASE = IO_PHYS + 0x0C340000, SYSTIMER_BASE = IO_PHYS + 0x0C400000, VLP_TRACKER_BASE = IO_PHYS + 0x0C4E0000, + VLP_DEVAPC_BASE = IO_PHYS + 0x0C550A00, MMVOTE_MMSYS_CONFIG_BASE = IO_PHYS + 0x12000000, MMVOTE_MMSYS1_CONFIG_BASE = IO_PHYS + 0x12400000, MMVOTE_OVLSYS_CONFIG_BASE = IO_PHYS + 0x12800000, diff --git a/src/soc/mediatek/mt8196/include/soc/pll.h b/src/soc/mediatek/mt8196/include/soc/pll.h index 7995a65..6c4a976 100644 --- a/src/soc/mediatek/mt8196/include/soc/pll.h +++ b/src/soc/mediatek/mt8196/include/soc/pll.h @@ -136,13 +136,15 @@ u32 reserved1[1]; u32 clk_cfg_update[3]; struct mtk_clk_cfg clk_cfg[23]; - u32 reserved2[16]; + u32 reserved2[8]; + u32 clk_scp_cfg; + u32 reserved3[7]; u32 clk26cali[2]; - u32 reserved3[3]; + u32 reserved4[3]; u32 clk_misc_cfg; - u32 reserved4[10]; + u32 reserved5[10]; u32 clk_dbg_cfg; - u32 reserved5[13]; + u32 reserved6[13]; u32 clk_prot_idle_reg; u32 clk_fenc_bypass_reg[3]; u32 clk_prot_idle_all_reg[3]; @@ -152,6 +154,7 @@ }; check_member(mtk_topckgen_regs, clk_cfg_update[0], 0x0004); check_member(mtk_topckgen_regs, clk_cfg[0], 0x0010); +check_member(mtk_topckgen_regs, clk_scp_cfg, 0x01A0); check_member(mtk_topckgen_regs, clk26cali[0], 0x01C0); check_member(mtk_topckgen_regs, clk_prot_idle_all_reg[0], 0x0248); check_member(mtk_topckgen_regs, clk_prot_spm_ck_en_reg, 0x026C); diff --git a/src/soc/mediatek/mt8196/include/soc/spm.h b/src/soc/mediatek/mt8196/include/soc/spm.h index b0f1264..5e6b784 100644 --- a/src/soc/mediatek/mt8196/include/soc/spm.h +++ b/src/soc/mediatek/mt8196/include/soc/spm.h @@ -9,6 +9,8 @@ #include <soc/spm_common.h> #include <types.h> +#define INFRA_SW_CG (INFRACFG_AO_BASE + 0x60) + /* SPM READ/WRITE CFG */ #define SPM_PROJECT_CODE 0xb16 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) @@ -61,11 +63,8 @@ /* MD32PCM_CFGREG_SW_RSTN (0x10006000+0xA00) */ DEFINE_BIT(MD32PCM_CFGREG_SW_RSTN_RESET, 0) -/************************************** - * Config and Parameter - **************************************/ -#define SPM_SYSTEM_BASE_OFFSET 0x40000000 -#define POWER_ON_VAL1_DEF 0x003ffe24 +#define SPM_SYSTEM_BASE_OFFSET 0x0 +#define POWER_ON_VAL1_DEF 0x003ffe20 #define SPM_WAKEUP_EVENT_MASK_DEF 0xefffffff #define SPM_BUS_PROTECT_MASK_B_DEF 0xffffffff #define SPM_BUS_PROTECT2_MASK_B_DEF 0xffffffff @@ -81,10 +80,15 @@ #define ARMPLL_CLK_SEL_DEF 0x3ff #define SPM_SYSCLK_SETTLE 0x60fe #define SPM_INIT_DONE_US 20 +#define PCM_WDT_TIMEOUT_S (30 * 32768) +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT_S) +#define AP_WDT_TIMEOUT_SUSPEND_S 5400 +#define PCM_TIMER_SUSPEND ((AP_WDT_TIMEOUT_SUSPEND_S - 30) * 32768) +#define SPM_FLAG_ENABLE_MT8196_ES_WA BIT(24) +#define SPM_FLAG_ENABLE_MT8196_EMI_ES_WA BIT(25) +#define MT_SPM_VERSION_ES 0x0 +#define MT_SPM_VERSION_CS 0x1 -/************************************** - * Definition and Declaration - **************************************/ /* SPM_IRQ_MASK */ #define ISRM_TWAM BIT(2) #define ISRM_PCM_RETURN BIT(3) @@ -192,13 +196,32 @@ u8 vrf18_state; /* SPM_SRC_MASK_0 */ + u8 reg_apifr_mem_apsrc_req_mask_b; + u8 reg_apifr_mem_ddren_req_mask_b; + u8 reg_apifr_mem_emi_req_mask_b; + u8 reg_apifr_mem_infra_req_mask_b; + u8 reg_apifr_mem_pmic_req_mask_b; + u8 reg_apifr_mem_srcclkena_mask_b; + u8 reg_apifr_mem_vcore_req_mask_b; + u8 reg_apifr_mem_vrf18_req_mask_b; u8 reg_apu_apsrc_req_mask_b; u8 reg_apu_ddren_req_mask_b; u8 reg_apu_emi_req_mask_b; u8 reg_apu_infra_req_mask_b; u8 reg_apu_pmic_req_mask_b; u8 reg_apu_srcclkena_mask_b; + u8 reg_apu_vcore_req_mask_b; u8 reg_apu_vrf18_req_mask_b; + u8 reg_audio_apsrc_req_mask_b; + u8 reg_audio_ddren_req_mask_b; + u8 reg_audio_emi_req_mask_b; + u8 reg_audio_infra_req_mask_b; + u8 reg_audio_pmic_req_mask_b; + u8 reg_audio_srcclkena_mask_b; + u8 reg_audio_vcore_req_mask_b; + u8 reg_audio_vrf18_req_mask_b; + + /* SPM_SRC_MASK_1 */ u8 reg_audio_dsp_apsrc_req_mask_b; u8 reg_audio_dsp_ddren_req_mask_b; u8 reg_audio_dsp_emi_req_mask_b; @@ -214,33 +237,18 @@ u8 reg_cam_pmic_req_mask_b; u8 reg_cam_srcclkena_mask_b; u8 reg_cam_vrf18_req_mask_b; - - /* SPM_SRC_MASK_1 */ u32 reg_ccif_apsrc_req_mask_b; - u32 reg_ccif_emi_req_mask_b; - u8 reg_vlpcfg_rsv0_apsrc_req_mask_b; - u8 reg_vlpcfg_rsv0_ddren_req_mask_b; - u8 reg_vlpcfg_rsv0_emi_req_mask_b; - u8 reg_vlpcfg_rsv0_infra_req_mask_b; - u8 reg_vlpcfg_rsv0_pmic_req_mask_b; - u8 reg_vlpcfg_rsv0_srcclkena_mask_b; - u8 reg_vlpcfg_rsv0_vcore_req_mask_b; - u8 reg_vlpcfg_rsv0_vrf18_req_mask_b; /* SPM_SRC_MASK_2 */ + u32 reg_ccif_emi_req_mask_b; u32 reg_ccif_infra_req_mask_b; - u32 reg_ccif_pmic_req_mask_b; - u8 reg_vlpcfg_rsv1_apsrc_req_mask_b; - u8 reg_vlpcfg_rsv1_ddren_req_mask_b; - u8 reg_vlpcfg_rsv1_emi_req_mask_b; - u8 reg_vlpcfg_rsv1_infra_req_mask_b; - u8 reg_vlpcfg_rsv1_pmic_req_mask_b; - u8 reg_vlpcfg_rsv1_srcclkena_mask_b; - u8 reg_vlpcfg_rsv1_vcore_req_mask_b; - u8 reg_vlpcfg_rsv1_vrf18_req_mask_b; /* SPM_SRC_MASK_3 */ + u32 reg_ccif_pmic_req_mask_b; u32 reg_ccif_srcclkena_mask_b; + + /* SPM_SRC_MASK_4 */ + u32 reg_ccif_vcore_req_mask_b; u32 reg_ccif_vrf18_req_mask_b; u8 reg_ccu_apsrc_req_mask_b; u8 reg_ccu_ddren_req_mask_b; @@ -251,7 +259,7 @@ u8 reg_ccu_vrf18_req_mask_b; u8 reg_cg_check_apsrc_req_mask_b; - /* SPM_SRC_MASK_4 */ + /* SPM_SRC_MASK_5 */ u8 reg_cg_check_ddren_req_mask_b; u8 reg_cg_check_emi_req_mask_b; u8 reg_cg_check_infra_req_mask_b; @@ -259,6 +267,32 @@ u8 reg_cg_check_srcclkena_mask_b; u8 reg_cg_check_vcore_req_mask_b; u8 reg_cg_check_vrf18_req_mask_b; + u8 reg_cksys_apsrc_req_mask_b; + u8 reg_cksys_ddren_req_mask_b; + u8 reg_cksys_emi_req_mask_b; + u8 reg_cksys_infra_req_mask_b; + u8 reg_cksys_pmic_req_mask_b; + u8 reg_cksys_srcclkena_mask_b; + u8 reg_cksys_vcore_req_mask_b; + u8 reg_cksys_vrf18_req_mask_b; + u8 reg_cksys_1_apsrc_req_mask_b; + u8 reg_cksys_1_ddren_req_mask_b; + u8 reg_cksys_1_emi_req_mask_b; + u8 reg_cksys_1_infra_req_mask_b; + u8 reg_cksys_1_pmic_req_mask_b; + u8 reg_cksys_1_srcclkena_mask_b; + u8 reg_cksys_1_vcore_req_mask_b; + u8 reg_cksys_1_vrf18_req_mask_b; + + /* SPM_SRC_MASK_6 */ + u8 reg_cksys_2_apsrc_req_mask_b; + u8 reg_cksys_2_ddren_req_mask_b; + u8 reg_cksys_2_emi_req_mask_b; + u8 reg_cksys_2_infra_req_mask_b; + u8 reg_cksys_2_pmic_req_mask_b; + u8 reg_cksys_2_srcclkena_mask_b; + u8 reg_cksys_2_vcore_req_mask_b; + u8 reg_cksys_2_vrf18_req_mask_b; u8 reg_conn_apsrc_req_mask_b; u8 reg_conn_ddren_req_mask_b; u8 reg_conn_emi_req_mask_b; @@ -268,12 +302,23 @@ u8 reg_conn_srcclkenb_mask_b; u8 reg_conn_vcore_req_mask_b; u8 reg_conn_vrf18_req_mask_b; + u8 reg_corecfg_rsv0_apsrc_req_mask_b; + u8 reg_corecfg_rsv0_ddren_req_mask_b; + u8 reg_corecfg_rsv0_emi_req_mask_b; + u8 reg_corecfg_rsv0_infra_req_mask_b; + u8 reg_corecfg_rsv0_pmic_req_mask_b; + u8 reg_corecfg_rsv0_srcclkena_mask_b; + u8 reg_corecfg_rsv0_vcore_req_mask_b; + u8 reg_corecfg_rsv0_vrf18_req_mask_b; + + /* SPM_SRC_MASK_7 */ u8 reg_cpueb_apsrc_req_mask_b; u8 reg_cpueb_ddren_req_mask_b; u8 reg_cpueb_emi_req_mask_b; u8 reg_cpueb_infra_req_mask_b; u8 reg_cpueb_pmic_req_mask_b; u8 reg_cpueb_srcclkena_mask_b; + u8 reg_cpueb_vcore_req_mask_b; u8 reg_cpueb_vrf18_req_mask_b; u8 reg_disp0_apsrc_req_mask_b; u8 reg_disp0_ddren_req_mask_b; @@ -284,8 +329,6 @@ u8 reg_disp0_vrf18_req_mask_b; u8 reg_disp1_apsrc_req_mask_b; u8 reg_disp1_ddren_req_mask_b; - - /* SPM_SRC_MASK_5 */ u8 reg_disp1_emi_req_mask_b; u8 reg_disp1_infra_req_mask_b; u8 reg_disp1_pmic_req_mask_b; @@ -293,12 +336,12 @@ u8 reg_disp1_vrf18_req_mask_b; u8 reg_dpm_apsrc_req_mask_b; u8 reg_dpm_ddren_req_mask_b; + + /* SPM_SRC_MASK_8 */ u8 reg_dpm_emi_req_mask_b; u8 reg_dpm_infra_req_mask_b; u8 reg_dpm_pmic_req_mask_b; u8 reg_dpm_srcclkena_mask_b; - - /* SPM_SRC_MASK_6 */ u8 reg_dpm_vcore_req_mask_b; u8 reg_dpm_vrf18_req_mask_b; u8 reg_dpmaif_apsrc_req_mask_b; @@ -307,17 +350,26 @@ u8 reg_dpmaif_infra_req_mask_b; u8 reg_dpmaif_pmic_req_mask_b; u8 reg_dpmaif_srcclkena_mask_b; + u8 reg_dpmaif_vcore_req_mask_b; u8 reg_dpmaif_vrf18_req_mask_b; + + /* SPM_SRC_MASK_9 */ u8 reg_dvfsrc_level_req_mask_b; u8 reg_emisys_apsrc_req_mask_b; u8 reg_emisys_ddren_req_mask_b; u8 reg_emisys_emi_req_mask_b; + u8 reg_emisys_infra_req_mask_b; + u8 reg_emisys_pmic_req_mask_b; + u8 reg_emisys_srcclkena_mask_b; + u8 reg_emisys_vcore_req_mask_b; + u8 reg_emisys_vrf18_req_mask_b; u8 reg_gce_apsrc_req_mask_b; u8 reg_gce_ddren_req_mask_b; u8 reg_gce_emi_req_mask_b; u8 reg_gce_infra_req_mask_b; u8 reg_gce_pmic_req_mask_b; u8 reg_gce_srcclkena_mask_b; + u8 reg_gce_vcore_req_mask_b; u8 reg_gce_vrf18_req_mask_b; u8 reg_gpueb_apsrc_req_mask_b; u8 reg_gpueb_ddren_req_mask_b; @@ -325,8 +377,7 @@ u8 reg_gpueb_infra_req_mask_b; u8 reg_gpueb_pmic_req_mask_b; u8 reg_gpueb_srcclkena_mask_b; - - /* SPM_SRC_MASK_7 */ + u8 reg_gpueb_vcore_req_mask_b; u8 reg_gpueb_vrf18_req_mask_b; u8 reg_hwccf_apsrc_req_mask_b; u8 reg_hwccf_ddren_req_mask_b; @@ -335,6 +386,8 @@ u8 reg_hwccf_pmic_req_mask_b; u8 reg_hwccf_srcclkena_mask_b; u8 reg_hwccf_vcore_req_mask_b; + + /* SPM_SRC_MASK_10 */ u8 reg_hwccf_vrf18_req_mask_b; u8 reg_img_apsrc_req_mask_b; u8 reg_img_ddren_req_mask_b; @@ -347,6 +400,9 @@ u8 reg_infrasys_ddren_req_mask_b; u8 reg_infrasys_emi_req_mask_b; u8 reg_infrasys_infra_req_mask_b; + u8 reg_infrasys_pmic_req_mask_b; + u8 reg_infrasys_srcclkena_mask_b; + u8 reg_infrasys_vcore_req_mask_b; u8 reg_infrasys_vrf18_req_mask_b; u8 reg_ipic_infra_req_mask_b; u8 reg_ipic_vrf18_req_mask_b; @@ -356,15 +412,16 @@ u8 reg_mcu_infra_req_mask_b; u8 reg_mcu_pmic_req_mask_b; u8 reg_mcu_srcclkena_mask_b; + u8 reg_mcu_vcore_req_mask_b; u8 reg_mcu_vrf18_req_mask_b; u8 reg_md_apsrc_req_mask_b; u8 reg_md_ddren_req_mask_b; - - /* SPM_SRC_MASK_8 */ u8 reg_md_emi_req_mask_b; u8 reg_md_infra_req_mask_b; u8 reg_md_pmic_req_mask_b; u8 reg_md_srcclkena_mask_b; + + /* SPM_SRC_MASK_11 */ u8 reg_md_srcclkena1_mask_b; u8 reg_md_vcore_req_mask_b; u8 reg_md_vrf18_req_mask_b; @@ -374,6 +431,7 @@ u8 reg_mm_proc_infra_req_mask_b; u8 reg_mm_proc_pmic_req_mask_b; u8 reg_mm_proc_srcclkena_mask_b; + u8 reg_mm_proc_vcore_req_mask_b; u8 reg_mm_proc_vrf18_req_mask_b; u8 reg_mml0_apsrc_req_mask_b; u8 reg_mml0_ddren_req_mask_b; @@ -393,11 +451,11 @@ u8 reg_ovl0_ddren_req_mask_b; u8 reg_ovl0_emi_req_mask_b; u8 reg_ovl0_infra_req_mask_b; - - /* SPM_SRC_MASK_9 */ u8 reg_ovl0_pmic_req_mask_b; u8 reg_ovl0_srcclkena_mask_b; u8 reg_ovl0_vrf18_req_mask_b; + + /* SPM_SRC_MASK_12 */ u8 reg_ovl1_apsrc_req_mask_b; u8 reg_ovl1_ddren_req_mask_b; u8 reg_ovl1_emi_req_mask_b; @@ -413,13 +471,32 @@ u8 reg_pcie0_srcclkena_mask_b; u8 reg_pcie0_vcore_req_mask_b; u8 reg_pcie0_vrf18_req_mask_b; + u8 reg_pcie1_apsrc_req_mask_b; + u8 reg_pcie1_ddren_req_mask_b; + u8 reg_pcie1_emi_req_mask_b; + u8 reg_pcie1_infra_req_mask_b; + u8 reg_pcie1_pmic_req_mask_b; + u8 reg_pcie1_srcclkena_mask_b; + u8 reg_pcie1_vcore_req_mask_b; + u8 reg_pcie1_vrf18_req_mask_b; u8 reg_perisys_apsrc_req_mask_b; u8 reg_perisys_ddren_req_mask_b; u8 reg_perisys_emi_req_mask_b; u8 reg_perisys_infra_req_mask_b; u8 reg_perisys_pmic_req_mask_b; u8 reg_perisys_srcclkena_mask_b; + u8 reg_perisys_vcore_req_mask_b; u8 reg_perisys_vrf18_req_mask_b; + u8 reg_pmsr_apsrc_req_mask_b; + + /* SPM_SRC_MASK_13 */ + u8 reg_pmsr_ddren_req_mask_b; + u8 reg_pmsr_emi_req_mask_b; + u8 reg_pmsr_infra_req_mask_b; + u8 reg_pmsr_pmic_req_mask_b; + u8 reg_pmsr_srcclkena_mask_b; + u8 reg_pmsr_vcore_req_mask_b; + u8 reg_pmsr_vrf18_req_mask_b; u8 reg_scp_apsrc_req_mask_b; u8 reg_scp_ddren_req_mask_b; u8 reg_scp_emi_req_mask_b; @@ -427,8 +504,6 @@ u8 reg_scp_pmic_req_mask_b; u8 reg_scp_srcclkena_mask_b; u8 reg_scp_vcore_req_mask_b; - - /* SPM_SRC_MASK_10 */ u8 reg_scp_vrf18_req_mask_b; u8 reg_spu_hwrot_apsrc_req_mask_b; u8 reg_spu_hwrot_ddren_req_mask_b; @@ -436,6 +511,7 @@ u8 reg_spu_hwrot_infra_req_mask_b; u8 reg_spu_hwrot_pmic_req_mask_b; u8 reg_spu_hwrot_srcclkena_mask_b; + u8 reg_spu_hwrot_vcore_req_mask_b; u8 reg_spu_hwrot_vrf18_req_mask_b; u8 reg_spu_ise_apsrc_req_mask_b; u8 reg_spu_ise_ddren_req_mask_b; @@ -443,10 +519,14 @@ u8 reg_spu_ise_infra_req_mask_b; u8 reg_spu_ise_pmic_req_mask_b; u8 reg_spu_ise_srcclkena_mask_b; + u8 reg_spu_ise_vcore_req_mask_b; u8 reg_spu_ise_vrf18_req_mask_b; + + /* SPM_SRC_MASK_14 */ u8 reg_srcclkeni_infra_req_mask_b; u8 reg_srcclkeni_pmic_req_mask_b; u8 reg_srcclkeni_srcclkena_mask_b; + u8 reg_srcclkeni_vcore_req_mask_b; u8 reg_sspm_apsrc_req_mask_b; u8 reg_sspm_ddren_req_mask_b; u8 reg_sspm_emi_req_mask_b; @@ -458,12 +538,21 @@ u8 reg_ssrsys_ddren_req_mask_b; u8 reg_ssrsys_emi_req_mask_b; u8 reg_ssrsys_infra_req_mask_b; - - /* SPM_SRC_MASK_11 */ u8 reg_ssrsys_pmic_req_mask_b; u8 reg_ssrsys_srcclkena_mask_b; + u8 reg_ssrsys_vcore_req_mask_b; u8 reg_ssrsys_vrf18_req_mask_b; + u8 reg_ssusb_apsrc_req_mask_b; + u8 reg_ssusb_ddren_req_mask_b; + u8 reg_ssusb_emi_req_mask_b; + u8 reg_ssusb_infra_req_mask_b; + u8 reg_ssusb_pmic_req_mask_b; + u8 reg_ssusb_srcclkena_mask_b; + u8 reg_ssusb_vcore_req_mask_b; + u8 reg_ssusb_vrf18_req_mask_b; u8 reg_uart_hub_infra_req_mask_b; + + /* SPM_SRC_MASK_15 */ u8 reg_uart_hub_pmic_req_mask_b; u8 reg_uart_hub_srcclkena_mask_b; u8 reg_uart_hub_vcore_req_mask_b; @@ -474,6 +563,7 @@ u8 reg_ufs_infra_req_mask_b; u8 reg_ufs_pmic_req_mask_b; u8 reg_ufs_srcclkena_mask_b; + u8 reg_ufs_vcore_req_mask_b; u8 reg_ufs_vrf18_req_mask_b; u8 reg_vdec_apsrc_req_mask_b; u8 reg_vdec_ddren_req_mask_b; @@ -489,11 +579,36 @@ u8 reg_venc_pmic_req_mask_b; u8 reg_venc_srcclkena_mask_b; u8 reg_venc_vrf18_req_mask_b; + u8 reg_vlpcfg_rsv0_apsrc_req_mask_b; + u8 reg_vlpcfg_rsv0_ddren_req_mask_b; + u8 reg_vlpcfg_rsv0_emi_req_mask_b; + u8 reg_vlpcfg_rsv0_infra_req_mask_b; + u8 reg_vlpcfg_rsv0_pmic_req_mask_b; + u8 reg_vlpcfg_rsv0_srcclkena_mask_b; + + /* SPM_SRC_MASK_16 */ + u8 reg_vlpcfg_rsv0_vcore_req_mask_b; + u8 reg_vlpcfg_rsv0_vrf18_req_mask_b; + u8 reg_vlpcfg_rsv1_apsrc_req_mask_b; + u8 reg_vlpcfg_rsv1_ddren_req_mask_b; + u8 reg_vlpcfg_rsv1_emi_req_mask_b; + u8 reg_vlpcfg_rsv1_infra_req_mask_b; + u8 reg_vlpcfg_rsv1_pmic_req_mask_b; + u8 reg_vlpcfg_rsv1_srcclkena_mask_b; + u8 reg_vlpcfg_rsv1_vcore_req_mask_b; + u8 reg_vlpcfg_rsv1_vrf18_req_mask_b; /* SPM_EVENT_CON_MISC */ u8 reg_srcclken_fast_resp; u8 reg_csyspwrup_ack_mask; + /* SPM_SRC_MASK_17 */ + u32 reg_spm_sw_rsv_vcore_req_mask_b; + u32 reg_spm_sw_rsv_pmic_req_mask_b; + + /* SPM_SRC_MASK_18 */ + u32 reg_spm_sw_rsv_srcclkena_mask_b; + /* SPM_WAKEUP_EVENT_MASK */ u32 reg_wakeup_event_mask; @@ -546,7 +661,15 @@ u8 reserved10[40]; u32 md32pcm_sta; u32 md32pcm_pc; - u8 reserved11[104]; + u32 spm_ulposc_en_cg_con; + u32 spm_resource_ulposc_ack_con; + u32 spm_ulposc_off_mode_con; + u32 spm_ulposc_ack_sta; + u32 spm_reosource_ulposc_mask; + u32 spm_req_block; + u32 dvfs_ips_ctrl; + u32 top_cksys_con; + u8 reserved11[72]; u32 spm_ap_standby_con; u32 cpu_wfi_en; u32 cpu_wfi_en_set; @@ -567,16 +690,17 @@ u32 spm_cputop_pwr_con; u32 spm_cpu_pwr_con[8]; u32 spm_mcupm_spmc_con; - u8 reserved13[20]; + u32 sodi5_mcusys_con; + u8 reserved13[16]; u32 spm_dpm_p2p_sta; u32 spm_dpm_p2p_con; u32 spm_dpm_intf_sta; u32 spm_dpm_wb_con; - u32 pcm_apwdt_latch[20]; + u8 reserved14[80]; u32 spm_pwrap_con; u32 spm_pwrap_con_sta; u32 spm_pmic_spmi_con; - u8 reserved14[4]; + u8 reserved15[4]; u32 spm_pwrap_cmd[32]; u32 dvfsrc_event_sta; u32 spm_force_dvfs; @@ -588,13 +712,23 @@ u32 spm_dvfs_con; u32 spm_sramrc_con; u32 spm_srclkenrc_con; - u32 spm_dpsw_con; + u8 reserved16[4]; u32 spm_dpsw_vapu_iso_con; u32 spm_dpsw_vmm_iso_con; u32 spm_dpsw_vmd_iso_con; u32 spm_dpsw_vmodem_iso_con; u32 spm_dpsw_vcore_iso_con; - u8 reserved15[48]; + u32 spm_dpsw_con; + u32 spm_dpsw_con_set; + u32 spm_dpsw_con_clr; + u32 spm_dpsw_aoc_iso_con; + u32 spm_dpsw_aoc_iso_con_set; + u32 spm_dpsw_aoc_iso_con_clr; + u32 spm_dpsw_force_switch_con; + u32 spm_dpsw_force_switch_con_set; + u32 spm_dpsw_force_switch_con_clr; + u32 spm2dpsw_ctrl_ack; + u8 reserved17[8]; u32 ulposc_con; u32 ap_mdsrc_req; u32 spm2md_switch_ctrl; @@ -612,7 +746,13 @@ u32 cirq_bypass_con; u32 aoc_vcore_sram_con; u32 spm2emi_pdn_ctrl; - u8 reserved16[28]; + u32 vlp_rtff_ctrl_mask; + u32 vlp_rtff_ctrl_mask_set; + u32 vlp_rtff_ctrl_mask_clr; + u32 vlp_rtff_ctrl_mask_2; + u32 vlp_rtff_ctrl_mask_2_set; + u32 vlp_rtff_ctrl_mask_2_clr; + u8 reserved18[4]; u32 reg_module_sw_cg_ddren_req_mask[4]; u32 reg_module_sw_cg_vrf18_req_mask[4]; u32 reg_module_sw_cg_infra_req_mask[4]; @@ -636,7 +776,7 @@ u32 reg_module_busy_f26m_req_mask; u32 reg_module_busy_pmic_req_mask; u32 reg_module_busy_vcore_req_mask; - u8 reserved17[8]; + u8 reserved19[8]; u32 sys_timer_con; u32 sys_timer_value_l; u32 sys_timer_value_h; @@ -651,8 +791,7 @@ u32 spm_counter[3]; u32 pcm_wdt_val; u32 pcm_wdt_out; - u32 pcm_apwdt_latch_20[19]; - u8 reserved18[4]; + u8 reserved20[80]; u32 spm_sw_flag_0; u32 spm_sw_debug_0; u32 spm_sw_flag_1; @@ -662,7 +801,7 @@ u32 spm_bk_vtcxo_dur; u32 spm_bk_wake_misc; u32 spm_bk_pcm_timer; - u8 reserved19[12]; + u8 reserved21[12]; u32 spm_rsv_con_0; u32 spm_rsv_con_1; u32 spm_rsv_sta_0; @@ -680,7 +819,7 @@ u32 spm_sw_debug_2; u32 spm_dv_con_0; u32 spm_dv_con_1; - u8 reserved20[8]; + u8 reserved22[8]; u32 spm_sema_m[8]; u32 spm2adsp_mailbox; u32 adsp2spm_mailbox; @@ -693,7 +832,7 @@ u32 vcore_rtff_ctrl_mask_set; u32 vcore_rtff_ctrl_mask_clr; u32 spm_sram_srclkeno_mask; - u8 reserved21[256]; + u8 reserved23[256]; u32 spm_wakeup_sta; u32 spm_wakeup_ext_sta; u32 spm_wakeup_event_mask; @@ -701,46 +840,32 @@ u32 spm_wakeup_event_sens; u32 spm_wakeup_event_clear; u32 spm_src_req; - u32 spm_src_mask[12]; - u32 spm_req_sta[12]; + u32 spm_src_mask[17]; + u32 spm_req_sta[17]; u32 spm_ipc_wakeup_req; u32 ipc_wakeup_req_mask_sta; u32 spm_event_con_misc; u32 ddren_dbc_con; u32 spm_resource_ack_con[2]; - u32 spm_resource_ack_mask[9]; + u32 spm_resource_ack_mask[13]; u32 spm_event_counter_clear; u32 spm_vcore_event_count_sta; u32 spm_pmic_event_count_sta; - u32 spm_srcclkena_event_count_sta; + u32 spm_srclkena_event_count_sta; u32 spm_infra_event_count_sta; u32 spm_vrf18_event_count_sta; u32 spm_emi_event_count_sta; u32 spm_apsrc_event_count_sta; u32 spm_ddren_event_count_sta; - u32 pcm_wdt_latch[39]; - u32 pcm_wdt_latch_spare[10]; - u32 dramc_gating_err_latch[6]; - u32 dramc_gating_err_latch_spare_0; - u32 spm_debug_con; - u32 spm_ack_chk_con_0; - u32 spm_ack_chk_sel_0; - u32 spm_ack_chk_timer_0; - u32 spm_ack_chk_sta_0; - u32 spm_ack_chk_con_1; - u32 spm_ack_chk_sel_1; - u32 spm_ack_chk_timer_1; - u32 spm_ack_chk_sta_1; - u32 spm_ack_chk_con_2; - u32 spm_ack_chk_sel_2; - u32 spm_ack_chk_timer_2; - u32 spm_ack_chk_sta_2; - u32 spm_ack_chk_con_3; - u32 spm_ack_chk_sel_3; - u32 spm_ack_chk_timer_3; - u32 spm_ack_chk_sta_3; + u32 spm_src_mask_17; + u32 spm_src_mask_18; + u32 spm_resource_ack_mask_13; + u32 spm_resource_ack_mask_14; + u32 spm_req_sta_17; + u32 spm_req_sta_18; + u8 reserved24[212]; u32 md32pcm_cfgreg_sw_rstn; - u8 reserved22[508]; + u8 reserved25[508]; u32 md32pcm_dma0_src; u32 md32pcm_dma0_dst; u32 md32pcm_dma0_wppt; @@ -748,101 +873,75 @@ u32 md32pcm_dma0_count; u32 md32pcm_dma0_con; u32 md32pcm_dma0_start; - u8 reserved23[8]; + u8 reserved26[8]; u32 md32pcm_dma0_rlct; - u8 reserved24[276]; - u32 md32pcm_intc_irq_raw_sta; - u8 reserved25[192]; + u8 reserved27[472]; u32 md1_pwr_con; u32 conn_pwr_con; - u32 ifr_pwr_con; + u32 apifr_io_pwr_con; + u32 apifr_mem_pwr_con; u32 peri_pwr_con; - u32 peri_usb0_pwr_con; + u32 peri_ether_pwr_con; + u32 ssusb_dp_phy_p0_pwr_con; + u32 ssusb_p0_pwr_con; + u32 ssusb_p1_pwr_con; + u32 ssusb_p23_pwr_con; + u32 ssusb_phy_p2_pwr_con; u32 ufs0_pwr_con; u32 ufs0_phy_pwr_con; u32 pextp_mac0_pwr_con; u32 pextp_mac1_pwr_con; + u32 pextp_mac2_pwr_con; u32 pextp_phy0_pwr_con; u32 pextp_phy1_pwr_con; + u32 pextp_phy2_pwr_con; u32 audio_pwr_con; u32 adsp_core1_pwr_con; u32 adsp_top_pwr_con; u32 adsp_infra_pwr_con; u32 adsp_ao_pwr_con; - u32 isp_traw_pwr_con; - u32 isp_dip1_pwr_con; - u32 isp_main_pwr_con; - u32 isp_vcore_pwr_con; - u32 vde0_pwr_con; - u32 vde1_pwr_con; - u32 vde_vcore0_pwr_con; - u32 vde_vcore1_pwr_con; - u32 ven0_pwr_con; - u32 ven1_pwr_con; - u32 ven2_pwr_con; - u32 cam_mraw_pwr_con; - u32 cam_suba_pwr_con; - u32 cam_subb_pwr_con; - u32 cam_subc_pwr_con; - u32 cam_main_pwr_con; - u32 cam_vcore_pwr_con; - u32 cam_ccu_pwr_con; - u32 cam_ccu_ao_pwr_con; - u32 disp_vcore_pwr_con; - u32 mml0_pwr_con; - u32 mml1_pwr_con; - u32 dis0_pwr_con; - u32 dis1_pwr_con; - u32 ovl0_pwr_con; - u32 ovl1_pwr_con; - u32 mm_infra_pwr_con; u32 mm_proc_pwr_con; - u32 dp_tx_pwr_con; u32 scp_pwr_con; - u32 dpyd0_pwr_con; - u32 dpyd1_pwr_con; - u32 dpyd2_pwr_con; - u32 dpyd3_pwr_con; - u32 dpya0_pwr_con; - u32 dpya1_pwr_con; - u32 dpya2_pwr_con; - u32 dpya3_pwr_con; u32 dpm0_pwr_con; u32 dpm1_pwr_con; u32 dpm2_pwr_con; u32 dpm3_pwr_con; u32 emi0_pwr_con; u32 emi1_pwr_con; - u32 cpueb_pwr_con; - u32 csi_rx_pwr_con; + u32 emi_infra_pwr_con; u32 ssrsys_pwr_con; u32 spu_ise_pwr_con; u32 spu_hwrot_pwr_con; + u32 vlp_pwr_con; + u32 hsgmii0_pwr_con; + u32 hsgmii1_pwr_con; + u32 mfg_vlp_pwr_con; + u32 mcusys_busblk_pwr_con; + u32 cpueb_pwr_con; u32 mfg0_pwr_con; - u32 unipro_pdn_sram_con; - u32 ufs_sleep_sram_con; - u32 ccu_sleep_sram_con; - u32 mm_infra_ao_pdn_sram_con; - u32 infra_sleep_sram_con; - u32 peri_sleep_sram_con; - u32 nth_emi_slb_sram_con; - u32 nth_emi_slb_sram_ack; - u32 sth_emi_slb_sram_con; - u32 sth_emi_slb_sram_ack; - u32 ssr_sleep_sram_con; - u32 spu_ise_sleep_sram_con; - u32 spu_hwrot_sleep_sram_con; - u32 infra_hre_sram_con; - u32 emi_hre_sram_con; - u32 mm_hre_sram_con; - u32 mml_hre_sram_con; u32 adsp_hre_sram_con; + u32 ccu_sleep_sram_con; u32 efuse_sram_con; + u32 emi_hre_sram_con; + u32 infra_hre_sram_con; + u32 infra_sleep_sram_con; + u32 mml_hre_sram_con; + u32 mm_hre_sram_con; + u32 mm_infra_ao_pdn_sram_con; + u32 nth_emi_slb_sram_con; + u32 peri_sleep_sram_con; u32 spm_sram_con; + u32 spu_hwrot_sleep_sram_con; + u32 spu_ise_sleep_sram_con; u32 sspm_sram_con; + u32 ssr_sleep_sram_con; + u32 sth_emi_slb_sram_con; + u32 ufs_sleep_sram_con; + u32 unipro_pdn_sram_con; u32 cpu_buck_iso_con; u32 md_buck_iso_con; u32 soc_buck_iso_con; + u32 reserved28[2]; u32 soc_buck_iso_con_set; u32 soc_buck_iso_con_clr; u32 pwr_status; @@ -852,39 +951,194 @@ u32 xpu_pwr_status; u32 xpu_pwr_status_2nd; u32 dfd_soc_pwr_latch; - u8 reserved26[68]; + u32 nth_emi_slb_sram_ack; + u32 sth_emi_slb_sram_ack; + u32 dpyd0_pwr_con; + u32 dpyd1_pwr_con; + u32 dpyd2_pwr_con; + u32 dpyd3_pwr_con; + u32 dpya0_pwr_con; + u32 dpya1_pwr_con; + u32 dpya2_pwr_con; + u32 reserved29[2]; + u32 dpya3_pwr_con; + u32 scp_2_pwr_con; + u32 rsv_0_sleep_sram_con; + u32 rsv_1_sleep_sram_con; + u32 apifr_mem_sleep_sram_con; + u32 rsv_0_pwr_con; + u32 rsv_1_pwr_con; + u32 reserved30[22]; u32 spm_twam_con; u32 spm_twam_window_len; u32 spm_twam_idle_sel; u32 spm_twam_last_sta[4]; u32 spm_twam_curr_sta[4]; u32 spm_twam_timer_out; + u32 reserved31[8192]; + u32 md1_ssyspm_con; + u32 conn_ssyspm_con; + u32 apifr_io_ssyspm_con; + u32 apifr_mem_ssyspm_con; + u32 peri_ssyspm_con; + u32 peri_ether_ssyspm_con; + u32 ssusb_dp_phy_p0_ssyspm_con; + u32 ssusb_p0_ssyspm_con; + u32 ssusb_p1_ssyspm_con; + u32 ssusb_p23_ssyspm_con; + u32 ssusb_phy_p2_ssyspm_con; + u32 ufs0_ssyspm_con; + u32 ufs0_phy_ssyspm_con; + u32 pextp_mac0_ssyspm_con; + u32 pextp_mac1_ssyspm_con; + u32 pextp_mac2_ssyspm_con; + u32 pextp_phy0_ssyspm_con; + u32 pextp_phy1_ssyspm_con; + u32 pextp_phy2_ssyspm_con; + u32 audio_ssyspm_con; + u32 adsp_core1_ssyspm_con; + u32 adsp_top_ssyspm_con; + u32 adsp_infra_ssyspm_con; + u32 adsp_ao_ssyspm_con; + u32 mm_proc_ssyspm_con; + u32 scp_ssyspm_con; + u32 scp_2_ssyspm_con; + u32 dpyd0_ssyspm_con; + u32 dpyd1_ssyspm_con; + u32 dpyd2_ssyspm_con; + u32 dpyd3_ssyspm_con; + u32 dpya0_ssyspm_con; + u32 dpya1_ssyspm_con; + u32 dpya2_ssyspm_con; + u32 dpya3_ssyspm_con; + u32 dpm0_ssyspm_con; + u32 dpm1_ssyspm_con; + u32 dpm2_ssyspm_con; + u32 dpm3_ssyspm_con; + u32 emi0_ssyspm_con; + u32 emi1_ssyspm_con; + u32 emi_infra_ssyspm_con; + u32 ssrsys_ssyspm_con; + u32 spu_ise_ssyspm_con; + u32 spu_hwrot_ssyspm_con; + u32 vlp_ssyspm_con; + u32 hsgmii0_ssyspm_con; + u32 hsgmii1_ssyspm_con; + u32 mfg_vlp_ssyspm_con; + u32 mcusys_busblk_ssyspm_con; + u32 rsv_0_ssyspm_con; + u32 rsv_1_ssyspm_con; + u32 cpueb_ssyspm_con; + u32 mfg0_ssyspm_con; + u32 bus_protect_con; + u32 bus_protect_con_set; + u32 bus_protect_con_clr; + u32 bus_protect_msb_con; + u32 bus_protect_msb_con_set; + u32 bus_protect_msb_con_clr; + u32 bus_protect_cg_con; + u32 bus_protect_cg_con_set; + u32 bus_protect_cg_con_clr; + u32 bus_protect_cg_msb_con; + u32 ocla_en; + u32 ocla_sw_rst; + u32 ocla_config_0; + u32 ocla_cand_mux_sel; + u32 ocla_sleep_sram_con; + u32 ocla_comp_val; + u32 ocla_vcore_req_sel; + u32 ocla_vcore_ack_sel; + u32 ocla_pmic_req_sel; + u32 ocla_pmic_ack_sel; + u32 ocla_26m_req_sel; + u32 ocla_26m_ack_sel; + u32 ocla_infra_req_sel; + u32 ocla_infra_ack_sel; + u32 ocla_buspll_req_sel; + u32 ocla_buspll_ack_sel; + u32 ocla_emi_req_sel; + u32 ocla_emi_ack_sel; + u32 ocla_apsrc_req_sel; + u32 ocla_apsrc_ack_sel; + u32 ocla_ddren_req_sel; + u32 ocla_ddren_ack_sel; + u32 ocla_mtcmos_pwr_on_sel; + u32 ocla_mtcmos_pwr_ack_sel; + u32 ocla_mon_mode[2]; + u32 ocla_bit_seq[2]; + u32 ocla_bit_en; + u32 ocla_timer_lsb; + u32 ocla_timer_msb; + u32 ocla_trig_addr; + u32 ocla_sta; + u32 ocla_level_max_time; + u32 ocla_rsv[6]; + u32 reserved32[24]; + u32 bus_protect_cg_msb_con_set; + u32 bus_protect_cg_msb_con_clr; + u32 bus_protect_rdy; + u32 bus_protect_rdy_msb; + u32 spm_rsv_ulposc_req; + u32 spm_sw_rsv_vcore_req_con; + u32 spm_sw_rsv_vcore_req_con_set; + u32 spm_sw_rsv_vcore_req_con_clr; + u32 spm_lteclksq_bg_off; + u32 reserved33[55]; + u32 pbus_vcore_pkt_ctrl; + u32 pbus_vlp_pkt_ctrl; + u32 reserved34[2]; + u32 pbus_vlp_pkt_data[4]; + u32 pbus_vcore_pkt_data[4]; + u32 pbus_vcore_ctrl; + u32 pbus_vlp_ctrl; + u32 reserved35[2]; + u32 pbus_vcore_rx_pkt_ctrl; + u32 pbus_vlp_rx_pkt_ctrl; + u32 reserved36[2]; + u32 pbus_vlp_rx_pkt_data[4]; + u32 pbus_vcore_rx_pkt_data[4]; + u32 reserved37[100]; + u32 pcm_wdt_latch[39]; + u32 pcm_wdt_latch_spare[10]; + u32 dramc_gating_err_latch[6]; + u32 dramc_gating_err_latch_spare_0; + u32 spm_debug_con; + struct { + u32 con; + u32 sel; + u32 timer; + u32 sta; + } spm_ack_chk[4]; + u32 reserved38[3]; + u32 pcm_apwdt_latch[27]; + u32 reserved39[2]; + u32 pcm_apwdt_latch_27[12]; }; check_member(mtk_spm_regs, spm_wakeup_misc, 0x140); check_member(mtk_spm_regs, spm_mcupm_spmc_con, 0x288); -check_member(mtk_spm_regs, spm_dpm_wb_con, 0x2ac); -check_member(mtk_spm_regs, spm_pwrap_cmd[31], 0x38c); -check_member(mtk_spm_regs, spm_dpsw_con, 0x3b8); +check_member(mtk_spm_regs, spm_dpm_wb_con, 0x2AC); +check_member(mtk_spm_regs, spm_pwrap_cmd[31], 0x38C); +check_member(mtk_spm_regs, spm_dpsw_con, 0x3D0); check_member(mtk_spm_regs, spm2emi_pdn_ctrl, 0x440); -check_member(mtk_spm_regs, pcm_wdt_out, 0x5ac); -check_member(mtk_spm_regs, spm_sram_srclkeno_mask, 0x6fc); -check_member(mtk_spm_regs, spm_vcore_event_count_sta, 0x8bc); -check_member(mtk_spm_regs, spm_ack_chk_sta_3, 0x9fc); -check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xa00); -check_member(mtk_spm_regs, md32pcm_dma0_src, 0xc00); -check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xc24); -check_member(mtk_spm_regs, soc_buck_iso_con, 0xf64); -check_member(mtk_spm_regs, spm_twam_timer_out, 0xffc); +check_member(mtk_spm_regs, reg_module_busy_vcore_req_mask, 0x4F4); +check_member(mtk_spm_regs, sys_timer_con, 0x500); +check_member(mtk_spm_regs, pcm_wdt_out, 0x5AC); +check_member(mtk_spm_regs, spm_sram_srclkeno_mask, 0x6FC); +check_member(mtk_spm_regs, spm_vcore_event_count_sta, 0x8F4); +check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xA00); +check_member(mtk_spm_regs, md32pcm_dma0_src, 0xC00); +check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xC24); +check_member(mtk_spm_regs, md1_pwr_con, 0xE00); +check_member(mtk_spm_regs, soc_buck_iso_con, 0xF00); +check_member(mtk_spm_regs, spm_twam_timer_out, 0xFFC); +check_member(mtk_spm_regs, spm_lteclksq_bg_off, 0x9220); +check_member(mtk_spm_regs, pbus_vcore_pkt_ctrl, 0x9300); +check_member(mtk_spm_regs, pbus_vlp_pkt_data[3], 0x931C); +check_member(mtk_spm_regs, pbus_vcore_rx_pkt_data[3], 0x936C); +check_member(mtk_spm_regs, pcm_wdt_latch, 0x9500); +check_member(mtk_spm_regs, spm_ack_chk[3].sta, 0x9620); static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; -static const struct power_domain_data disp[] = { - /* TODO: add disp power domains */ -}; - -static const struct power_domain_data audio[] = { - /* TODO: add audio power domains */ -}; - #endif /* SOC_MEDIATEK_MT8196_SPM_H */ diff --git a/src/soc/mediatek/mt8196/spm.c b/src/soc/mediatek/mt8196/spm.c new file mode 100644 index 0000000..66964fb --- /dev/null +++ b/src/soc/mediatek/mt8196/spm.c @@ -0,0 +1,923 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <assert.h> +#include <delay.h> +#include <soc/mcu_common.h> +#include <soc/pll.h> +#include <soc/spm.h> + +struct mtk_vlpcksys_regs { + u32 reserved0[136]; + u32 vlp_clksq_con1; + u32 reserved1[15]; + u32 vlp_ap_pll_con3; +}; +check_member(mtk_vlpcksys_regs, vlp_clksq_con1, 0x220); +check_member(mtk_vlpcksys_regs, vlp_ap_pll_con3, 0x260); + +struct mtk_vlpdevapc_regs { + u32 vlp_ao_mas_sec_0; + u32 reserved0[319]; + u32 vlp_ao_apc_con; +}; +check_member(mtk_vlpdevapc_regs, vlp_ao_apc_con, 0x500); + +struct mtk_vlpcfg_regs { + u32 reserved0[66]; + u32 debug_mon_reg[2]; +}; +check_member(mtk_vlpcfg_regs, debug_mon_reg[1], 0x10c); + +static struct mtk_vlpcksys_regs *const mtk_vlpcksys = (void *)VLP_CKSYS_BASE; +static struct mtk_vlpdevapc_regs *const mtk_vlpdevapc = (void *)VLP_DEVAPC_BASE; +static struct mtk_vlpcfg_regs *const mtk_vlpcfg = (void *)VLP_CFG_BASE; + +unsigned int mt_spm_version; + +#define SPM_INIT_PCM_FLAG (SPM_FLAG_DISABLE_VCORE_DVS\ + | SPM_FLAG_DISABLE_DDR_DFS\ + | SPM_FLAG_DISABLE_EMI_DFS\ + | SPM_FLAG_DISABLE_BUS_DFS\ + | SPM_FLAG_RUN_COMMON_SCENARIO\ + | SPM_FLAG_ENABLE_MT8196_ES_WA\ + | SPM_FLAG_ENABLE_MT8196_EMI_ES_WA) + +static struct pwr_ctrl spm_init_ctrl = { + /* SPM_SRC_REQ */ + .reg_spm_adsp_mailbox_req = 0, + .reg_spm_apsrc_req = 1, + .reg_spm_ddren_req = 0, + .reg_spm_dvfs_req = 0, + .reg_spm_emi_req = 0, + .reg_spm_f26m_req = 0, + .reg_spm_infra_req = 0, + .reg_spm_pmic_req = 0, + .reg_spm_scp_mailbox_req = 0, + .reg_spm_sspm_mailbox_req = 0, + .reg_spm_sw_mailbox_req = 0, + .reg_spm_vcore_req = 1, + .reg_spm_vrf18_req = 0, + .adsp_mailbox_state = 0, + .apsrc_state = 0, + .ddren_state = 0, + .dvfs_state = 0, + .emi_state = 0, + .f26m_state = 0, + .infra_state = 0, + .pmic_state = 0, + .scp_mailbox_state = 0, + .sspm_mailbox_state = 0, + .sw_mailbox_state = 0, + .vcore_state = 0, + .vrf18_state = 0, + + /* SPM_SRC_MASK_0 */ + .reg_apu_apsrc_req_mask_b = 1, + .reg_apu_ddren_req_mask_b = 1, + .reg_apu_emi_req_mask_b = 1, + .reg_apu_infra_req_mask_b = 1, + .reg_apu_pmic_req_mask_b = 1, + .reg_apu_srcclkena_mask_b = 1, + .reg_apu_vrf18_req_mask_b = 1, + .reg_audio_dsp_apsrc_req_mask_b = 1, + .reg_audio_dsp_ddren_req_mask_b = 1, + .reg_audio_dsp_emi_req_mask_b = 1, + .reg_audio_dsp_infra_req_mask_b = 1, + .reg_audio_dsp_pmic_req_mask_b = 1, + .reg_audio_dsp_srcclkena_mask_b = 1, + .reg_audio_dsp_vcore_req_mask_b = 1, + .reg_audio_dsp_vrf18_req_mask_b = 1, + .reg_cam_apsrc_req_mask_b = 1, + .reg_cam_ddren_req_mask_b = 1, + .reg_cam_emi_req_mask_b = 1, + .reg_cam_infra_req_mask_b = 1, + .reg_cam_pmic_req_mask_b = 1, + .reg_cam_srcclkena_mask_b = 1, + .reg_cam_vrf18_req_mask_b = 1, + + /* SPM_SRC_MASK_1 */ + .reg_ccif_apsrc_req_mask_b = 0xfff, + .reg_ccif_emi_req_mask_b = 0xfff, + .reg_vlpcfg_rsv0_apsrc_req_mask_b = 1, + .reg_vlpcfg_rsv0_ddren_req_mask_b = 1, + .reg_vlpcfg_rsv0_emi_req_mask_b = 1, + .reg_vlpcfg_rsv0_infra_req_mask_b = 1, + .reg_vlpcfg_rsv0_pmic_req_mask_b = 1, + .reg_vlpcfg_rsv0_srcclkena_mask_b = 1, + .reg_vlpcfg_rsv0_vcore_req_mask_b = 1, + .reg_vlpcfg_rsv0_vrf18_req_mask_b = 1, + + /* SPM_SRC_MASK_2 */ + .reg_ccif_infra_req_mask_b = 0xfff, + .reg_ccif_pmic_req_mask_b = 0xfff, + .reg_vlpcfg_rsv1_apsrc_req_mask_b = 1, + .reg_vlpcfg_rsv1_ddren_req_mask_b = 1, + .reg_vlpcfg_rsv1_emi_req_mask_b = 1, + .reg_vlpcfg_rsv1_infra_req_mask_b = 1, + .reg_vlpcfg_rsv1_pmic_req_mask_b = 1, + .reg_vlpcfg_rsv1_srcclkena_mask_b = 1, + .reg_vlpcfg_rsv1_vcore_req_mask_b = 1, + .reg_vlpcfg_rsv1_vrf18_req_mask_b = 1, + + /* SPM_SRC_MASK_3 */ + .reg_ccif_srcclkena_mask_b = 0xfff, + .reg_ccif_vrf18_req_mask_b = 0xfff, + .reg_ccu_apsrc_req_mask_b = 1, + .reg_ccu_ddren_req_mask_b = 1, + .reg_ccu_emi_req_mask_b = 1, + .reg_ccu_infra_req_mask_b = 1, + .reg_ccu_pmic_req_mask_b = 1, + .reg_ccu_srcclkena_mask_b = 1, + .reg_ccu_vrf18_req_mask_b = 1, + .reg_cg_check_apsrc_req_mask_b = 1, + + /* SPM_SRC_MASK_4 */ + .reg_cg_check_ddren_req_mask_b = 1, + .reg_cg_check_emi_req_mask_b = 1, + .reg_cg_check_infra_req_mask_b = 1, + .reg_cg_check_pmic_req_mask_b = 1, + .reg_cg_check_srcclkena_mask_b = 1, + .reg_cg_check_vcore_req_mask_b = 1, + .reg_cg_check_vrf18_req_mask_b = 1, + .reg_conn_apsrc_req_mask_b = 1, + .reg_conn_ddren_req_mask_b = 1, + .reg_conn_emi_req_mask_b = 1, + .reg_conn_infra_req_mask_b = 1, + .reg_conn_pmic_req_mask_b = 1, + .reg_conn_srcclkena_mask_b = 1, + .reg_conn_srcclkenb_mask_b = 1, + .reg_conn_vcore_req_mask_b = 1, + .reg_conn_vrf18_req_mask_b = 1, + .reg_cpueb_apsrc_req_mask_b = 1, + .reg_cpueb_ddren_req_mask_b = 1, + .reg_cpueb_emi_req_mask_b = 1, + .reg_cpueb_infra_req_mask_b = 1, + .reg_cpueb_pmic_req_mask_b = 1, + .reg_cpueb_srcclkena_mask_b = 1, + .reg_cpueb_vrf18_req_mask_b = 1, + .reg_disp0_apsrc_req_mask_b = 1, + .reg_disp0_ddren_req_mask_b = 1, + .reg_disp0_emi_req_mask_b = 1, + .reg_disp0_infra_req_mask_b = 1, + .reg_disp0_pmic_req_mask_b = 1, + .reg_disp0_srcclkena_mask_b = 1, + .reg_disp0_vrf18_req_mask_b = 1, + .reg_disp1_apsrc_req_mask_b = 1, + .reg_disp1_ddren_req_mask_b = 1, + + /* SPM_SRC_MASK_5 */ + .reg_disp1_emi_req_mask_b = 1, + .reg_disp1_infra_req_mask_b = 1, + .reg_disp1_pmic_req_mask_b = 1, + .reg_disp1_srcclkena_mask_b = 1, + .reg_disp1_vrf18_req_mask_b = 1, + .reg_dpm_apsrc_req_mask_b = 0xf, + .reg_dpm_ddren_req_mask_b = 0xf, + .reg_dpm_emi_req_mask_b = 0xf, + .reg_dpm_infra_req_mask_b = 0xf, + .reg_dpm_pmic_req_mask_b = 0xf, + .reg_dpm_srcclkena_mask_b = 0xf, + + /* SPM_SRC_MASK_6 */ + .reg_dpm_vcore_req_mask_b = 0xf, + .reg_dpm_vrf18_req_mask_b = 0xf, + .reg_dpmaif_apsrc_req_mask_b = 1, + .reg_dpmaif_ddren_req_mask_b = 1, + .reg_dpmaif_emi_req_mask_b = 1, + .reg_dpmaif_infra_req_mask_b = 1, + .reg_dpmaif_pmic_req_mask_b = 1, + .reg_dpmaif_srcclkena_mask_b = 1, + .reg_dpmaif_vrf18_req_mask_b = 1, + .reg_dvfsrc_level_req_mask_b = 1, + .reg_emisys_apsrc_req_mask_b = 0, + .reg_emisys_ddren_req_mask_b = 1, + .reg_emisys_emi_req_mask_b = 0, + .reg_gce_apsrc_req_mask_b = 1, + .reg_gce_ddren_req_mask_b = 1, + .reg_gce_emi_req_mask_b = 1, + .reg_gce_infra_req_mask_b = 1, + .reg_gce_pmic_req_mask_b = 1, + .reg_gce_srcclkena_mask_b = 1, + .reg_gce_vrf18_req_mask_b = 1, + .reg_gpueb_apsrc_req_mask_b = 1, + .reg_gpueb_ddren_req_mask_b = 1, + .reg_gpueb_emi_req_mask_b = 1, + .reg_gpueb_infra_req_mask_b = 1, + .reg_gpueb_pmic_req_mask_b = 1, + .reg_gpueb_srcclkena_mask_b = 1, + + /* SPM_SRC_MASK_7 */ + .reg_gpueb_vrf18_req_mask_b = 1, + .reg_hwccf_apsrc_req_mask_b = 1, + .reg_hwccf_ddren_req_mask_b = 1, + .reg_hwccf_emi_req_mask_b = 1, + .reg_hwccf_infra_req_mask_b = 1, + .reg_hwccf_pmic_req_mask_b = 1, + .reg_hwccf_srcclkena_mask_b = 1, + .reg_hwccf_vcore_req_mask_b = 1, + .reg_hwccf_vrf18_req_mask_b = 1, + .reg_img_apsrc_req_mask_b = 1, + .reg_img_ddren_req_mask_b = 1, + .reg_img_emi_req_mask_b = 1, + .reg_img_infra_req_mask_b = 1, + .reg_img_pmic_req_mask_b = 1, + .reg_img_srcclkena_mask_b = 1, + .reg_img_vrf18_req_mask_b = 1, + .reg_infrasys_apsrc_req_mask_b = 0, + .reg_infrasys_ddren_req_mask_b = 1, + .reg_infrasys_emi_req_mask_b = 0, + .reg_infrasys_infra_req_mask_b = 1, + .reg_infrasys_vrf18_req_mask_b = 1, + .reg_ipic_infra_req_mask_b = 1, + .reg_ipic_vrf18_req_mask_b = 1, + .reg_mcu_apsrc_req_mask_b = 1, + .reg_mcu_ddren_req_mask_b = 1, + .reg_mcu_emi_req_mask_b = 1, + .reg_mcu_infra_req_mask_b = 1, + .reg_mcu_pmic_req_mask_b = 1, + .reg_mcu_srcclkena_mask_b = 1, + .reg_mcu_vrf18_req_mask_b = 1, + .reg_md_apsrc_req_mask_b = 1, + .reg_md_ddren_req_mask_b = 1, + + /* SPM_SRC_MASK_8 */ + .reg_md_emi_req_mask_b = 1, + .reg_md_infra_req_mask_b = 1, + .reg_md_pmic_req_mask_b = 1, + .reg_md_srcclkena_mask_b = 1, + .reg_md_srcclkena1_mask_b = 1, + .reg_md_vcore_req_mask_b = 1, + .reg_md_vrf18_req_mask_b = 1, + .reg_mm_proc_apsrc_req_mask_b = 1, + .reg_mm_proc_ddren_req_mask_b = 1, + .reg_mm_proc_emi_req_mask_b = 1, + .reg_mm_proc_infra_req_mask_b = 1, + .reg_mm_proc_pmic_req_mask_b = 1, + .reg_mm_proc_srcclkena_mask_b = 1, + .reg_mm_proc_vrf18_req_mask_b = 1, + .reg_mml0_apsrc_req_mask_b = 1, + .reg_mml0_ddren_req_mask_b = 1, + .reg_mml0_emi_req_mask_b = 1, + .reg_mml0_infra_req_mask_b = 1, + .reg_mml0_pmic_req_mask_b = 1, + .reg_mml0_srcclkena_mask_b = 1, + .reg_mml0_vrf18_req_mask_b = 1, + .reg_mml1_apsrc_req_mask_b = 1, + .reg_mml1_ddren_req_mask_b = 1, + .reg_mml1_emi_req_mask_b = 1, + .reg_mml1_infra_req_mask_b = 1, + .reg_mml1_pmic_req_mask_b = 1, + .reg_mml1_srcclkena_mask_b = 1, + .reg_mml1_vrf18_req_mask_b = 1, + .reg_ovl0_apsrc_req_mask_b = 1, + .reg_ovl0_ddren_req_mask_b = 1, + .reg_ovl0_emi_req_mask_b = 1, + .reg_ovl0_infra_req_mask_b = 1, + + /* SPM_SRC_MASK_9 */ + .reg_ovl0_pmic_req_mask_b = 1, + .reg_ovl0_srcclkena_mask_b = 1, + .reg_ovl0_vrf18_req_mask_b = 1, + .reg_ovl1_apsrc_req_mask_b = 1, + .reg_ovl1_ddren_req_mask_b = 1, + .reg_ovl1_emi_req_mask_b = 1, + .reg_ovl1_infra_req_mask_b = 1, + .reg_ovl1_pmic_req_mask_b = 1, + .reg_ovl1_srcclkena_mask_b = 1, + .reg_ovl1_vrf18_req_mask_b = 1, + .reg_pcie0_apsrc_req_mask_b = 1, + .reg_pcie0_ddren_req_mask_b = 1, + .reg_pcie0_emi_req_mask_b = 1, + .reg_pcie0_infra_req_mask_b = 1, + .reg_pcie0_pmic_req_mask_b = 1, + .reg_pcie0_srcclkena_mask_b = 1, + .reg_pcie0_vcore_req_mask_b = 1, + .reg_pcie0_vrf18_req_mask_b = 1, + .reg_perisys_apsrc_req_mask_b = 1, + .reg_perisys_ddren_req_mask_b = 1, + .reg_perisys_emi_req_mask_b = 1, + .reg_perisys_infra_req_mask_b = 1, + .reg_perisys_pmic_req_mask_b = 1, + .reg_perisys_srcclkena_mask_b = 1, + .reg_perisys_vrf18_req_mask_b = 1, + .reg_scp_apsrc_req_mask_b = 1, + .reg_scp_ddren_req_mask_b = 1, + .reg_scp_emi_req_mask_b = 1, + .reg_scp_infra_req_mask_b = 1, + .reg_scp_pmic_req_mask_b = 1, + .reg_scp_srcclkena_mask_b = 1, + .reg_scp_vcore_req_mask_b = 1, + + /* SPM_SRC_MASK_10 */ + .reg_scp_vrf18_req_mask_b = 1, + .reg_spu_hwrot_apsrc_req_mask_b = 1, + .reg_spu_hwrot_ddren_req_mask_b = 1, + .reg_spu_hwrot_emi_req_mask_b = 1, + .reg_spu_hwrot_infra_req_mask_b = 1, + .reg_spu_hwrot_pmic_req_mask_b = 1, + .reg_spu_hwrot_srcclkena_mask_b = 1, + .reg_spu_hwrot_vrf18_req_mask_b = 1, + .reg_spu_ise_apsrc_req_mask_b = 1, + .reg_spu_ise_ddren_req_mask_b = 1, + .reg_spu_ise_emi_req_mask_b = 1, + .reg_spu_ise_infra_req_mask_b = 1, + .reg_spu_ise_pmic_req_mask_b = 1, + .reg_spu_ise_srcclkena_mask_b = 1, + .reg_spu_ise_vrf18_req_mask_b = 1, + .reg_srcclkeni_infra_req_mask_b = 3, + .reg_srcclkeni_pmic_req_mask_b = 3, + .reg_srcclkeni_srcclkena_mask_b = 3, + .reg_sspm_apsrc_req_mask_b = 1, + .reg_sspm_ddren_req_mask_b = 1, + .reg_sspm_emi_req_mask_b = 1, + .reg_sspm_infra_req_mask_b = 1, + .reg_sspm_pmic_req_mask_b = 1, + .reg_sspm_srcclkena_mask_b = 1, + .reg_sspm_vrf18_req_mask_b = 1, + .reg_ssrsys_apsrc_req_mask_b = 1, + .reg_ssrsys_ddren_req_mask_b = 1, + .reg_ssrsys_emi_req_mask_b = 1, + .reg_ssrsys_infra_req_mask_b = 1, + + /* SPM_SRC_MASK_11 */ + .reg_ssrsys_pmic_req_mask_b = 1, + .reg_ssrsys_srcclkena_mask_b = 1, + .reg_ssrsys_vrf18_req_mask_b = 1, + .reg_uart_hub_infra_req_mask_b = 1, + .reg_uart_hub_pmic_req_mask_b = 1, + .reg_uart_hub_srcclkena_mask_b = 1, + .reg_uart_hub_vcore_req_mask_b = 1, + .reg_uart_hub_vrf18_req_mask_b = 1, + .reg_ufs_apsrc_req_mask_b = 1, + .reg_ufs_ddren_req_mask_b = 1, + .reg_ufs_emi_req_mask_b = 1, + .reg_ufs_infra_req_mask_b = 1, + .reg_ufs_pmic_req_mask_b = 1, + .reg_ufs_srcclkena_mask_b = 1, + .reg_ufs_vrf18_req_mask_b = 1, + .reg_vdec_apsrc_req_mask_b = 1, + .reg_vdec_ddren_req_mask_b = 1, + .reg_vdec_emi_req_mask_b = 1, + .reg_vdec_infra_req_mask_b = 1, + .reg_vdec_pmic_req_mask_b = 1, + .reg_vdec_srcclkena_mask_b = 1, + .reg_vdec_vrf18_req_mask_b = 1, + .reg_venc_apsrc_req_mask_b = 1, + .reg_venc_ddren_req_mask_b = 1, + .reg_venc_emi_req_mask_b = 1, + .reg_venc_infra_req_mask_b = 1, + .reg_venc_pmic_req_mask_b = 1, + .reg_venc_srcclkena_mask_b = 1, + .reg_venc_vrf18_req_mask_b = 1, + + /* SPM_EVENT_CON_MISC */ + .reg_srcclken_fast_resp = 0, + .reg_csyspwrup_ack_mask = 0, + + /* SPM_WAKEUP_EVENT_MASK */ + .reg_wakeup_event_mask = 0xEFFFFFF7, + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + .reg_ext_wakeup_event_mask = 0xFFFFFFFF, + + /*sw flag setting */ + .pcm_flags = SPM_INIT_PCM_FLAG, +}; + +void spm_set_power_control(const struct pwr_ctrl *pwrctrl) +{ + /* SPM_SRC_REQ */ + write32(&mtk_spm->spm_src_req, + ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 0) | + ((pwrctrl->reg_spm_apsrc_req & 0x1) << 1) | + ((pwrctrl->reg_spm_ddren_req & 0x1) << 2) | + ((pwrctrl->reg_spm_dvfs_req & 0x1) << 3) | + ((pwrctrl->reg_spm_emi_req & 0x1) << 4) | + ((pwrctrl->reg_spm_f26m_req & 0x1) << 5) | + ((pwrctrl->reg_spm_infra_req & 0x1) << 6) | + ((pwrctrl->reg_spm_pmic_req & 0x1) << 7) | + ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 8) | + ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 9) | + ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 10) | + ((pwrctrl->reg_spm_vcore_req & 0x1) << 11) | + ((pwrctrl->reg_spm_vrf18_req & 0x1) << 12) | + ((pwrctrl->adsp_mailbox_state & 0x1) << 16) | + ((pwrctrl->apsrc_state & 0x1) << 17) | + ((pwrctrl->ddren_state & 0x1) << 18) | + ((pwrctrl->dvfs_state & 0x1) << 19) | + ((pwrctrl->emi_state & 0x1) << 20) | + ((pwrctrl->f26m_state & 0x1) << 21) | + ((pwrctrl->infra_state & 0x1) << 22) | + ((pwrctrl->pmic_state & 0x1) << 23) | + ((pwrctrl->scp_mailbox_state & 0x1) << 24) | + ((pwrctrl->sspm_mailbox_state & 0x1) << 25) | + ((pwrctrl->sw_mailbox_state & 0x1) << 26) | + ((pwrctrl->vcore_state & 0x1) << 27) | + ((pwrctrl->vrf18_state & 0x1) << 28)); + + /* SPM_SRC_MASK_0 */ + write32(&mtk_spm->spm_src_mask, + ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_apu_emi_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_apu_pmic_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 5) | + ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_audio_dsp_emi_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_audio_dsp_pmic_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 12) | + ((pwrctrl->reg_audio_dsp_vcore_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_cam_apsrc_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_cam_ddren_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_cam_emi_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_cam_infra_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_cam_pmic_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_cam_srcclkena_mask_b & 0x1) << 20) | + ((pwrctrl->reg_cam_vrf18_req_mask_b & 0x1) << 21)); + + /* SPM_SRC_MASK_1 */ + write32(&mtk_spm->spm_src_mask[1], + ((pwrctrl->reg_ccif_apsrc_req_mask_b & 0xfff) << 0) | + ((pwrctrl->reg_ccif_emi_req_mask_b & 0xfff) << 12) | + ((pwrctrl->reg_vlpcfg_rsv0_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_vlpcfg_rsv0_ddren_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_vlpcfg_rsv0_emi_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_vlpcfg_rsv0_infra_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_vlpcfg_rsv0_pmic_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_vlpcfg_rsv0_srcclkena_mask_b & 0x1) << 29) | + ((pwrctrl->reg_vlpcfg_rsv0_vcore_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_vlpcfg_rsv0_vrf18_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_2 */ + write32(&mtk_spm->spm_src_mask[2], + ((pwrctrl->reg_ccif_infra_req_mask_b & 0xfff) << 0) | + ((pwrctrl->reg_ccif_pmic_req_mask_b & 0xfff) << 12) | + ((pwrctrl->reg_vlpcfg_rsv1_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_vlpcfg_rsv1_ddren_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_vlpcfg_rsv1_emi_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_vlpcfg_rsv1_infra_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_vlpcfg_rsv1_pmic_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_vlpcfg_rsv1_srcclkena_mask_b & 0x1) << 29) | + ((pwrctrl->reg_vlpcfg_rsv1_vcore_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_vlpcfg_rsv1_vrf18_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_3 */ + write32(&mtk_spm->spm_src_mask[3], + ((pwrctrl->reg_ccif_srcclkena_mask_b & 0xfff) << 0) | + ((pwrctrl->reg_ccif_vrf18_req_mask_b & 0xfff) << 12) | + ((pwrctrl->reg_ccu_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_ccu_ddren_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_ccu_emi_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_ccu_infra_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_ccu_pmic_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_ccu_srcclkena_mask_b & 0x1) << 29) | + ((pwrctrl->reg_ccu_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_4 */ + write32(&mtk_spm->spm_src_mask[4], + ((pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_cg_check_emi_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_cg_check_infra_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_cg_check_pmic_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 4) | + ((pwrctrl->reg_cg_check_vcore_req_mask_b & 0x1) << 5) | + ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_conn_emi_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_conn_pmic_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) | + ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) | + ((pwrctrl->reg_conn_vcore_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_cpueb_ddren_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_cpueb_emi_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_cpueb_pmic_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 21) | + ((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_disp0_emi_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_disp0_infra_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_disp0_pmic_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_disp0_srcclkena_mask_b & 0x1) << 28) | + ((pwrctrl->reg_disp0_vrf18_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_5 */ + write32(&mtk_spm->spm_src_mask[5], + ((pwrctrl->reg_disp1_emi_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_disp1_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_disp1_pmic_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_disp1_srcclkena_mask_b & 0x1) << 3) | + ((pwrctrl->reg_disp1_vrf18_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_dpm_apsrc_req_mask_b & 0xf) << 5) | + ((pwrctrl->reg_dpm_ddren_req_mask_b & 0xf) << 9) | + ((pwrctrl->reg_dpm_emi_req_mask_b & 0xf) << 13) | + ((pwrctrl->reg_dpm_infra_req_mask_b & 0xf) << 17) | + ((pwrctrl->reg_dpm_pmic_req_mask_b & 0xf) << 21) | + ((pwrctrl->reg_dpm_srcclkena_mask_b & 0xf) << 25)); + + /* SPM_SRC_MASK_6 */ + write32(&mtk_spm->spm_src_mask[6], + ((pwrctrl->reg_dpm_vcore_req_mask_b & 0xf) << 0) | + ((pwrctrl->reg_dpm_vrf18_req_mask_b & 0xf) << 4) | + ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_dpmaif_emi_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_dpmaif_pmic_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 13) | + ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_dvfsrc_level_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_emisys_apsrc_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_emisys_ddren_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_emisys_emi_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_gce_ddren_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_gce_emi_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_gce_pmic_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_gce_srcclkena_mask_b & 0x1) << 24) | + ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_gpueb_apsrc_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_gpueb_ddren_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_gpueb_emi_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_gpueb_infra_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_gpueb_pmic_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_gpueb_srcclkena_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_7 */ + write32(&mtk_spm->spm_src_mask[7], + ((pwrctrl->reg_gpueb_vrf18_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_hwccf_apsrc_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_hwccf_ddren_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_hwccf_emi_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_hwccf_infra_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_hwccf_pmic_req_mask_b & 0x1) << 5) | + ((pwrctrl->reg_hwccf_srcclkena_mask_b & 0x1) << 6) | + ((pwrctrl->reg_hwccf_vcore_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_hwccf_vrf18_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_img_apsrc_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_img_ddren_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_img_emi_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_img_infra_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_img_pmic_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_img_srcclkena_mask_b & 0x1) << 14) | + ((pwrctrl->reg_img_vrf18_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_infrasys_emi_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_infrasys_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_infrasys_vrf18_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_ipic_infra_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_ipic_vrf18_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_mcu_apsrc_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_mcu_ddren_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_mcu_emi_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_mcu_infra_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_mcu_pmic_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_mcu_srcclkena_mask_b & 0x1) << 28) | + ((pwrctrl->reg_mcu_vrf18_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_md_apsrc_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_md_ddren_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_8 */ + write32(&mtk_spm->spm_src_mask[8], + ((pwrctrl->reg_md_emi_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_md_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_md_pmic_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_md_srcclkena_mask_b & 0x1) << 3) | + ((pwrctrl->reg_md_srcclkena1_mask_b & 0x1) << 4) | + ((pwrctrl->reg_md_vcore_req_mask_b & 0x1) << 5) | + ((pwrctrl->reg_md_vrf18_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_mm_proc_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_mm_proc_ddren_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_mm_proc_emi_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_mm_proc_infra_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_mm_proc_pmic_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_mm_proc_srcclkena_mask_b & 0x1) << 12) | + ((pwrctrl->reg_mm_proc_vrf18_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_mml0_apsrc_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_mml0_ddren_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_mml0_emi_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_mml0_infra_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_mml0_pmic_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_mml0_srcclkena_mask_b & 0x1) << 19) | + ((pwrctrl->reg_mml0_vrf18_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_mml1_apsrc_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_mml1_ddren_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_mml1_emi_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_mml1_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_mml1_pmic_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_mml1_srcclkena_mask_b & 0x1) << 26) | + ((pwrctrl->reg_mml1_vrf18_req_mask_b & 0x1) << 27) | + (((u32)pwrctrl->reg_ovl0_apsrc_req_mask_b & 0x1) << 28) | + (((u32)pwrctrl->reg_ovl0_ddren_req_mask_b & 0x1) << 29) | + (((u32)pwrctrl->reg_ovl0_emi_req_mask_b & 0x1) << 30) | + (((u32)pwrctrl->reg_ovl0_infra_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_9 */ + write32(&mtk_spm->spm_src_mask[9], + ((pwrctrl->reg_ovl0_pmic_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_ovl0_srcclkena_mask_b & 0x1) << 1) | + ((pwrctrl->reg_ovl0_vrf18_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_ovl1_apsrc_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_ovl1_ddren_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_ovl1_emi_req_mask_b & 0x1) << 5) | + ((pwrctrl->reg_ovl1_infra_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_ovl1_pmic_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_ovl1_srcclkena_mask_b & 0x1) << 8) | + ((pwrctrl->reg_ovl1_vrf18_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_pcie0_apsrc_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_pcie0_ddren_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_pcie0_emi_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_pcie0_infra_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_pcie0_pmic_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_pcie0_srcclkena_mask_b & 0x1) << 15) | + ((pwrctrl->reg_pcie0_vcore_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_pcie0_vrf18_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_perisys_apsrc_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_perisys_ddren_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_perisys_emi_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_perisys_infra_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_perisys_pmic_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_perisys_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_perisys_vrf18_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_scp_emi_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_scp_pmic_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 30) | + ((pwrctrl->reg_scp_vcore_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_10 */ + write32(&mtk_spm->spm_src_mask[10], + ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_spu_hwrot_apsrc_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_spu_hwrot_ddren_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_spu_hwrot_emi_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_spu_hwrot_infra_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_spu_hwrot_pmic_req_mask_b & 0x1) << 5) | + ((pwrctrl->reg_spu_hwrot_srcclkena_mask_b & 0x1) << 6) | + ((pwrctrl->reg_spu_hwrot_vrf18_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_spu_ise_apsrc_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_spu_ise_ddren_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_spu_ise_emi_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_spu_ise_infra_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_spu_ise_pmic_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_spu_ise_srcclkena_mask_b & 0x1) << 13) | + ((pwrctrl->reg_spu_ise_vrf18_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x3) << 15) | + ((pwrctrl->reg_srcclkeni_pmic_req_mask_b & 0x3) << 17) | + ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x3) << 19) | + ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_sspm_emi_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_sspm_pmic_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 26) | + ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_ssrsys_apsrc_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_ssrsys_ddren_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_ssrsys_emi_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_ssrsys_infra_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_11 */ + write32(&mtk_spm->spm_src_mask[11], + ((pwrctrl->reg_ssrsys_pmic_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_ssrsys_srcclkena_mask_b & 0x1) << 1) | + ((pwrctrl->reg_ssrsys_vrf18_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_uart_hub_infra_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_uart_hub_pmic_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_uart_hub_srcclkena_mask_b & 0x1) << 5) | + ((pwrctrl->reg_uart_hub_vcore_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_uart_hub_vrf18_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_ufs_emi_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_ufs_pmic_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 13) | + ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_vdec_apsrc_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_vdec_ddren_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_vdec_emi_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_vdec_infra_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_vdec_pmic_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_vdec_srcclkena_mask_b & 0x1) << 20) | + ((pwrctrl->reg_vdec_vrf18_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_venc_apsrc_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_venc_ddren_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_venc_emi_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_venc_infra_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_venc_pmic_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_venc_srcclkena_mask_b & 0x1) << 27) | + ((pwrctrl->reg_venc_vrf18_req_mask_b & 0x1) << 28)); + + /* SPM_EVENT_CON_MISC */ + write32(&mtk_spm->spm_event_con_misc, + ((pwrctrl->reg_srcclken_fast_resp & 0x1) << 0) | + ((pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 1)); + + /* SPM_WAKEUP_EVENT_MASK */ + write32(&mtk_spm->spm_wakeup_event_mask, + (pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0); + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + write32(&mtk_spm->spm_wakeup_event_ext_mask, + (pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0); +} + +static void spm_hw_s1_state_monitor(bool en) +{ + if (en) + clrsetbits32(&mtk_spm->spm_ack_chk[3].con, SPM_ACK_CHK_3_CON_CLR_ALL, + SPM_ACK_CHK_3_CON_EN); + else + clrsetbits32(&mtk_spm->spm_ack_chk[3].con, + SPM_ACK_CHK_3_CON_HW_MODE_TRIG | SPM_ACK_CHK_3_CON_CLR_ALL, + SPM_ACK_CHK_3_CON_EN); +} + +static void spm_init_ulposc_ctrl(void) +{ + write32(&mtk_spm->spm_reosource_ulposc_mask, 0x0); + + clrbits32(&mtk_spm->spm_ulposc_en_cg_con, BIT(16)); + + write32(&mtk_spm->spm_resource_ulposc_ack_con, 0x185); + + setbits32(&mtk_spm->spm_reosource_ulposc_mask, + BIT(2) | BIT(18) | BIT(5) | BIT(21) | BIT(6) | BIT(22) | BIT(1) | BIT(17)); + + setbits32(&mtk_spm->spm_ulposc_en_cg_con, BIT(5) | BIT(0) | BIT(16)); + + setbits32(&mtk_spm->spm_rsv_ulposc_req, (0x1)); + + udelay(100); + + write32(&mtk_spm->spm_ulposc_off_mode_con, 0x1); +} + +void spm_register_init(void) +{ + /* Enable scpsys (SPM) clock off control, 0: Topck AO */ + setbits32(&mtk_topckgen->clk_scp_cfg, 0x3FF); + setbits32(&mtk_vlpcksys->vlp_clksq_con1, 0x1); + clrbits32(&mtk_vlpcksys->vlp_ap_pll_con3, BIT(1)); + clrbits32(&mtk_vlpcksys->vlp_ap_pll_con3, BIT(6)); + + /* Enable register control */ + write32(&mtk_spm->poweron_config_en, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); + + /* Init power control register */ + write32(&mtk_spm->spm_power_on_val[1], POWER_ON_VAL1_DEF); + + clrbits32(&mtk_spm->spm_sram_con, 0xF << 16); + + /* SRAM Workaround for Sleep FSM */ + setbits32(&mtk_spm->spm_sram_sleep_ctrl, 0x2 << 8); + + write32(&mtk_spm->spm_power_on_val[1], POWER_ON_VAL1_DEF); + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + write32(&mtk_spm->pcm_con1, + SPM_REGWR_CFG_KEY | REG_SPM_APB_INTERNAL_EN_LSB | REG_SSPM_APB_P2P_EN_LSB); + + write32(&mtk_spm->spm_clk_con, (0x10 << 24) | (0x7 << 4)); + + /* clean wakeup event raw status */ + write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF); + + /* clean ISR status */ + write32(&mtk_spm->spm_irq_mask, ISRM_ALL); + write32(&mtk_spm->spm_irq_sta, ISRC_ALL); + write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL); + + setbits32(&mtk_spm->spm_ap_standby_con, BIT(1)); + + write32(&mtk_spm->spm_resource_ack_con[0], 0xCC4E4ECC); + write32(&mtk_spm->spm_resource_ack_con[1], 0x00CCCCCC); + + /* Init Other Reg */ + write32(&mtk_spm->spm_ack_chk[3].sel, SPM_ACK_CHK_3_SEL_HW_S1); + write32(&mtk_spm->spm_ack_chk[3].timer, SPM_ACK_CHK_3_HW_S1_CNT); + spm_hw_s1_state_monitor(0); + + /* Init SPM DEBUG Output enable */ + write32(&mtk_spm->spm_debug_con, 0x1); + /* Init for SPM Resource ACK */ + write32(&mtk_spm->spm_resource_ack_con[0], 0xCC4E4ECC); + write32(&mtk_spm->spm_resource_ack_con[1], 0x00CCCCCC); + + clrbits32(&mtk_vlpdevapc->vlp_ao_apc_con, BIT(2)); + setbits32(&mtk_vlpdevapc->vlp_ao_mas_sec_0, 0x3); + /* infra sw cg mask for all bit */ + write32p(INFRA_SW_CG, 0xFFFFFFFF); + /* debug_mon for spm pwr_status_msb mtcmos ack check */ + write32(&mtk_vlpcfg->debug_mon_reg[0], (0x79U << 16) | (0x78U << 0)); + write32(&mtk_vlpcfg->debug_mon_reg[1], (0x7BU << 16) | (0x7AU << 0)); + + spm_init_ulposc_ctrl(); + + spm_set_power_control(&spm_init_ctrl); +} + +void spm_reset_and_init_pcm(void) +{ + /* disable r0 and r7 to control power */ + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* disable pcm timer after leaving FW */ + clrsetbits32(&mtk_spm->pcm_con1, + REG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); + + /* reset PCM */ + write32(&mtk_spm->pcm_con0, + SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + /* init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */ + clrsetbits32(&mtk_spm->pcm_con1, ~REG_PCM_WDT_WAKE_LSB, + SPM_REGWR_CFG_KEY | REG_SPM_APB_INTERNAL_EN_LSB | + REG_SSPM_APB_P2P_EN_LSB); +} + +void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) +{ + u32 val, mask; + + /* toggle event counter clear */ + write32(&mtk_spm->spm_event_counter_clear, REG_SPM_EVENT_COUNTER_CLR_LSB); + /* toggle for reset SYS TIMER start point */ + setbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB); + + if (pwrctrl->timer_val_cust == 0) + val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_SUSPEND; + else + val = pwrctrl->timer_val_cust; + + write32(&mtk_spm->pcm_timer_val, val); + setbits32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | REG_PCM_TIMER_EN_LSB); + + /* unmask AP wakeup source */ + if (pwrctrl->wake_src_cust == 0) + mask = pwrctrl->wake_src; + else + mask = pwrctrl->wake_src_cust; + + if (pwrctrl->reg_csyspwrup_ack_mask) + mask &= ~R12_CSYSPWREQ_B; + write32(&mtk_spm->spm_wakeup_event_mask, ~mask); + + /* unmask SPM ISR (keep TWAM setting) */ + setbits32(&mtk_spm->spm_irq_mask, ISRM_RET_IRQ_AUX); + + /* toggle event counter clear */ + write32(&mtk_spm->spm_event_counter_clear, 0); + /* toggle for reset SYS TIMER start point */ + clrbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB); +} + +void spm_init_pcm_register(void) +{ + write32(&mtk_spm->pcm_pwr_io_en, 0); +} + +void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl) +{ + /* Waiting for loading SPMFW done*/ + while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0) + ; + + /* In the new SOC design, this part has been simplified */ + spm_set_pcm_flags(pwrctrl); + + /* Kick PCM to run (only toggle PCM_KICK) */ + setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + /* Reset md32pcm */ + SET32_BITFIELDS(&mtk_spm->md32pcm_cfgreg_sw_rstn, + MD32PCM_CFGREG_SW_RSTN_RESET, 1); + + /* Waiting for SPM init done */ + udelay(SPM_INIT_DONE_US); +} + +const struct pwr_ctrl *get_pwr_ctrl(void) +{ + return &spm_init_ctrl; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Gerrit-Change-Number: 85599 Gerrit-PatchSet: 16 Gerrit-Owner: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-CC: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com>

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[XL] Change in coreboot[main]: util/intelp2m: Rework platforms and fields packages
by Maxim (Code Review) 21 Dec '24

21 Dec '24

Attention is currently required from: David Hendricks. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71167?usp=email to look at the new patch set (#18). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/intelp2m: Rework platforms and fields packages ...................................................................... util/intelp2m: Rework platforms and fields packages - Add the base platform interface to be able to reuse its methods. - The macro structure is excluded from the platform structure. - Instead of a global macro instance, create a new local structure for each generated macro. TEST: 1) 'make test' = PASS 2) './intelp2m -p cnl -iiii -file inteltool.log' = gpio.h before and after the commit is the same. Change-Id: I2e0aa56efa2430ac6524c6977f8b6fd13113edf9 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/fields/cb/cb.go M util/intelp2m/fields/cb/cb_test.go M util/intelp2m/fields/fields.go M util/intelp2m/fields/fsp/fsp.go M util/intelp2m/fields/fsp/fsp_test.go M util/intelp2m/fields/raw/raw.go M util/intelp2m/fields/raw/raw_test.go M util/intelp2m/fields/test/suite.go M util/intelp2m/parser/parser.go M util/intelp2m/platforms/adl/adl_test.go M util/intelp2m/platforms/adl/macro.go M util/intelp2m/platforms/adl/template.go M util/intelp2m/platforms/apl/apl_test.go M util/intelp2m/platforms/apl/macro.go M util/intelp2m/platforms/apl/template.go M util/intelp2m/platforms/cnl/cnl_test.go M util/intelp2m/platforms/cnl/macro.go M util/intelp2m/platforms/cnl/template.go A util/intelp2m/platforms/common/common.go M util/intelp2m/platforms/common/macro.go M util/intelp2m/platforms/common/register/dw0.go M util/intelp2m/platforms/common/register/dw1.go A util/intelp2m/platforms/common/register/helper.go M util/intelp2m/platforms/ebg/ebg_test.go M util/intelp2m/platforms/ebg/macro.go M util/intelp2m/platforms/ebg/template.go D util/intelp2m/platforms/interfaces.go M util/intelp2m/platforms/jsl/jsl_test.go M util/intelp2m/platforms/jsl/macro.go M util/intelp2m/platforms/jsl/template.go M util/intelp2m/platforms/lbg/lbg_test.go M util/intelp2m/platforms/lbg/macro.go M util/intelp2m/platforms/lbg/template.go M util/intelp2m/platforms/mtl/macro.go M util/intelp2m/platforms/mtl/mtl_test.go M util/intelp2m/platforms/mtl/template.go A util/intelp2m/platforms/platforms.go M util/intelp2m/platforms/snr/macro.go M util/intelp2m/platforms/snr/snr_test.go M util/intelp2m/platforms/snr/template.go M util/intelp2m/platforms/test/suite.go M util/intelp2m/platforms/tgl/macro.go M util/intelp2m/platforms/tgl/template.go M util/intelp2m/platforms/tgl/tgl_test.go 44 files changed, 1,183 insertions(+), 1,500 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/71167/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/71167?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e0aa56efa2430ac6524c6977f8b6fd13113edf9 Gerrit-Change-Number: 71167 Gerrit-PatchSet: 18 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com>

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[L] Change in coreboot[main]: mb/prodrive/atlas: Add initial support for options
by Martin L Roth (Code Review) 21 Dec '24

21 Dec '24

Attention is currently required from: Angel Pons, Lean Sheng Tan, Patrick Rudolph. Martin L Roth has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/74122?usp=email ) Change subject: mb/prodrive/atlas: Add initial support for options ...................................................................... Patch Set 24: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/74122?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47585a9a6f94ab5005f2ab63a0df267c0caef231 Gerrit-Change-Number: 74122 Gerrit-PatchSet: 24 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Comment-Date: Sat, 21 Dec 2024 15:31:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: util/crossgcc: Update CMake from 3.30.2 to 3.31.3
by Elyes Haouas (Code Review) 21 Dec '24

21 Dec '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85168?usp=email ) Change subject: util/crossgcc: Update CMake from 3.30.2 to 3.31.3 ...................................................................... util/crossgcc: Update CMake from 3.30.2 to 3.31.3 Change-Id: I573dace3b752a0d3c4614ece9c0845f8334e2857 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85168 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.30.2.tar.gz.cksum A util/crossgcc/sum/cmake-3.31.3.tar.gz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) Approvals: Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 4c327d1..a751003 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -44,7 +44,7 @@ IASL_VERSION=20241212 # CLANG version number CLANG_VERSION=18.1.8 -CMAKE_VERSION=3.30.2 +CMAKE_VERSION=3.31.3 NASM_VERSION=2.16.03 # Filename for each package diff --git a/util/crossgcc/sum/cmake-3.30.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.30.2.tar.gz.cksum deleted file mode 100644 index f3ddfba..0000000 --- a/util/crossgcc/sum/cmake-3.30.2.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -7cf72aa27d1a7791e035060031aebfdcf0a10e5a tarballs/cmake-3.30.2.tar.gz diff --git a/util/crossgcc/sum/cmake-3.31.3.tar.gz.cksum b/util/crossgcc/sum/cmake-3.31.3.tar.gz.cksum new file mode 100644 index 0000000..cef715c --- /dev/null +++ b/util/crossgcc/sum/cmake-3.31.3.tar.gz.cksum @@ -0,0 +1 @@ +7ce645495d3c79e0a5763fff08c5a78aea877258 tarballs/cmake-3.31.3.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/85168?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I573dace3b752a0d3c4614ece9c0845f8334e2857 Gerrit-Change-Number: 85168 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: amdfwtool: Check fletcher of each header
by Maximilian Brune (Code Review) 21 Dec '24

21 Dec '24

Attention is currently required from: Bao Zheng, Felix Held, Julius Werner, Paul Menzel, Zheng Bao. Maximilian Brune has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84338?usp=email ) Change subject: amdfwtool: Check fletcher of each header ...................................................................... Patch Set 5: (3 comments) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/84338/comment/57d10763_a99794b0?us… : PS5, Line 540: psp_directory_table *dir = directory; nit: Use same naming scheme as for the others (e.g. pdir instead of dir) https://review.coreboot.org/c/coreboot/+/84338/comment/2bb5a0af_fd54015d?us… : PS5, Line 544: uint32_t cookie = ((psp_directory_table *)directory)->header.cookie; Do you need the extra type conversion? Can't you just use the `dir` from above? https://review.coreboot.org/c/coreboot/+/84338/comment/178d4ee7_f6db04cb?us… : PS5, Line 549: if (directory == NULL) You should probably do this check before dereferencing `directory` above -- To view, visit https://review.coreboot.org/c/coreboot/+/84338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7540386027c6449317e9b7c0b4fd22d09d4a3a3 Gerrit-Change-Number: 84338 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 21 Dec 2024 15:17:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: util/crossgcc: Update CMake from 3.30.2 to 3.31.3
by Elyes Haouas (Code Review) 21 Dec '24

21 Dec '24

Attention is currently required from: Felix Singer, Martin L Roth. Elyes Haouas has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/85168?usp=email ) Change subject: util/crossgcc: Update CMake from 3.30.2 to 3.31.3 ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85168?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I573dace3b752a0d3c4614ece9c0845f8334e2857 Gerrit-Change-Number: 85168 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Sat, 21 Dec 2024 15:15:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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