coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[M] Change in coreboot[main]: mb/google/rauru: Add support for getting storage id
by Jarried Lin (Code Review) 22 Dec '24

22 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85717?usp=email ) Change subject: mb/google/rauru: Add support for getting storage id ...................................................................... Patch Set 3: (8 comments) File src/mainboard/google/rauru/boardid.c: https://review.coreboot.org/c/coreboot/+/85717/comment/c53fa90c_6c448986?us… : PS1, Line 14: SKU IDs > Storage ID Done https://review.coreboot.org/c/coreboot/+/85717/comment/84118de7_559699f3?us… : PS1, Line 16: STORAGE_ID_HIGH_CHANNEL > Do we need this if not used? Done https://review.coreboot.org/c/coreboot/+/85717/comment/0301861b_72a55eb8?us… : PS1, Line 57: panel > storage Done https://review.coreboot.org/c/coreboot/+/85717/comment/1b3b6f8b_e4ad7182?us… : PS1, Line 61: printk(BIOS_DEBUG, "Storage ID: %#02x\n", cached_panel_id); > insert the blank line on above Done https://review.coreboot.org/c/coreboot/+/85717/comment/73d6bc13_c09093e9?us… : PS1, Line 62: > remove this blank line Done File src/mainboard/google/rauru/mainboard.c: https://review.coreboot.org/c/coreboot/+/85717/comment/fee1fe96_4f2a0241?us… : PS1, Line 14: #include <soc/mt6363_sdmadc.h> > remove ? Done https://review.coreboot.org/c/coreboot/+/85717/comment/dba70376_8e80f01d?us… : PS1, Line 60: mt6363_init_pmif_arb(); : mt6363_enable_vtref18(true); : mt6363_set_vtref18_voltage(1800000); : mt6363_get_vtref18_voltage(); > An alternative is powering on `vtref18` in `storage_id` (since this power rail is board-specific des […] Done https://review.coreboot.org/c/coreboot/+/85717/comment/f93b076e_7269baa1?us… : PS1, Line 63: mt6363_get_vtref18_voltage(); > Remove `mt6363_get_vtref18_voltage`. It is not needed. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I036df324cd6644ff69110c6247af29360b83225f Gerrit-Change-Number: 85717 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Knox Chiou <knoxchiou(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sun, 22 Dec 2024 12:06:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

1 0

[M] Change in coreboot[main]: mb/google/rauru: Add support for getting storage id
by Jarried Lin (Code Review) 22 Dec '24

22 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85717?usp=email to look at the new patch set (#3). Change subject: mb/google/rauru: Add support for getting storage id ...................................................................... mb/google/rauru: Add support for getting storage id We add storage_id() to read the storage id from auxadc. BUG=b:317009620 TEST=Build pass Change-Id: I036df324cd6644ff69110c6247af29360b83225f Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/Makefile.mk A src/mainboard/google/rauru/boardid.c M src/mainboard/google/rauru/romstage.c A src/mainboard/google/rauru/storage.h 4 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/85717/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I036df324cd6644ff69110c6247af29360b83225f Gerrit-Change-Number: 85717 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Knox Chiou <knoxchiou(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[S] Change in coreboot[main]: mb/google/rauru: Implement SKU ID
by Jarried Lin (Code Review) 22 Dec '24

22 Dec '24

Attention is currently required from: Hung-Te Lin, Knox Chiou, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85666?usp=email ) Change subject: mb/google/rauru: Implement SKU ID ...................................................................... Patch Set 10: (2 comments) File src/mainboard/google/rauru/boardid.c: https://review.coreboot.org/c/coreboot/+/85666/comment/ffaa1745_392904c8?us… : PS9, Line 65: > If the definition starts getting that complicated, I'd suggest using `DEFINE_BITFIELD` API: […] Done https://review.coreboot.org/c/coreboot/+/85666/comment/fd8195b3_2503baec?us… : PS9, Line 77: 8 > Shouldn't this be 9 if bit[11:9] is for storage id? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85666?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I49ba6f428f55d3aae1b84a4d5ce06bec765caece Gerrit-Change-Number: 85666 Gerrit-PatchSet: 10 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Knox Chiou <knoxchiou(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Knox Chiou <knoxchiou(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sun, 22 Dec 2024 12:02:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

1 0

[M] Change in coreboot[main]: mb/google/rauru: Add support for getting storage id
by Jarried Lin (Code Review) 22 Dec '24

22 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85717?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rauru: Add support for getting storage id ...................................................................... mb/google/rauru: Add support for getting storage id We add storage_id() to read the storage id from auxadc. BUG=b:317009620 TEST=Build pass Change-Id: I036df324cd6644ff69110c6247af29360b83225f Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/Makefile.mk A src/mainboard/google/rauru/boardid.c M src/mainboard/google/rauru/romstage.c A src/mainboard/google/rauru/storage.h 4 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/85717/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I036df324cd6644ff69110c6247af29360b83225f Gerrit-Change-Number: 85717 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Knox Chiou <knoxchiou(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[S] Change in coreboot[main]: mb/google/rauru: Implement SKU ID
by Jarried Lin (Code Review) 22 Dec '24

22 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Knox Chiou, Yidi Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85666?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+1 by Yidi Lin, Verified+1 by build bot (Jenkins) Change subject: mb/google/rauru: Implement SKU ID ...................................................................... mb/google/rauru: Implement SKU ID Retrieve the SKU ID for Rauru via CBI interface. If that failed (or no data found), fall back to ADC channels for SKU ID. TEST=Build pass, boot ok, log show: SKU Code: 0x2 BUG=b:317009620 Change-Id: I49ba6f428f55d3aae1b84a4d5ce06bec765caece Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/boardid.c 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/85666/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/85666?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I49ba6f428f55d3aae1b84a4d5ce06bec765caece Gerrit-Change-Number: 85666 Gerrit-PatchSet: 10 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Knox Chiou <knoxchiou(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Knox Chiou <knoxchiou(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[M] Change in coreboot[main]: util/intelp2m: Move remapping reset source to common
by Maxim (Code Review) 22 Dec '24

22 Dec '24

Maxim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85731?usp=email ) Change subject: util/intelp2m: Move remapping reset source to common ...................................................................... util/intelp2m: Move remapping reset source to common TEST: 'make test' = PASS Change-Id: I315541b12f5f1fdf7c97c2ff8ddd305e30a447cc Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/platforms/adl/macro.go M util/intelp2m/platforms/apl/macro.go M util/intelp2m/platforms/cnl/macro.go M util/intelp2m/platforms/common/common.go M util/intelp2m/platforms/common/macro.go M util/intelp2m/platforms/ebg/macro.go M util/intelp2m/platforms/jsl/macro.go M util/intelp2m/platforms/lbg/macro.go M util/intelp2m/platforms/mtl/macro.go M util/intelp2m/platforms/snr/macro.go M util/intelp2m/platforms/tgl/macro.go 11 files changed, 90 insertions(+), 155 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/85731/1 diff --git a/util/intelp2m/platforms/adl/macro.go b/util/intelp2m/platforms/adl/macro.go index c4a04ed..b53eecb 100644 --- a/util/intelp2m/platforms/adl/macro.go +++ b/util/intelp2m/platforms/adl/macro.go @@ -3,7 +3,6 @@ import ( "strings" - "review.coreboot.org/coreboot.git/util/intelp2m/logs" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bi…" @@ -14,6 +13,13 @@ DW1Mask uint32 = 0b11111101111111111100001111111111 ) +var remapping = common.ResetSources{ + 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, + 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, + 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, + 0b11: bits.RstCfgPWROK << bits.DW0PadRstCfg, +} + type BasePlatform struct { // based on the Cannon Lake platform cnl.BasePlatform @@ -28,32 +34,15 @@ return &p } -// RemapRstSrc() remaps Pad Reset Source Config -func (p *BasePlatform) RemapRstSrc(m *common.Macro) { +// RemapResetSource() remaps Pad Reset Source Config +func (p *BasePlatform) RemapResetSource(m *common.Macro) { if strings.Contains(m.GetPadId(), "GPD") { // See reset map for the Alderlake GPD Group in the Community 2: // https://github.com/coreboot/coreboot/blob/master/src/soc/intel/alderlake/gp… // remmap is not required because it is the same as common. return } - - remapping := map[uint32]uint32{ - 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, - 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, - 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, - 0b11: bits.RstCfgPWROK << bits.DW0PadRstCfg, - } - dw0 := p.GetRegisterDW0() - source, valid := remapping[dw0.GetResetConfig()] - if valid { - dw0.Value &= 0x3fffffff - dw0.Value |= source - } else { - logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b", - m.GetPadId(), dw0, dw0.GetResetConfig()) - } - mask := bits.DW0[bits.DW0PadRstCfg] - dw0.CntrMaskFieldsClear(mask) + p.BasePlatform.UpdateResetSource(m.GetPadId(), remapping) } func (p *BasePlatform) Pull(m *common.Macro) { diff --git a/util/intelp2m/platforms/apl/macro.go b/util/intelp2m/platforms/apl/macro.go index f20acc4..614d0be 100644 --- a/util/intelp2m/platforms/apl/macro.go +++ b/util/intelp2m/platforms/apl/macro.go @@ -25,8 +25,8 @@ return &p } -// RemapRstSrc() remaps Pad Reset Source Config -func (p *BasePlatform) RemapRstSrc(m *common.Macro) {} +// RemapResetSource() remaps Pad Reset Source Config +func (p *BasePlatform) RemapResetSource(m *common.Macro) {} // Pull() adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro func (p *BasePlatform) Pull(m *common.Macro) { diff --git a/util/intelp2m/platforms/cnl/macro.go b/util/intelp2m/platforms/cnl/macro.go index de9bfc7..654fc66 100644 --- a/util/intelp2m/platforms/cnl/macro.go +++ b/util/intelp2m/platforms/cnl/macro.go @@ -15,6 +15,12 @@ DW1Mask uint32 = 0b11111101111111111100001111111111 ) +var remapping = common.ResetSources{ + 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, + 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, + 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, +} + type BasePlatform struct { // based on the Sunrise platform snr.BasePlatform @@ -29,7 +35,7 @@ return &p } -func (p *BasePlatform) RemapRstSrc(m *common.Macro) { +func (p *BasePlatform) RemapResetSource(m *common.Macro) { if strings.Contains(m.GetPadId(), "GPP_A") || strings.Contains(m.GetPadId(), "GPP_B") || strings.Contains(m.GetPadId(), "GPP_G") { @@ -38,23 +44,7 @@ // remmap is not required because it is the same as common. return } - - dw0 := p.GetRegisterDW0() - remapping := map[uint32]uint32{ - 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, - 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, - 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, - } - source, valid := remapping[dw0.GetResetConfig()] - if valid { - dw0.Value &= 0x3fffffff - dw0.Value |= source - } else { - logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b", - m.GetPadId(), dw0, dw0.GetResetConfig()) - } - mask := bits.DW0[bits.DW0PadRstCfg] - dw0.CntrMaskFieldsClear(mask) + p.BasePlatform.UpdateResetSource(m.GetPadId(), remapping) } func (p *BasePlatform) Pull(m *common.Macro) { diff --git a/util/intelp2m/platforms/common/common.go b/util/intelp2m/platforms/common/common.go index 5771984..3a7512b 100644 --- a/util/intelp2m/platforms/common/common.go +++ b/util/intelp2m/platforms/common/common.go @@ -1,9 +1,13 @@ package common import ( + "review.coreboot.org/coreboot.git/util/intelp2m/logs" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bi…" ) +type ResetSources map[uint32]uint32 + type BasePlatform struct { dw0 register.DW0 dw1 register.DW1 @@ -23,3 +27,18 @@ func (p *BasePlatform) GetRegisterDW1() *register.DW1 { return &p.dw1 } + +// UpdateResetSource() remaps the Pad Reset configuration. +// This function can be redefined in each platform based on the current one. +func (p *BasePlatform) UpdateResetSource(pad string, remapping ResetSources) { + dw0 := p.GetRegisterDW0() + mask := bits.DW0[bits.DW0PadRstCfg] + if source, valid := remapping[dw0.GetResetConfig()]; !valid { + logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b", + pad, dw0, dw0.GetResetConfig()) + } else { + dw0.Value &= ^mask + dw0.Value |= source + } + dw0.CntrMaskFieldsClear(mask) +} diff --git a/util/intelp2m/platforms/common/macro.go b/util/intelp2m/platforms/common/macro.go index 0f544ac..76e76e8 100644 --- a/util/intelp2m/platforms/common/macro.go +++ b/util/intelp2m/platforms/common/macro.go @@ -22,7 +22,7 @@ } type PlatformIf interface { - RemapRstSrc(*Macro) + RemapResetSource(*Macro) Pull(*Macro) AddGpiMacro(*Macro) AddGpoMacro(*Macro) @@ -352,7 +352,7 @@ // Generate() generates string of macro func (m *Macro) Generate() string { - m.Platform.RemapRstSrc(m) + m.Platform.RemapResetSource(m) if dw0 := m.Platform.GetRegisterDW0(); dw0.GetPadMode() == 0 { const txDisable uint32 = 0b01 const rxDisable uint32 = 0b10 diff --git a/util/intelp2m/platforms/ebg/macro.go b/util/intelp2m/platforms/ebg/macro.go index 9d3d93e..fa03eae 100644 --- a/util/intelp2m/platforms/ebg/macro.go +++ b/util/intelp2m/platforms/ebg/macro.go @@ -1,7 +1,6 @@ package ebg import ( - "review.coreboot.org/coreboot.git/util/intelp2m/logs" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bi…" @@ -12,6 +11,12 @@ DW1Mask = 0b11111101111111111100001111111111 ) +var remapping = common.ResetSources{ + 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, + 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, + 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, +} + type BasePlatform struct { // based on the Cannon Lake platform cnl.BasePlatform @@ -26,23 +31,8 @@ return &p } -func (p *BasePlatform) RemapRstSrc(m *common.Macro) { - remapping := map[uint32]uint32{ - 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, - 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, - 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, - } - dw0 := p.GetRegisterDW0() - source, valid := remapping[dw0.GetResetConfig()] - if valid { - dw0.Value &= 0x3fffffff - dw0.Value |= source - } else { - logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b", - m.GetPadId(), dw0, dw0.GetResetConfig()) - } - mask := bits.DW0[bits.DW0PadRstCfg] - dw0.CntrMaskFieldsClear(mask) +func (p *BasePlatform) RemapResetSource(m *common.Macro) { + p.BasePlatform.UpdateResetSource(m.GetPadId(), remapping) } func (p *BasePlatform) Pull(m *common.Macro) { diff --git a/util/intelp2m/platforms/jsl/macro.go b/util/intelp2m/platforms/jsl/macro.go index 88e2d97..3a0e7d1b 100644 --- a/util/intelp2m/platforms/jsl/macro.go +++ b/util/intelp2m/platforms/jsl/macro.go @@ -3,7 +3,6 @@ import ( "strings" - "review.coreboot.org/coreboot.git/util/intelp2m/logs" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bi…" @@ -14,6 +13,12 @@ DW1Mask = 0b11111101111111111100001111111111 ) +var remapping = common.ResetSources{ + 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, + 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, + 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, +} + type BasePlatform struct { // based on the Cannon Lake platform cnl.BasePlatform @@ -28,7 +33,7 @@ return &p } -func (p *BasePlatform) RemapRstSrc(m *common.Macro) { +func (p *BasePlatform) RemapResetSource(m *common.Macro) { if strings.Contains(m.GetPadId(), "GPP_F") || strings.Contains(m.GetPadId(), "GPP_B") || strings.Contains(m.GetPadId(), "GPP_A") || @@ -39,23 +44,7 @@ // remmap is not required because it is the same as common. return } - - remapping := map[uint32]uint32{ - 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, - 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, - 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, - } - dw0 := p.GetRegisterDW0() - source, valid := remapping[dw0.GetResetConfig()] - if valid { - dw0.Value &= 0x3fffffff - dw0.Value |= source - } else { - logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b", - m.GetPadId(), dw0, dw0.GetResetConfig()) - } - mask := bits.DW0[bits.DW0PadRstCfg] - dw0.CntrMaskFieldsClear(mask) + p.BasePlatform.UpdateResetSource(m.GetPadId(), remapping) } func (p *BasePlatform) Pull(m *common.Macro) { diff --git a/util/intelp2m/platforms/lbg/macro.go b/util/intelp2m/platforms/lbg/macro.go index ffb1572..9720470 100644 --- a/util/intelp2m/platforms/lbg/macro.go +++ b/util/intelp2m/platforms/lbg/macro.go @@ -1,7 +1,6 @@ package lbg import ( - "review.coreboot.org/coreboot.git/util/intelp2m/logs" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bi…" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" @@ -12,6 +11,12 @@ DW1Mask uint32 = 0b11111101111111111100001111111111 ) +var remapping = common.ResetSources{ + 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, + 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, + 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, +} + type BasePlatform struct { // based on the Sunrise Point platform snr.BasePlatform @@ -26,24 +31,8 @@ return &p } -func (p *BasePlatform) RemapRstSrc(m *common.Macro) { - dw0 := p.GetRegisterDW0() - remapping := map[uint32]uint32{ - 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, - 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, - 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, - } - source, valid := remapping[dw0.GetResetConfig()] - if valid { - // dw0.SetResetConfig(resetsrc) - dw0.Value &= 0x3fffffff - dw0.Value |= source - } else { - logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b", - m.GetPadId(), dw0, dw0.GetResetConfig()) - } - mask := bits.DW0[bits.DW0PadRstCfg] - dw0.CntrMaskFieldsClear(mask) +func (p *BasePlatform) RemapResetSource(m *common.Macro) { + p.BasePlatform.UpdateResetSource(m.GetPadId(), remapping) } func (p *BasePlatform) Pull(m *common.Macro) { diff --git a/util/intelp2m/platforms/mtl/macro.go b/util/intelp2m/platforms/mtl/macro.go index 0060f53..705f1ea 100644 --- a/util/intelp2m/platforms/mtl/macro.go +++ b/util/intelp2m/platforms/mtl/macro.go @@ -3,7 +3,6 @@ import ( "strings" - "review.coreboot.org/coreboot.git/util/intelp2m/logs" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bi…" @@ -14,6 +13,13 @@ DW1Mask = 0b11111101111111111100001111111111 ) +var remapping = common.ResetSources{ + 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, + 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, + 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, + 0b11: bits.RstCfgPWROK << bits.RstCfgPWROK, +} + type BasePlatform struct { // based on the Cannon Lake platform cnl.BasePlatform @@ -28,31 +34,14 @@ return &p } -func (p *BasePlatform) RemapRstSrc(m *common.Macro) { +func (p *BasePlatform) RemapResetSource(m *common.Macro) { if strings.Contains(m.GetPadId(), "GPD") { // See reset map for the MeteorLake GPD group at // https://github.com/coreboot/coreboot/blob/master/src/soc/intel/meteorlake/g… // remmap is not required because it is the same as common. return } - - remapping := map[uint32]uint32{ - 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, - 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, - 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, - 0b11: bits.RstCfgPWROK << bits.RstCfgPWROK, - } - dw0 := p.GetRegisterDW0() - source, valid := remapping[dw0.GetResetConfig()] - if valid { - dw0.Value &= 0x3fffffff - dw0.Value |= source - } else { - logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b", - m.GetPadId(), dw0, dw0.GetResetConfig()) - } - mask := bits.DW0[bits.DW0PadRstCfg] - dw0.CntrMaskFieldsClear(mask) + p.BasePlatform.UpdateResetSource(m.GetPadId(), remapping) } func (p *BasePlatform) Pull(m *common.Macro) { diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go index 9a4ace4..fb9471c 100644 --- a/util/intelp2m/platforms/snr/macro.go +++ b/util/intelp2m/platforms/snr/macro.go @@ -14,6 +14,12 @@ DW1Mask uint32 = 0b11111101111111111100001111111111 ) +var remapping = common.ResetSources{ + 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, + 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, + 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, +} + type BasePlatform struct { common.BasePlatform } @@ -28,29 +34,14 @@ } // RemmapRstSrc() remaps Pad Reset Source Config -func (p *BasePlatform) RemapRstSrc(m *common.Macro) { +func (p *BasePlatform) RemapResetSource(m *common.Macro) { if strings.Contains(m.GetPadId(), "GPD") { // See reset map for the Sunrise GPD Group in the Community 2: // https://github.com/coreboot/coreboot/blob/master/src/soc/intel/skylake/gpio… // remmap is not required because it is the same as common. return } - - dw0 := p.GetRegisterDW0() - remapping := map[uint32]uint32{ - 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, - 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, - 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, - } - - if source, valid := remapping[dw0.GetResetConfig()]; valid { - dw0.Value &= 0x3fffffff - dw0.Value |= source - } else { - logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b", - m.GetPadId(), dw0, dw0.GetResetConfig()) - } - dw0.CntrMaskFieldsClear(bits.DW0[bits.DW0PadRstCfg]) + p.BasePlatform.UpdateResetSource(m.GetPadId(), remapping) } // Pull() adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro diff --git a/util/intelp2m/platforms/tgl/macro.go b/util/intelp2m/platforms/tgl/macro.go index f316444..ddc7c86 100644 --- a/util/intelp2m/platforms/tgl/macro.go +++ b/util/intelp2m/platforms/tgl/macro.go @@ -3,7 +3,6 @@ import ( "strings" - "review.coreboot.org/coreboot.git/util/intelp2m/logs" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bi…" @@ -14,6 +13,12 @@ DW1Mask = 0b11111101111111111100001111111111 ) +var remapping = common.ResetSources{ + 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, + 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, + 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, +} + type BasePlatform struct { // based on the Cannon Lake platform cnl.BasePlatform @@ -28,30 +33,14 @@ return &p } -func (p *BasePlatform) RemapRstSrc(m *common.Macro) { +func (p *BasePlatform) RemapResetSource(m *common.Macro) { if strings.Contains(m.GetPadId(), "GPD") { // See reset map for the TigerLake Community 2: // https://github.com/coreboot/coreboot/blob/master/src/soc/intel/tigerlake/gp… // remmap is not required because it is the same as common. return } - - remapping := map[uint32]uint32{ - 0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg, - 0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg, - 0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg, - } - dw0 := p.GetRegisterDW0() - source, valid := remapping[dw0.GetResetConfig()] - if valid { - dw0.Value &= 0x3fffffff - dw0.Value |= source - } else { - logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b", - m.GetPadId(), dw0, dw0.GetResetConfig()) - } - mask := bits.DW0[bits.DW0PadRstCfg] - dw0.CntrMaskFieldsClear(mask) + p.BasePlatform.UpdateResetSource(m.GetPadId(), remapping) } func (p *BasePlatform) Pull(m *common.Macro) { -- To view, visit https://review.coreboot.org/c/coreboot/+/85731?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I315541b12f5f1fdf7c97c2ff8ddd305e30a447cc Gerrit-Change-Number: 85731 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com>

1 0

[XS] Change in coreboot[main]: [test] add some Wextra's warnings
by Elyes Haouas (Code Review) 22 Dec '24

22 Dec '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85730?usp=email ) Change subject: [test] add some Wextra's warnings ...................................................................... [test] add some Wextra's warnings https://gcc.gnu.org/onlinedocs/gcc-14.2.0/gcc/Warning-Options.html#index-W Change-Id: Iaf8516b736378d0a33dee59d6e2b98e78f48e756 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.mk 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/85730/1 diff --git a/Makefile.mk b/Makefile.mk index ca79d05..10f0bc8 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -509,7 +509,10 @@ CFLAGS_common += -nostdinc CFLAGS_common += -std=gnu11 CFLAGS_common += -nostdlib -CFLAGS_common += -Wall +CFLAGS_common += -Wall -Wuninitialized -Wtype-limits -Wstring-compare +CFLAGS_common += -Woverride-init -Wmissing-parameter-type -Wmissing-field-initializers +CFLAGS_common += -Wignored-qualifiers -Wexpansion-to-defined -Wenum-conversion +CFLAGS_common += -Wclobbered -Wcalloc-transposed-args CFLAGS_common += -Wundef CFLAGS_common += -Wstrict-prototypes CFLAGS_common += -Wmissing-prototypes -- To view, visit https://review.coreboot.org/c/coreboot/+/85730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf8516b736378d0a33dee59d6e2b98e78f48e756 Gerrit-Change-Number: 85730 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[M] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Enable FPS
by Subrata Banik (Code Review) 22 Dec '24

22 Dec '24

Attention is currently required from: Pranava Y N. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85687?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Enable FPS ...................................................................... Patch Set 5: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/85687?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifced5c779407b4ffcc69a7ed1297704def09b554 Gerrit-Change-Number: 85687 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 22 Dec 2024 07:48:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: [test] upgrade GCC to 15-20241215 Snapshot
by Elyes Haouas (Code Review) 22 Dec '24

22 Dec '24

Attention is currently required from: Martin L Roth. Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85729?usp=email ) Change subject: [test] upgrade GCC to 15-20241215 Snapshot ...................................................................... [test] upgrade GCC to 15-20241215 Snapshot Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-15-20241215_gnat.patch R util/crossgcc/patches/gcc-15-20241215_libcpp.patch R util/crossgcc/patches/gcc-15-20241215_libgcc.patch R util/crossgcc/patches/gcc-15-20241215_musl_poisoned_calloc.patch R util/crossgcc/patches/gcc-15-20241215_rv32iafc.patch D util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-15-20241215.tar.xz.cksum 9 files changed, 3 insertions(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85729/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 9dbd7ae..da09b07 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -38,7 +38,7 @@ GMP_VERSION=6.3.0 MPFR_VERSION=4.2.1 MPC_VERSION=1.3.1 -GCC_VERSION=14.2.0 +GCC_VERSION=15-20241215 LIBSTDCXX_VERSION="${GCC_VERSION}" BINUTILS_VERSION=2.43.1 IASL_VERSION=20241212 @@ -74,7 +74,7 @@ GMP_BASE_URL="https://ftpmirror.gnu.org/gmp" MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" -GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" +GCC_BASE_URL="https://gcc.gnu.org/pub/gcc/snapshots/15-20241215" LIBSTDCXX_BASE_URL="${GCC_BASE_URL}" BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" IASL_BASE_URL="https://github.com/acpica/acpica/releases/download/R2024_12_12" diff --git a/util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch b/util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch deleted file mode 100644 index d446025..0000000 --- a/util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 41a82fb711f3637b4b7f57756492b628058f9d5f Mon Sep 17 00:00:00 2001 -From: Harshit Sharma <harshitsharmajs(a)gmail.com> -Date: Fri, 10 Jul 2020 13:06:08 -0700 -Subject: [PATCH] crossgcc: Enable GCC to get asan shadow offset at runtime - -Unlike Linux kernel which has a static shadow region layout, we have multiple stages in -coreboot and thus require a different shadow offset address. Unfortunately, GCC currently -only supports adding a static shadow offset at compile time using -fasan-shadow-offset flag. - -For this reason, we enable GCC to determine asan shadow offset address at runtime using a -callback function named __asan_shadow_offset(). This supersedes the need to specify this -address at compile time. GCC then makes use of this shadow offset to protect stack buffers -by inserting red zones around them. - -Some other benefits of having this GCC patch are: -a. We can place the shadow region in a separate linker section with all its advantages like - automatic fit insurance. This ensures if a platform doesn't have enough memory space to - hold shadow region, the build will fail. (However, if we use a fixed shadow offset on a - platform that actually doesn't have enough memory, it may still build without any errors.) -b. We don't modify the memory layout compared to the current one, as we are placing the - shadow region at the end of the space already occupied by the program. -c. We can be much more flexible later if needed (thinking of other stages like bootblock). -d. Since we are appending the shadow buffer to the region already occupied, we make efficient - use of the limited memory available which is highly beneficial when using cache as ram. - -Further, we have made sure that if you compile you tree with ASan enabled but missed this -patch, it will end up in the following compilation error: -"invalid --param name 'asan-use-shadow-offset-callback'" -So, you cannot accidentally enable the feature without having your compiler patched. - -[pgeorgi: Updated for gcc 11.1] - -Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> -Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> - -diff --git a/gcc/asan.c b/gcc/asan.c -index 235e21947..713bf994d 100644 ---- a/gcc/asan.cc -+++ b/gcc/asan.cc -@@ -1389,13 +1389,28 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb, - TREE_ASM_WRITTEN (decl) = 1; - TREE_ASM_WRITTEN (id) = 1; - emit_move_insn (mem, expand_normal (build_fold_addr_expr (decl))); -- shadow_base = expand_binop (Pmode, lshr_optab, base, -- gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), -- NULL_RTX, 1, OPTAB_DIRECT); -- shadow_base -- = plus_constant (Pmode, shadow_base, -- asan_shadow_offset () -- + (base_align_bias >> ASAN_SHADOW_SHIFT)); -+ if (param_asan_use_shadow_offset_callback) { -+ rtx addr, shadow_offset_rtx; -+ ret = init_one_libfunc ("__asan_shadow_offset"); -+ addr = convert_memory_address (ptr_mode, base); -+ ret = emit_library_call_value (ret, NULL_RTX, LCT_NORMAL, ptr_mode, -+ addr, ptr_mode); -+ shadow_offset_rtx = convert_memory_address (Pmode, ret); -+ shadow_base = expand_binop (Pmode, lshr_optab, base, -+ gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), -+ NULL_RTX, 1, OPTAB_DIRECT); -+ shadow_base = expand_binop (Pmode, add_optab, shadow_base, -+ shadow_offset_rtx, NULL_RTX, 1, OPTAB_LIB_WIDEN); -+ shadow_base = plus_constant (Pmode, shadow_base, -+ (base_align_bias >> ASAN_SHADOW_SHIFT)); -+ } else { -+ shadow_base = expand_binop (Pmode, lshr_optab, base, -+ gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), -+ NULL_RTX, 1, OPTAB_DIRECT); -+ shadow_base = plus_constant (Pmode, shadow_base, -+ asan_shadow_offset () -+ + (base_align_bias >> ASAN_SHADOW_SHIFT)); -+ } - gcc_assert (asan_shadow_set != -1 - && (ASAN_RED_ZONE_SIZE >> ASAN_SHADOW_SHIFT) == 4); - shadow_mem = gen_rtx_MEM (SImode, shadow_base); ---- gcc-11.1.0/gcc/params.opt~ 2021-05-11 09:02:51.897508677 +0200 -+++ gcc-11.1.0/gcc/params.opt 2021-05-11 09:10:43.692610696 +0200 -@@ -50,6 +50,10 @@ - Common Joined UInteger Var(param_asan_instrumentation_with_call_threshold) Init(7000) Param Optimization - Use callbacks instead of inline code if number of accesses in function becomes greater or equal to this number. - -+-param=asan-use-shadow-offset-callback= -+Common Joined UInteger Var(param_asan_use_shadow_offset_callback) Init(0) IntegerRange(0, 1) Param Optimization -+Use shadow offset callback function at runtime instead of fixed value at compile time at the cost of runtime overhead. -+ - -param=asan-memintrin= - Common Joined UInteger Var(param_asan_memintrin) Init(1) IntegerRange(0, 1) Param Optimization - Enable asan builtin functions protection. diff --git a/util/crossgcc/patches/gcc-14.2.0_gnat.patch b/util/crossgcc/patches/gcc-15-20241215_gnat.patch similarity index 100% rename from util/crossgcc/patches/gcc-14.2.0_gnat.patch rename to util/crossgcc/patches/gcc-15-20241215_gnat.patch diff --git a/util/crossgcc/patches/gcc-14.2.0_libcpp.patch b/util/crossgcc/patches/gcc-15-20241215_libcpp.patch similarity index 100% rename from util/crossgcc/patches/gcc-14.2.0_libcpp.patch rename to util/crossgcc/patches/gcc-15-20241215_libcpp.patch diff --git a/util/crossgcc/patches/gcc-14.2.0_libgcc.patch b/util/crossgcc/patches/gcc-15-20241215_libgcc.patch similarity index 100% rename from util/crossgcc/patches/gcc-14.2.0_libgcc.patch rename to util/crossgcc/patches/gcc-15-20241215_libgcc.patch diff --git a/util/crossgcc/patches/gcc-14.2.0_musl_poisoned_calloc.patch b/util/crossgcc/patches/gcc-15-20241215_musl_poisoned_calloc.patch similarity index 100% rename from util/crossgcc/patches/gcc-14.2.0_musl_poisoned_calloc.patch rename to util/crossgcc/patches/gcc-15-20241215_musl_poisoned_calloc.patch diff --git a/util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch b/util/crossgcc/patches/gcc-15-20241215_rv32iafc.patch similarity index 100% rename from util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch rename to util/crossgcc/patches/gcc-15-20241215_rv32iafc.patch diff --git a/util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum b/util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum deleted file mode 100644 index f81c535..0000000 --- a/util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -d91ecc3d20ce6298bd95f9b09cc51dc6d3c73ae3 tarballs/gcc-14.2.0.tar.xz diff --git a/util/crossgcc/sum/gcc-15-20241215.tar.xz.cksum b/util/crossgcc/sum/gcc-15-20241215.tar.xz.cksum new file mode 100644 index 0000000..88592d5 --- /dev/null +++ b/util/crossgcc/sum/gcc-15-20241215.tar.xz.cksum @@ -0,0 +1 @@ +cf3899e0c1bc7f9ea2b4b21bfcb21ecc6e49372c tarballs/gcc-15-20241215.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/85729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Gerrit-Change-Number: 85729 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>

1 0

[S] Change in coreboot[main]: [test] upgrade LLVM to 19.1.5
by Elyes Haouas (Code Review) 22 Dec '24

22 Dec '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85728?usp=email ) Change subject: [test] upgrade LLVM to 19.1.5 ...................................................................... [test] upgrade LLVM to 19.1.5 Change-Id: I6852770d7bbfbd80bbe401d28917c4dcf416562a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/clang-18.1.8.src_x86_baremetal.patch D util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/clang-19.1.5.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-19.1.5.src.tar.xz.cksum D util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/cmake-19.1.5.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-19.1.5.src.tar.xz.cksum D util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/libunwind-19.1.5.src.tar.xz.cksum D util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/lld-19.1.5.src.tar.xz.cksum D util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/llvm-19.1.5.src.tar.xz.cksum 16 files changed, 8 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/85728/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index a751003..9dbd7ae 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -43,7 +43,7 @@ BINUTILS_VERSION=2.43.1 IASL_VERSION=20241212 # CLANG version number -CLANG_VERSION=18.1.8 +CLANG_VERSION=19.1.5 CMAKE_VERSION=3.31.3 NASM_VERSION=2.16.03 diff --git a/util/crossgcc/patches/clang-18.1.8.src_x86_baremetal.patch b/util/crossgcc/patches/clang-18.1.8.src_x86_baremetal.patch deleted file mode 100644 index 61c608c..0000000 --- a/util/crossgcc/patches/clang-18.1.8.src_x86_baremetal.patch +++ /dev/null @@ -1,29 +0,0 @@ -diff --git a/lib/Driver/ToolChains/BareMetal.cpp b/lib/Driver/ToolChains/BareMetal.cpp -index 852e0442..eb84a785 100644 ---- a/lib/Driver/ToolChains/BareMetal.cpp -+++ b/lib/Driver/ToolChains/BareMetal.cpp -@@ -169,6 +169,12 @@ static bool isPPCBareMetal(const llvm::Triple &Triple) { - Triple.getEnvironment() == llvm::Triple::EABI; - } - -+/// Is the triple x86_32 or x86_64 -*-none-elf? -+static bool isX86BareMetal(const llvm::Triple &Triple) { -+ return Triple.isX86() && Triple.getOS() == llvm::Triple::UnknownOS && -+ Triple.getEnvironmentName() == "elf"; -+} -+ - static void findMultilibsFromYAML(const ToolChain &TC, const Driver &D, - StringRef MultilibPath, const ArgList &Args, - DetectedMultilibs &Result) { -@@ -234,9 +240,10 @@ void BareMetal::findMultilibs(const Driver &D, const llvm::Triple &Triple, - - bool BareMetal::handlesTarget(const llvm::Triple &Triple) { - return isARMBareMetal(Triple) || isAArch64BareMetal(Triple) || -- isRISCVBareMetal(Triple) || isPPCBareMetal(Triple); -+ isRISCVBareMetal(Triple) || isPPCBareMetal(Triple) || isX86BareMetal(Triple); - } - -+ - Tool *BareMetal::buildLinker() const { - return new tools::baremetal::Linker(*this); - } diff --git a/util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum deleted file mode 100644 index a517ab9..0000000 --- a/util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -581e929ba0d9fafc555081ab18d8c3fdf4478ac2 tarballs/clang-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/clang-19.1.5.src.tar.xz.cksum b/util/crossgcc/sum/clang-19.1.5.src.tar.xz.cksum new file mode 100644 index 0000000..e47ebce --- /dev/null +++ b/util/crossgcc/sum/clang-19.1.5.src.tar.xz.cksum @@ -0,0 +1 @@ +97d171d45738b07788864b79304d0128feca0596 tarballs/clang-19.1.5.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum deleted file mode 100644 index 6b9b67c..0000000 --- a/util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -32923b812700526b76451384e4662ca45360d564 tarballs/clang-tools-extra-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-19.1.5.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-19.1.5.src.tar.xz.cksum new file mode 100644 index 0000000..6ef2059 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-19.1.5.src.tar.xz.cksum @@ -0,0 +1 @@ +a445ba274276f3fa470ae765e774b2ed922d98e8 tarballs/clang-tools-extra-19.1.5.src.tar.xz diff --git a/util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum deleted file mode 100644 index d0e6331..0000000 --- a/util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -1ea03e355b705b4cada3051bd7301a57daa19283 tarballs/cmake-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/cmake-19.1.5.src.tar.xz.cksum b/util/crossgcc/sum/cmake-19.1.5.src.tar.xz.cksum new file mode 100644 index 0000000..b6ada93 --- /dev/null +++ b/util/crossgcc/sum/cmake-19.1.5.src.tar.xz.cksum @@ -0,0 +1 @@ +7bf3c141bd5797ce6885b4b52c9dcab778c41e40 tarballs/cmake-19.1.5.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum deleted file mode 100644 index 711ef35..0000000 --- a/util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -6ecbfa5516b60adb4e4e60f991b0d8ddf5aab12a tarballs/compiler-rt-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-19.1.5.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-19.1.5.src.tar.xz.cksum new file mode 100644 index 0000000..ceccaa9 --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-19.1.5.src.tar.xz.cksum @@ -0,0 +1 @@ +1caa4598ec1752afe537a63e797a9b0fb2819266 tarballs/compiler-rt-19.1.5.src.tar.xz diff --git a/util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum deleted file mode 100644 index d3819e3..0000000 --- a/util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -5bee6cd2847f6d468861c78a21236e1c6fdc8374 tarballs/libunwind-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/libunwind-19.1.5.src.tar.xz.cksum b/util/crossgcc/sum/libunwind-19.1.5.src.tar.xz.cksum new file mode 100644 index 0000000..6423faf --- /dev/null +++ b/util/crossgcc/sum/libunwind-19.1.5.src.tar.xz.cksum @@ -0,0 +1 @@ +35a196c5fd4e73a3a4edba8518e07c2ed7c99d69 tarballs/libunwind-19.1.5.src.tar.xz diff --git a/util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum deleted file mode 100644 index 490a835..0000000 --- a/util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -1cf1fa9848b05a07d3d52e69949d44003f2ab2af tarballs/lld-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/lld-19.1.5.src.tar.xz.cksum b/util/crossgcc/sum/lld-19.1.5.src.tar.xz.cksum new file mode 100644 index 0000000..7634bd5 --- /dev/null +++ b/util/crossgcc/sum/lld-19.1.5.src.tar.xz.cksum @@ -0,0 +1 @@ +10307ae0b5cab4fb8b9d2daf1a58230af7ee104b tarballs/lld-19.1.5.src.tar.xz diff --git a/util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum deleted file mode 100644 index 4845fb5..0000000 --- a/util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -f9befa4cbef3f688ab48fca42449e13c5bcb872d tarballs/llvm-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/llvm-19.1.5.src.tar.xz.cksum b/util/crossgcc/sum/llvm-19.1.5.src.tar.xz.cksum new file mode 100644 index 0000000..2c90383 --- /dev/null +++ b/util/crossgcc/sum/llvm-19.1.5.src.tar.xz.cksum @@ -0,0 +1 @@ +11638313aa790f259ba8f18f83833d9b7a451f33 tarballs/llvm-19.1.5.src.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/85728?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6852770d7bbfbd80bbe401d28917c4dcf416562a Gerrit-Change-Number: 85728 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2024