coreboot-gerrit December 2024

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6316 driver
by Yidi Lin (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85630?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6316 driver ...................................................................... Patch Set 7: (8 comments) File src/soc/mediatek/common/mt6316.c: https://review.coreboot.org/c/coreboot/+/85630/comment/151a649d_0b20fb0a?us… : PS7, Line 48: 0x%x %#x https://review.coreboot.org/c/coreboot/+/85630/comment/ac75140a_679f53b0?us… : PS7, Line 78: %u `%u\n` https://review.coreboot.org/c/coreboot/+/85630/comment/d7a352cc_65ae76b3?us… : PS7, Line 106: %u \n https://review.coreboot.org/c/coreboot/+/85630/comment/7cb4d82f_d9aa2d12?us… : PS7, Line 132: %u `%u\n` https://review.coreboot.org/c/coreboot/+/85630/comment/ec1a747a_99dfff01?us… : PS7, Line 158: -1 false https://review.coreboot.org/c/coreboot/+/85630/comment/b55b1b50_3d2a7c3c?us… : PS7, Line 170: { remove https://review.coreboot.org/c/coreboot/+/85630/comment/9e0760da_af457720?us… : PS7, Line 184: : printk(BIOS_INFO, "[%s][MT6316_6]CHIP ID = 0x%x\n", __func__, : mt6316_read_field(SPMI_SLAVE_6, MT6316_PMIC_SWCID_H_ADDR, 0xFF, 0x0)); : printk(BIOS_INFO, "[%s][MT6316_7]CHIP ID = 0x%x\n", __func__, : mt6316_read_field(SPMI_SLAVE_7, MT6316_PMIC_SWCID_H_ADDR, 0xFF, 0x0)); : printk(BIOS_INFO, "[%s][MT6316_8]CHIP ID = 0x%x\n", __func__, : mt6316_read_field(SPMI_SLAVE_8, MT6316_PMIC_SWCID_H_ADDR, 0xFF, 0x0)); : printk(BIOS_INFO, "[%s][MT6316_15]CHIP ID = 0x%x\n", __func__, : mt6316_read_field(SPMI_SLAVE_15, MT6316_PMIC_SWCID_H_ADDR, 0xFF, 0x0)); ``` for (int i = 0; i < ARRAY_SIZE(mt6316_slave_id); i++) printk(BIOS_INOF, "%s: MT6316_%d: CHIP ID = %#x", __func__, mt6316_slave_id[i] mt6316_read_field(mt6316_slave_id[i], MT6316_PMIC_SWCID_H_ADDR, 0xFF, 0x0));); ``` https://review.coreboot.org/c/coreboot/+/85630/comment/6eaedc9d_70d1e469?us… : PS7, Line 199: { remove -- To view, visit https://review.coreboot.org/c/coreboot/+/85630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Gerrit-Change-Number: 85630 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 04:25:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6316 driver
by Hope Wang (Code Review) 23 Dec '24

23 Dec '24

1 0

[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6316 driver
by Jarried Lin (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85630?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+1 by Yidi Lin Change subject: soc/mediatek/mt8196: Add PMIC MT6316 driver ...................................................................... soc/mediatek/mt8196: Add PMIC MT6316 driver Add MT6316 driver in SoC folder. TEST=Build pass BUG=b:317009620 Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/mt6316.h A src/soc/mediatek/common/mt6316.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6316.c 4 files changed, 1,162 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/85630/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Gerrit-Change-Number: 85630 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6316 driver
by Yidi Lin (Code Review) 23 Dec '24

23 Dec '24

1 0

[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6316 driver
by Jarried Lin (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85630?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6316 driver ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85630/comment/ac26f235_6c8c9a6a?us… : PS3, Line 9: Add MT6316 driver in SoC folder > Missing `. […] Done File src/soc/mediatek/mt8196/mt6316.c: https://review.coreboot.org/c/coreboot/+/85630/comment/a8b824fe_6d3dabc1?us… : PS3, Line 6: MeidaTek > MediaTek Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Gerrit-Change-Number: 85630 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 03:00:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6316 driver
by Jarried Lin (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85630?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add PMIC MT6316 driver ...................................................................... soc/mediatek/mt8196: Add PMIC MT6316 driver Add MT6316 driver in SoC folder. TEST=Build pass BUG=b:317009620 Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/mt6316.h A src/soc/mediatek/common/mt6316.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6316.c 4 files changed, 1,162 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/85630/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Gerrit-Change-Number: 85630 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6316 driver
by Hope Wang (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hope Wang has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85630?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6316 driver ...................................................................... Patch Set 5: (16 comments) File src/soc/mediatek/common/include/soc/mt6316.h: https://review.coreboot.org/c/coreboot/+/85630/comment/13674336_0582257d?us… : PS3, Line 21: max > MAX Done File src/soc/mediatek/common/mt6316.c: https://review.coreboot.org/c/coreboot/+/85630/comment/91b654e7_e1dc025f?us… : PS2, Line 14: assert(pmif_arb); : pmif_arb->read(pmif_arb, slvid, reg, data); > Is `data` supposed to be `u8`? There is no read api for u8, how about u16? File src/soc/mediatek/common/mt6316.c: https://review.coreboot.org/c/coreboot/+/85630/comment/5b005af7_1a1bbb91?us… : PS3, Line 12: enum spmi_slave > Please consistently use either `u32` or `enum spmi_slave` in all of the functions. Done https://review.coreboot.org/c/coreboot/+/85630/comment/15019cfe_285f34dc?us… : PS3, Line 77: ( > remove Done https://review.coreboot.org/c/coreboot/+/85630/comment/b8b4c835_9b0aed0d?us… : PS3, Line 78: ( > remove Done https://review.coreboot.org/c/coreboot/+/85630/comment/f742cef5_89c2f2c0?us… : PS3, Line 107: ( > remove Done https://review.coreboot.org/c/coreboot/+/85630/comment/2f2af29c_aa175614?us… : PS3, Line 108: ( > remove Done https://review.coreboot.org/c/coreboot/+/85630/comment/7bfa628b_06b642b0?us… : PS3, Line 111: u8 > Is this supposed to be a boolean? Done https://review.coreboot.org/c/coreboot/+/85630/comment/4d1ef617_386ef0be?us… : PS3, Line 160: con9 > What does con9 mean? The register name of address 0x222 is TEST_CON9 https://review.coreboot.org/c/coreboot/+/85630/comment/e9f8d670_819189c1?us… : PS3, Line 164: 0x222 > 0x222 is `reg`, not the mask. Please define a macro for it. Yes, 0x222 is the register of test_con9, has 8 bit, only need to set bit5. https://review.coreboot.org/c/coreboot/+/85630/comment/7dd2b072_720a9681?us… : PS3, Line 169: reg_val_6 > +1. Please change the type of `data` to u8 for both `mt6316_read` and `mt6316_write`. Yes, read ont byte, read api do not have u8 but only u16, how about mt6316_read8 get u16 from pmif_arb->read16 and return u8 implicitly. https://review.coreboot.org/c/coreboot/+/85630/comment/34213a5b_317ef605?us… : PS3, Line 181: /* for N*/ > remove. […] N means project liber https://review.coreboot.org/c/coreboot/+/85630/comment/25290ccd_961f1b81?us… : PS3, Line 202: mt6316_wdt_enable(SPMI_SLAVE_6); : mt6316_wdt_enable(SPMI_SLAVE_7); : mt6316_wdt_enable(SPMI_SLAVE_8); : mt6316_wdt_enable(SPMI_SLAVE_15); : > Define a global static const array for `[SPMI_SLAVE_6, SPMI_SLAVE_7, SPMI_SLAVE_8, SPMI_SLAVE_15]` a […] mt6316_init_setting not have only slave id, but also init_setting array, do we need to optimize these arrays? File src/soc/mediatek/mt8196/mt6316.c: https://review.coreboot.org/c/coreboot/+/85630/comment/efa4f888_37611d3c?us… : PS3, Line 885: for (int i = 0; i < ARRAY_SIZE(init_setting_s8); i++) > Can we make the order consistent: 6, 7, 8, 15 (instead of 8, 6, 7, 15)? Done https://review.coreboot.org/c/coreboot/+/85630/comment/ef476d08_1195dfc1?us… : PS3, Line 886: mt6316_write_field(SPMI_SLAVE_8, : init_setting_s8[i].addr, init_setting_s8[i].val, : init_setting_s8[i].mask, init_setting_s8[i].shift); > Extract it to […] Done https://review.coreboot.org/c/coreboot/+/85630/comment/c4c3723b_1c2ff306?us… : PS3, Line 889: printk(BIOS_INFO, "%s S8 done\n", __func__); > Do we really need these logs? `mt6316_write_field` won't fail, so these logs will always be printed. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Gerrit-Change-Number: 85630 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 02:53:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: commonlib: Refactor CSE sync eventLog
by Subrata Banik (Code Review) 23 Dec '24

23 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85622?usp=email ) Change subject: commonlib: Refactor CSE sync eventLog ...................................................................... commonlib: Refactor CSE sync eventLog This patch enhances the readability of the CSE sync event ELOG_TYPE_FW_CSE_SYNC by updating the event naming from "early and late bootstage" to "pre and post memory." BUG=b:379585294 TEST=boot verified on google/rex0 and google/rex64 without change: ``` rex-rev3 ~ # elogtool list rex64-rev3 ~ # /media/usb/elogtool list 3 | 2024-01-01 22:25:59-0800 | Firmware CSE sync | Late CSE Sync ``` with change: ``` rex64-rev3 ~ # elogtool list 3 | 2024-12-17 02:22:36-0800 | Firmware CSE sync | Post RAM CSE Sync ``` Change-Id: Ia5db3ffb43b2ceac821de72ef9e88ed62e617d41 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85622 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/commonlib/bsd/include/commonlib/bsd/elog.h M src/soc/intel/common/block/cse/cse_lite.c M util/cbfstool/eventlog.c 3 files changed, 6 insertions(+), 6 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/commonlib/bsd/include/commonlib/bsd/elog.h b/src/commonlib/bsd/include/commonlib/bsd/elog.h index e1c8f5d..f7dc4a1 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/elog.h +++ b/src/commonlib/bsd/include/commonlib/bsd/elog.h @@ -385,8 +385,8 @@ * Events related to CSE sync */ #define ELOG_TYPE_FW_CSE_SYNC 0xbd -#define ELOG_FW_EARLY_CSE_SYNC 0x0 -#define ELOG_FW_LATE_CSE_SYNC 0x1 +#define ELOG_FW_PRE_RAM_CSE_SYNC 0x0 +#define ELOG_FW_POST_RAM_CSE_SYNC 0x1 #define ELOG_FW_CSE_SYNC_AT_PAYLOAD 0x2 /* Only the 7-LSB are used for size */ diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 00b5de6..5647a36 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -806,8 +806,8 @@ return CB_ERR; printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n"); - elog_add_event_byte(ELOG_TYPE_FW_CSE_SYNC, ENV_RAMSTAGE ? ELOG_FW_LATE_CSE_SYNC : - ELOG_FW_EARLY_CSE_SYNC); + elog_add_event_byte(ELOG_TYPE_FW_CSE_SYNC, ENV_RAMSTAGE ? ELOG_FW_POST_RAM_CSE_SYNC : + ELOG_FW_PRE_RAM_CSE_SYNC); return CB_SUCCESS; } diff --git a/util/cbfstool/eventlog.c b/util/cbfstool/eventlog.c index 0227683..b9a3706 100644 --- a/util/cbfstool/eventlog.c +++ b/util/cbfstool/eventlog.c @@ -485,8 +485,8 @@ }; static const struct valstr cse_sync_path_types[] = { - {ELOG_FW_EARLY_CSE_SYNC, "Early CSE Sync"}, - {ELOG_FW_LATE_CSE_SYNC, "Late CSE Sync"}, + {ELOG_FW_PRE_RAM_CSE_SYNC, "Pre-RAM CSE Sync"}, + {ELOG_FW_POST_RAM_CSE_SYNC, "Post-RAM CSE Sync"}, {ELOG_FW_CSE_SYNC_AT_PAYLOAD, "CSE Sync at Payload"}, {0, NULL}, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/85622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5db3ffb43b2ceac821de72ef9e88ed62e617d41 Gerrit-Change-Number: 85622 Gerrit-PatchSet: 3 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: commonlib: Refactor CSE sync eventLog
by Subrata Banik (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal. Subrata Banik has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/85622?usp=email ) Change subject: commonlib: Refactor CSE sync eventLog ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85622/comment/a189e627_57652994?us… : PS2, Line 24: Post RAM CSE Sync > This is not a hand editing, but exact output with patch update#1". […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5db3ffb43b2ceac821de72ef9e88ed62e617d41 Gerrit-Change-Number: 85622 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 01:57:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Dinesh Gehlot <digehlot(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brya: Adjust EC memory map range to support indexed IO
by Subrata Banik (Code Review) 23 Dec '24

23 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85547?usp=email ) Change subject: mb/google/brya: Adjust EC memory map range to support indexed IO ...................................................................... mb/google/brya: Adjust EC memory map range to support indexed IO Adjust the EC memory map range for indexed IO access in trulo variant from 0x900 to 0x380 BUG=b:379224648 TEST= able to build nissa/trulo. Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Signed-off-by: Jayvik Desai <jayvik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85547 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb 1 file changed, 5 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb index 3090bb5..a93c669 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb @@ -8,8 +8,11 @@ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + # For platform selects EC_GOOGLE_CHROMEEC_MEMMAP_INDEXED_IO + # EC memmap range is in 0x380-0x381 + # For others + # EC memmap range is in 0x900-0x9ff + register "gen3_dec" = "CONFIG(EC_GOOGLE_CHROMEEC_MEMMAP_INDEXED_IO) ? (0x00010001 | CONFIG_EC_GOOGLE_CHROMEEC_MEMMAP_INDEXED_IO_PORT) : 0x00fc0901" register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Gerrit-Change-Number: 85547 Gerrit-PatchSet: 8 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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coreboot-gerrit December 2024